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/* SPDX-License-Identifier: GPL-2.0 */
/*
* mt8196-afe-common.h -- Mediatek 8196 audio driver definitions
*
* Copyright (c) 2025 MediaTek Inc.
* Author: Darren Ye <darren.ye@mediatek.com>
*/
#ifndef _MT_8196_AFE_COMMON_H_
#define _MT_8196_AFE_COMMON_H_
#include <sound/pcm.h>
#include <sound/soc.h>
#include "mt8196-reg.h"
#include "../common/mtk-base-afe.h"
/* HW IPM 2.0 */
enum {
MTK_AFE_IPM2P0_RATE_8K = 0x0,
MTK_AFE_IPM2P0_RATE_11K = 0x1,
MTK_AFE_IPM2P0_RATE_12K = 0x2,
MTK_AFE_IPM2P0_RATE_16K = 0x4,
MTK_AFE_IPM2P0_RATE_22K = 0x5,
MTK_AFE_IPM2P0_RATE_24K = 0x6,
MTK_AFE_IPM2P0_RATE_32K = 0x8,
MTK_AFE_IPM2P0_RATE_44K = 0x9,
MTK_AFE_IPM2P0_RATE_48K = 0xa,
MTK_AFE_IPM2P0_RATE_88K = 0xd,
MTK_AFE_IPM2P0_RATE_96K = 0xe,
MTK_AFE_IPM2P0_RATE_176K = 0x11,
MTK_AFE_IPM2P0_RATE_192K = 0x12,
MTK_AFE_IPM2P0_RATE_352K = 0x15,
MTK_AFE_IPM2P0_RATE_384K = 0x16,
};
enum {
MTKAIF_PROTOCOL_1,
MTKAIF_PROTOCOL_2,
MTKAIF_PROTOCOL_2_CLK_P2,
};
enum {
MT8196_MEMIF_DL0,
MT8196_MEMIF_DL1,
MT8196_MEMIF_DL2,
MT8196_MEMIF_DL3,
MT8196_MEMIF_DL4,
MT8196_MEMIF_DL5,
MT8196_MEMIF_DL6,
MT8196_MEMIF_DL7,
MT8196_MEMIF_DL8,
MT8196_MEMIF_DL23,
MT8196_MEMIF_DL24,
MT8196_MEMIF_DL25,
MT8196_MEMIF_DL26,
MT8196_MEMIF_DL_4CH,
MT8196_MEMIF_DL_24CH,
MT8196_MEMIF_VUL0,
MT8196_MEMIF_VUL1,
MT8196_MEMIF_VUL2,
MT8196_MEMIF_VUL3,
MT8196_MEMIF_VUL4,
MT8196_MEMIF_VUL5,
MT8196_MEMIF_VUL6,
MT8196_MEMIF_VUL7,
MT8196_MEMIF_VUL8,
MT8196_MEMIF_VUL9,
MT8196_MEMIF_VUL10,
MT8196_MEMIF_VUL24,
MT8196_MEMIF_VUL25,
MT8196_MEMIF_VUL26,
MT8196_MEMIF_VUL_CM0,
MT8196_MEMIF_VUL_CM1,
MT8196_MEMIF_VUL_CM2,
MT8196_MEMIF_ETDM_IN0,
MT8196_MEMIF_ETDM_IN1,
MT8196_MEMIF_ETDM_IN2,
MT8196_MEMIF_ETDM_IN3,
MT8196_MEMIF_ETDM_IN4,
MT8196_MEMIF_ETDM_IN6,
MT8196_MEMIF_HDMI,
MT8196_MEMIF_NUM,
MT8196_DAI_ADDA = MT8196_MEMIF_NUM,
MT8196_DAI_ADDA_CH34,
MT8196_DAI_ADDA_CH56,
MT8196_DAI_AP_DMIC,
MT8196_DAI_AP_DMIC_CH34,
MT8196_DAI_AP_DMIC_MULTICH,
MT8196_DAI_I2S_IN0,
MT8196_DAI_I2S_IN1,
MT8196_DAI_I2S_IN2,
MT8196_DAI_I2S_IN3,
MT8196_DAI_I2S_IN4,
MT8196_DAI_I2S_IN6,
MT8196_DAI_I2S_OUT0,
MT8196_DAI_I2S_OUT1,
MT8196_DAI_I2S_OUT2,
MT8196_DAI_I2S_OUT3,
MT8196_DAI_I2S_OUT4,
MT8196_DAI_I2S_OUT6,
MT8196_DAI_FM_I2S_MASTER,
MT8196_DAI_TDM,
MT8196_DAI_TDM_DPTX,
MT8196_DAI_NUM,
};
#define MT8196_DAI_I2S_MAX_NUM 13 //depends each platform's max i2s num
/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
enum {
MT8196_IRQ_0,
MT8196_IRQ_1,
MT8196_IRQ_2,
MT8196_IRQ_3,
MT8196_IRQ_4,
MT8196_IRQ_5,
MT8196_IRQ_6,
MT8196_IRQ_7,
MT8196_IRQ_8,
MT8196_IRQ_9,
MT8196_IRQ_10,
MT8196_IRQ_11,
MT8196_IRQ_12,
MT8196_IRQ_13,
MT8196_IRQ_14,
MT8196_IRQ_15,
MT8196_IRQ_16,
MT8196_IRQ_17,
MT8196_IRQ_18,
MT8196_IRQ_19,
MT8196_IRQ_20,
MT8196_IRQ_21,
MT8196_IRQ_22,
MT8196_IRQ_23,
MT8196_IRQ_24,
MT8196_IRQ_25,
MT8196_IRQ_26,
MT8196_IRQ_31, /* used only for TDM */
MT8196_IRQ_NUM,
};
/* update irq ID (= enum) from AFE_IRQ_MCU_STATUS */
enum {
MT8196_CUS_IRQ_TDM, /* used only for TDM */
MT8196_CUS_IRQ_NUM,
};
enum {
/* AUDIO_ENGEN_CON0 */
MT8196_AUDIO_26M_EN_ON,
MT8196_AUDIO_F3P25M_EN_ON,
MT8196_AUDIO_APLL1_EN_ON,
MT8196_AUDIO_APLL2_EN_ON,
MT8196_AUDIO_F26M_EN_RST,
MT8196_MULTI_USER_RST,
MT8196_MULTI_USER_BYPASS,
/* AUDIO_TOP_CON4 */
MT8196_CG_AUDIO_HOPPING_CK,
MT8196_CG_AUDIO_F26M_CK,
MT8196_CG_APLL1_CK,
MT8196_CG_APLL2_CK,
MT8196_PDN_APLL_TUNER2,
MT8196_PDN_APLL_TUNER1,
MT8196_AUDIO_CG_NUM,
};
/* MCLK */
enum {
MT8196_I2SIN0_MCK,
MT8196_I2SIN1_MCK,
MT8196_FMI2S_MCK,
MT8196_TDMOUT_MCK,
MT8196_TDMOUT_BCK,
MT8196_MCK_NUM,
};
/* CM*/
enum {
CM0,
CM1,
CM2,
CM_NUM,
};
struct clk;
struct mtk_base_afe;
struct mt8196_afe_private {
struct clk **clk;
/* dai */
void *dai_priv[MT8196_DAI_NUM];
/* mck */
int mck_rate[MT8196_MCK_NUM];
/* channel merge */
u32 cm_rate[CM_NUM];
u32 cm_channels;
};
int mt8196_dai_adda_register(struct mtk_base_afe *afe);
int mt8196_dai_i2s_register(struct mtk_base_afe *afe);
int mt8196_dai_tdm_register(struct mtk_base_afe *afe);
int mt8196_dai_set_priv(struct mtk_base_afe *afe, int id,
int priv_size, const void *priv_data);
#endif
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