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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H
#define _DT_BINDINGS_CLK_QCOM_IPQ5332_CMN_PLL_H
/* CMN PLL core clock. */
#define IPQ5332_CMN_PLL_CLK 0
/* The output clocks from CMN PLL of IPQ5332. */
#define IPQ5332_XO_24MHZ_CLK 1
#define IPQ5332_SLEEP_32KHZ_CLK 2
#define IPQ5332_PCS_31P25MHZ_CLK 3
#define IPQ5332_NSS_300MHZ_CLK 4
#define IPQ5332_PPE_200MHZ_CLK 5
#define IPQ5332_ETH_50MHZ_CLK 6
#endif
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