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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_60_H_
#define QCOM_PHY_QMP_QSERDES_COM_V10_60_H_
/* Only for QMP V10_60 PHY - QSERDES COM registers */
#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1 0x00
#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1 0x04
#define QSERDES_V10_60_COM_CP_CTRL_MODE1 0x10
#define QSERDES_V10_60_COM_PLL_RCTRL_MODE1 0x14
#define QSERDES_V10_60_COM_PLL_CCTRL_MODE1 0x18
#define QSERDES_V10_60_COM_CORECLK_DIV_MODE1 0x1c
#define QSERDES_V10_60_COM_LOCK_CMP1_MODE1 0x20
#define QSERDES_V10_60_COM_LOCK_CMP2_MODE1 0x24
#define QSERDES_V10_60_COM_DEC_START_MODE1 0x28
#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1 0x30
#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1 0x34
#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1 0x38
#define QSERDES_V10_60_COM_HSCLK_SEL_1 0x3c
#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0 0x60
#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0 0x64
#define QSERDES_V10_60_COM_CP_CTRL_MODE0 0x70
#define QSERDES_V10_60_COM_PLL_RCTRL_MODE0 0x74
#define QSERDES_V10_60_COM_PLL_CCTRL_MODE0 0x78
#define QSERDES_V10_60_COM_CORECLK_DIV_MODE0 0x7c
#define QSERDES_V10_60_COM_LOCK_CMP1_MODE0 0x80
#define QSERDES_V10_60_COM_LOCK_CMP2_MODE0 0x84
#define QSERDES_V10_60_COM_DEC_START_MODE0 0x88
#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0 0x90
#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0 0x94
#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0 0x98
#define QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
#define QSERDES_V10_60_COM_BG_TIMER 0xbc
#define QSERDES_V10_60_COM_SSC_PER1 0xcc
#define QSERDES_V10_60_COM_SSC_PER2 0xd0
#define QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN 0xdc
#define QSERDES_V10_60_COM_CLK_ENABLE1 0xe0
#define QSERDES_V10_60_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V10_60_COM_PLL_IVCO 0xf4
#define QSERDES_V10_60_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V10_60_COM_LOCK_CMP_EN 0x120
#define QSERDES_V10_60_COM_LOCK_CMP_CFG 0x124
#define QSERDES_V10_60_COM_VCO_TUNE_MAP 0x140
#define QSERDES_V10_60_COM_CLK_SELECT 0x164
#define QSERDES_V10_60_COM_CORE_CLK_EN 0x170
#define QSERDES_V10_60_COM_CMN_CONFIG_1 0x174
#define QSERDES_V10_60_COM_CMN_MISC1 0x184
#define QSERDES_V10_60_COM_CMN_MODE 0x188
#define QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL 0x198
#define QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO 0x2b4
#endif
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