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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2026, The Linux Foundation. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_PCS_UFS_V7_H_
#define QCOM_PHY_QMP_PCS_UFS_V7_H_
/* Only for QMP V7 PHY - UFS PCS registers */
#define QPHY_V7_PCS_UFS_PHY_START 0x000
#define QPHY_V7_PCS_UFS_POWER_DOWN_CONTROL 0x004
#define QPHY_V7_PCS_UFS_SW_RESET 0x008
#define QPHY_V7_PCS_UFS_PCS_CTRL1 0x01c
#define QPHY_V7_PCS_UFS_PLL_CNTL 0x028
#define QPHY_V7_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c
#define QPHY_V7_PCS_UFS_TX_HSGEAR_CAPABILITY 0x060
#define QPHY_V7_PCS_UFS_RX_HSGEAR_CAPABILITY 0x094
#define QPHY_V7_PCS_UFS_LINECFG_DISABLE 0x140
#define QPHY_V7_PCS_UFS_RX_SIGDET_CTRL2 0x150
#define QPHY_V7_PCS_UFS_READY_STATUS 0x16c
#define QPHY_V7_PCS_UFS_TX_MID_TERM_CTRL1 0x1b8
#define QPHY_V7_PCS_UFS_MULTI_LANE_CTRL1 0x1c0
#endif
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