1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
|
// SPDX-License-Identifier: GPL-2.0
/*
* Original all-in-one devicetree:
* Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
* Rewritten to use includes:
* Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
*/
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-m100pfs-fabric.dtsi"
/ {
model = "Aries Embedded M100PFEVPS";
compatible = "aries,m100pfsevp", "microchip,mpfs";
aliases {
ethernet0 = &mac0;
ethernet1 = &mac1;
serial0 = &mmuart0;
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
serial4 = &mmuart4;
gpio0 = &gpio0;
gpio1 = &gpio2;
};
chosen {
stdout-path = "serial1:115200n8";
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
};
ddrc_cache_hi: memory@1040000000 {
device_type = "memory";
reg = <0x10 0x40000000 0x0 0x40000000>;
};
};
&can0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&irqmux {
interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
<12 &plic 25>, <13 &plic 26>,
<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
<94 &plic 53>, <95 &plic 53>;
};
&gpio0 {
ngpios = <14>;
status = "okay";
pmic-irq-hog {
gpio-hog;
gpios = <13 0>;
input;
};
/* Set to low for eMMC, high for SD-card */
mmc-sel-hog {
gpio-hog;
gpios = <12 0>;
output-high;
};
};
&gpio2 {
status = "okay";
};
&mac0 {
status = "okay";
phy-mode = "gmii";
phy-handle = <&phy0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&mac1 {
status = "okay";
phy-mode = "gmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@0 {
reg = <0>;
};
};
&mbox {
status = "okay";
};
&mmc {
max-frequency = <50000000>;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
no-1-8-v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
disable-wp;
status = "okay";
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&pcie {
status = "okay";
};
&qspi {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&usb {
status = "okay";
dr_mode = "host";
};
|
