1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
|
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
*/
#include <dt-bindings/clock/canaan,k230-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/canaan,k230-rst.h>
#include "k230-pinctrl.h"
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "canaan,kendryte-k230";
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <27000000>;
cpu@0 {
compatible = "thead,c908", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihpm_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
"zicbop", "zicboz", "zicntr", "zicsr", "zifencei",
"zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zvfh",
"svpbmt";
riscv,cbom-block-size = <64>;
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
d-cache-block-size = <64>;
d-cache-sets = <128>;
d-cache-size = <32768>;
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <32768>;
next-level-cache = <&l2_cache>;
mmu-type = "riscv,sv39";
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
l2_cache: l2-cache {
compatible = "cache";
cache-block-size = <64>;
cache-level = <2>;
cache-size = <262144>;
cache-sets = <256>;
cache-unified;
};
};
osc24m: clock-24000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc24m";
};
soc {
compatible = "simple-bus";
interrupt-parent = <&plic>;
#address-cells = <2>;
#size-cells = <2>;
dma-noncoherent;
ranges;
plic: interrupt-controller@f00000000 {
compatible = "canaan,k230-plic", "thead,c900-plic";
reg = <0xf 0x00000000 0x0 0x04000000>;
interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <2>;
riscv,ndev = <208>;
};
clint: timer@f04000000 {
compatible = "canaan,k230-clint", "thead,c900-clint";
reg = <0xf 0x04000000 0x0 0x00010000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
};
rst: reset-controller@91101000 {
compatible = "canaan,k230-rst";
reg = <0x0 0x91101000 0x0 0x1000>;
#reset-cells = <1>;
};
pinctrl: pinctrl@91105000 {
compatible = "canaan,k230-pinctrl";
reg = <0x0 0x91105000 0x0 0x100>;
};
sysclk: clock-controller@91102000 {
compatible = "canaan,k230-clk";
reg = <0x0 0x91102000 0x0 0x40>,
<0x0 0x91100000 0x0 0x108>;
clocks = <&osc24m>;
clock-names = "osc24m";
#clock-cells = <1>;
};
uart0: serial@91400000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91400000 0x0 0x1000>;
clocks = <&sysclk K230_LS_UART0_RATE>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
resets = <&rst RST_UART0>;
status = "disabled";
};
uart1: serial@91401000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91401000 0x0 0x1000>;
clocks = <&sysclk K230_LS_UART1_RATE>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
resets = <&rst RST_UART1>;
status = "disabled";
};
uart2: serial@91402000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91402000 0x0 0x1000>;
clocks = <&sysclk K230_LS_UART2_RATE>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
resets = <&rst RST_UART2>;
status = "disabled";
};
uart3: serial@91403000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91403000 0x0 0x1000>;
clocks = <&sysclk K230_LS_UART3_RATE>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
resets = <&rst RST_UART3>;
status = "disabled";
};
uart4: serial@91404000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x91404000 0x0 0x1000>;
clocks = <&sysclk K230_LS_UART4_RATE>;
interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
reg-io-width = <4>;
reg-shift = <2>;
resets = <&rst RST_UART4>;
status = "disabled";
};
};
};
|
