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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the Ironhide board
*
* Copyright (C) 2025 Renesas Electronics Corp.
*/
/dts-v1/;
#include <dt-bindings/soc/renesas,r8a78000-mfis.h>
#include "r8a78000.dtsi"
/ {
model = "Renesas Ironhide board based on r8a78000";
compatible = "renesas,ironhide", "renesas,r8a78000";
aliases {
serial0 = &hscif0;
};
chosen {
stdout-path = "serial0:1843200n8";
};
firmware {
scmi: scmi {
compatible = "arm,scmi";
mboxes = <&mfis_scp 2 MFIS_CHANNEL_TX>,
<&mfis_scp 2 MFIS_CHANNEL_RX>;
mbox-names = "tx", "rx";
shmem = <&scmi_tx_shmem>, <&scmi_rx_shmem>;
arm,no-completion-irq;
#address-cells = <1>;
#size-cells = <0>;
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x80000000>;
};
memory@1080000000 {
device_type = "memory";
reg = <0x10 0x80000000 0x0 0x80000000>;
};
memory@1200000000 {
device_type = "memory";
reg = <0x12 0x00000000 0x1 0x00000000>;
};
memory@1400000000 {
device_type = "memory";
reg = <0x14 0x00000000 0x1 0x00000000>;
};
memory@1600000000 {
device_type = "memory";
reg = <0x16 0x00000000 0x1 0x00000000>;
};
memory@1800000000 {
device_type = "memory";
reg = <0x18 0x00000000 0x1 0x00000000>;
};
memory@1a00000000 {
device_type = "memory";
reg = <0x1a 0x00000000 0x1 0x00000000>;
};
memory@1c00000000 {
device_type = "memory";
reg = <0x1c 0x00000000 0x1 0x00000000>;
};
memory@1e00000000 {
device_type = "memory";
reg = <0x1e 0x00000000 0x1 0x00000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
/* First 518 MiB is reserved for other purposes. */
firmware@40000000 {
reg = <0x0 0x40000000 0x0 0x20600000>;
no-map;
};
/* Parameters set by IPL. */
parameters@8c100000 {
reg = <0x0 0x8c100000 0x0 0x00008000>;
no-map;
};
/* TFA BL31. */
tfa-bl31@8c200000 {
reg = <0x0 0x8c200000 0x0 0x00080000>;
no-map;
};
/* TEE TZ DRAM. */
tee@8c400000 {
reg = <0x0 0x8c400000 0x0 0x02000000>;
no-map;
};
/* DRAM controller inline ECC areas */
ecc@10cccc0000 {
reg = <0x10 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@12cccc0000 {
reg = <0x12 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@14cccc0000 {
reg = <0x14 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@16cccc0000 {
reg = <0x16 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@18cccc0000 {
reg = <0x18 0xcccc0000 0x0 0x33340000>;
no-map;
};
ecc@1a66660000 {
reg = <0x1a 0x66660000 0x0 0x999a0000>;
no-map;
};
ecc@1c66660000 {
reg = <0x1c 0x66660000 0x0 0x999a0000>;
no-map;
};
ecc@1e66660000 {
reg = <0x1e 0x66660000 0x0 0x999a0000>;
no-map;
};
};
};
&extal_clk {
clock-frequency = <16666600>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
uart-has-rtscts;
status = "okay";
};
&mfis_scp {
status = "okay";
};
&scif_clk {
clock-frequency = <26000000>;
};
&stcm_transport {
scmi_tx_shmem: sram@1200 {
compatible = "arm,scmi-shmem";
reg = <0x1200 0x0100>;
};
scmi_rx_shmem: sram@1300 {
compatible = "arm,scmi-shmem";
reg = <0x1300 0x100>;
};
};
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