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// SPDX-License-Identifier: BSD-3-Clause
/*
* IPQ5332 RDP board common device tree source
*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include "ipq5332.dtsi"
/ {
aliases {
serial0 = &blsp1_uart0;
};
chosen {
stdout-path = "serial0";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&gpio_keys_default>;
pinctrl-names = "default";
button-wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&gpio_leds_default>;
pinctrl-names = "default";
led-0 {
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WLAN;
gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx";
default-state = "off";
};
};
};
&blsp1_uart0 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
/*
* The bootstrap pins for the board select the XO clock frequency that
* supports 48 MHZ or 96 MHZ. This setting automatically enables the
* right dividers, to ensure the reference clock output from WiFi to
* the CMN PLL is 48 MHZ.
*/
&ref_48mhz_clk {
clock-div = <1>;
clock-mult = <1>;
};
&sleep_clk {
clock-frequency = <32000>;
};
/*
* The frequency of xo_board is fixed to 24 MHZ, which is routed
* from WiFi output clock 48 MHZ divided by 2.
*/
&xo_board {
clock-div = <2>;
clock-mult = <1>;
};
&xo_clk {
clock-frequency = <48000000>;
};
/* PINCTRL */
&tlmm {
gpio_keys_default: gpio-keys-default-state {
pins = "gpio35";
function = "gpio";
drive-strength = <8>;
bias-pull-up;
};
gpio_leds_default: gpio-leds-default-state {
pins = "gpio36";
function = "gpio";
drive-strength = <8>;
bias-pull-down;
};
qpic_snand_default_state: qpic-snand-default-state {
clock-pins {
pins = "gpio13";
function = "qspi_clk";
drive-strength = <8>;
bias-disable;
};
cs-pins {
pins = "gpio12";
function = "qspi_cs";
drive-strength = <8>;
bias-disable;
};
data-pins {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "qspi_data";
drive-strength = <8>;
bias-disable;
};
};
};
&qpic_bam {
status = "okay";
};
&qpic_nand {
pinctrl-0 = <&qpic_snand_default_state>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
nand-ecc-engine = <&qpic_nand>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
};
};
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