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|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite DART-MX95
*
* Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-95/dart-mx95/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/usb/pd.h>
#include "imx95.dtsi"
/ {
model = "Variscite DART-MX95 Module";
compatible = "variscite,var-dart-mx95", "fsl,imx95";
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <1800000>;
regulator-name = "+V1.8_SW";
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SW";
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_audio: regulator-audio-vdd {
compatible = "regulator-fixed";
regulator-name = "wm8904_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reserved-memory {
ranges;
#address-cells = <2>;
#size-cells = <2>;
linux_cma: linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x80000000 0 0x7F000000>;
reusable;
size = <0 0x3c000000>;
linux,cma-default;
};
};
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio2 27 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
};
&adc1 {
vref-supply = <®_vref_1v8>;
status = "okay";
};
&enetc_port0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enetc0>;
phy-handle = <ðphy0>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
status = "okay";
};
&lpi2c8 {
clock-frequency = <400000>;
pinctrl-names = "default","gpio","sleep";
pinctrl-0 = <&pinctrl_lpi2c8>;
pinctrl-1 = <&pinctrl_lpi2c8_gpio>;
pinctrl-2 = <&pinctrl_lpi2c8_gpio>;
scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&scmi_clk IMX95_CLK_SAI3>;
clock-names = "mclk";
AVDD-supply = <®_audio>;
CPVDD-supply = <®_audio>;
DBVDD-supply = <®_audio>;
DCVDD-supply = <®_audio>;
MICVDD-supply = <®_audio>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
/* DMIC is connected to IN1L */
wlf,in1l-as-dmicdat1;
};
};
/* BT */
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&mu7 {
status = "okay";
};
&netc_blk_ctrl {
status = "okay";
};
&netc_emdio {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emdio>, <&pinctrl_phy0res>;
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio5 16 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_YELLOW>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
linux,default-trigger = "netdev";
};
};
};
};
&netc_timer {
status = "okay";
};
&netcmix_blk_ctrl {
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>,
<&scmi_clk IMX95_CLK_AUDIOPLL2>,
<&scmi_clk IMX95_CLK_SAI3>;
assigned-clock-parents = <0>, <0>, <0>, <0>,
<&scmi_clk IMX95_CLK_AUDIOPLL1>;
assigned-clock-rates = <3932160000>,
<3612672000>, <393216000>,
<361267200>, <12288000>;
#sound-dai-cells = <0>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
pinctrl-3 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
no-sdio;
no-sd;
status = "okay";
};
/* WiFi */
&usdhc3 {
pinctrl-names = "default","state_100mhz","state_200mhz","sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-3 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
non-removable;
wakeup-source;
keep-power-in-suspend;
status = "okay";
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
};
&scmi_iomuxc {
pinctrl_bt: btgrp {
fsl,pins = <
IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e
>;
};
pinctrl_emdio: emdiogrp {
fsl,pins = <
IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x57e
IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e
>;
};
pinctrl_enetc0: enetc0grp {
fsl,pins = <
IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e
IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e
IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e
IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e
IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e
IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e
IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e
IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e
IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e
IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e
IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e
IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e
>;
};
pinctrl_lpi2c8: lpi2c8grp {
fsl,pins = <
IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x40000b9e
IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x40000b9e
>;
};
pinctrl_lpi2c8_gpio: lpi2c8gpiogrp {
fsl,pins = <
IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e
IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e
>;
};
pinctrl_phy0res: phy0resgrp {
fsl,pins = <
IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e
IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e
IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x31e
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
IMX95_PAD_GPIO_IO00__LPUART5_TX 0x31e
IMX95_PAD_GPIO_IO01__LPUART5_RX 0x31e
IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x31e
IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe
IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe
IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc3_gpio: usdhc3gpiogrp {
fsl,pins = <
IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x31e
IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x31e
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe
IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe
IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
};
|
