1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
|
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Common dtsi for Variscite VAR-SOM-MX91
*
* Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/var-som-mx91/
*
* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
*
*/
/dts-v1/;
#include "imx91.dtsi"
/{
model = "Variscite VAR-SOM-MX91 module";
compatible = "variscite,var-som-mx91", "fsl,imx91";
usdhc3_pwrseq: mmc-pwrseq {
compatible = "mmc-pwrseq-simple";
post-power-on-delay-ms = <100>;
power-off-delay-us = <10000>;
reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"IN1L", "Microphone Jack",
"IN1R", "Microphone Jack";
simple-audio-card,widgets =
"Microphone", "Microphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
simple-audio-card,mclk-fs = <256>;
codec_dai: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
};
};
&eqos {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-1 = <&pinctrl_eqos_sleep>;
/*
* The required RGMII TX and RX 2ns delays are implemented directly
* in hardware via passive delay elements on the SOM PCB.
* No delay configuration is needed in software via PHY driver.
*/
phy-mode = "rgmii";
phy-handle = <ðphy0>;
snps,clk-csr = <5>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
eee-broken-1000t;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
reset-assert-us = <15000>;
reset-deassert-us = <100000>;
};
};
};
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep", "gpio";
pinctrl-0 = <&pinctrl_lpi2c3>;
pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
scl-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9451a";
reg = <0x25>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <650000>;
regulator-max-microvolt = <2237500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&clk IMX93_CLK_SAI1_GATE>;
clock-names = "mclk";
AVDD-supply = <&buck5>;
CPVDD-supply = <&buck5>;
DBVDD-supply = <&buck4>;
DCVDD-supply = <&buck5>;
MICVDD-supply = <&buck5>;
wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
"soft", "music";
/*
* Config registers per name, respectively:
* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
*/
wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
/* GPIO1 = DMIC_CLK, don't touch others */
wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
};
};
&lpspi8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpspi8>;
cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
/* BT module */
&lpuart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "nxp,88w8987-bt";
};
};
&sai1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai1>;
pinctrl-1 = <&pinctrl_sai1_sleep>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
/* WiFi */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
bus-width = <4>;
keep-power-in-suspend;
mmc-pwrseq = <&usdhc3_pwrseq>;
non-removable;
wakeup-source;
status = "okay";
};
&iomuxc {
pinctrl_bluetooth: bluetoothgrp {
fsl,pins = <
MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
>;
};
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e
>;
};
pinctrl_eqos_sleep: eqos-sleepgrp {
fsl,pins = <
MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
>;
};
pinctrl_lpi2c3: lpi2c3grp {
fsl,pins = <
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
>;
};
pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {
fsl,pins = <
MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e
MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e
>;
};
pinctrl_lpspi8: lpspi8grp {
fsl,pins = <
MX91_PAD_GPIO_IO12__GPIO2_IO12 0x31e
MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x31e
MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e
MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x31e
>;
};
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e
MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e
MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e
MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e
>;
};
pinctrl_sai1_sleep: sai1-sleepgrp {
fsl,pins = <
MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e
MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e
MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e
MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e
MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e
MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e
MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
>;
};
pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
fsl,pins = <
MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
>;
};
pinctrl_usdhc3_wlan: usdhc3-wlangrp {
fsl,pins = <
MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e
>;
};
};
|
