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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2026 Cix Technology Group Co., Ltd.
*/
#ifndef __SKY1_POWER_H__
#define __SKY1_POWER_H__
/* The Rich OS need flow the macro */
#define SKY1_PD_AUDIO 0
#define SKY1_PD_PCIE_CTRL0 1
#define SKY1_PD_PCIE_DUMMY 2
#define SKY1_PD_PCIEHUB 3
#define SKY1_PD_MMHUB 4
#define SKY1_PD_MMHUB_SMMU 5
#define SKY1_PD_DPU0 6
#define SKY1_PD_DPU1 7
#define SKY1_PD_DPU2 8
#define SKY1_PD_DPU3 9
#define SKY1_PD_DPU4 10
#define SKY1_PD_VPU_TOP 11
#define SKY1_PD_VPU_CORE0 12
#define SKY1_PD_VPU_CORE1 13
#define SKY1_PD_VPU_CORE2 14
#define SKY1_PD_VPU_CORE3 15
#define SKY1_PD_NPU_CORE0 16
#define SKY1_PD_NPU_CORE1 17
#define SKY1_PD_NPU_CORE2 18
#define SKY1_PD_NPU_TOP 19
#define SKY1_PD_ISP0 20
#define SKY1_PD_GPU 21
#define SKY1_PERF_GPU_CORE 0
#define SKY1_PERF_GPU_TOP 1
#define SKY1_PERF_CPU_L 2
#define SKY1_PERF_CPU_B0 3
#define SKY1_PERF_CPU_B1 4
#define SKY1_PERF_CPU_M0 5
#define SKY1_PERF_CPU_M1 6
#define SKY1_PERF_DSU 7
#define SKY1_PERF_NPU 8
#define SKY1_PERF_VPU 9
#define SKY1_PERF_CI700 10
#define SKY1_PERF_NI700 11
#endif
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