path: root/arch/arm/boot/dts/renesas/r9a06g032.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
 *
 * Copyright (C) 2018 Renesas Electronics Europe Limited
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a06g032-sysctrl.h>

/ {
	compatible = "renesas,r9a06g032";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&gic>;

	/*
	 * The CPUs clock is based on the 'ref' clock (output of OPPDIV divisor)
	 * with x1, x2 or x4 ratio between the CPUs clock frequency and this
	 * 'ref' clock frequency.
	 *
	 * The table below is built on the assumption that the 'ref' clock
	 * frequency is set to 500MHz which is its default value.
	 *
	 * The table should be overridden in the board device-tree file based
	 * on the 'ref' clock frequency if this frequency value is not the
	 * default one.
	 */
	cpu_opp_table: opp-table-cpu {
		compatible = "operating-points-v2";
		opp-shared;

		opp-125000000 {
			opp-hz = /bits/ 64 <125000000>;
			/* ~35 clocks cycles at 125mhz */
			clock-latency-ns = <300>;
		};

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};

		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
			operating-points-v2 = <&cpu_opp_table>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <1>;
			clocks = <&sysctrl R9A06G032_CLK_A7MP>;
			enable-method = "renesas,r9a06g032-smp";
			cpu-release-addr = <0 0x4000c204>;
			operating-points-v2 = <&cpu_opp_table>;
		};
	};

	ext_jtag_clk: extjtagclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_mclk: extmclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <40000000>;
	};

	ext_rgmii_ref: extrgmiiref {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	ext_rtc_clk: extrtcclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		qspi0: spi@40005000 {
			compatible = "renesas,r9a06g032-qspi", "renesas,rzn1-qspi";
			reg = <0x40005000 0x1000>, <0x10000000 0x10000000>;
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_CLK_QSPI0>, <&sysctrl R9A06G032_HCLK_QSPI0>,
				 <&sysctrl R9A06G032_HCLK_QSPI0>;
			clock-names = "ref", "ahb", "apb";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		rtc0: rtc@40006000 {
			compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
			reg = <0x40006000 0x1000>;
			interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
				     <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "alarm", "timer", "pps";
			clocks = <&sysctrl R9A06G032_HCLK_RTC>, <&ext_rtc_clk>;
			clock-names = "hclk", "xtal";
			power-domains = <&sysctrl>;
			status = "disabled";
		};

		wdt0: watchdog@40008000 {
			compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
			reg = <0x40008000 0x1000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
			status = "disabled";
		};

		wdt1: watchdog@40009000 {
			compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
			reg = <0x40009000 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
			clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
			status = "disabled";
		};

		sysctrl: system-controller@4000c000 {
			compatible = "renesas,r9a06g032-sysctrl";
			reg = <0x4000c000 0x1000>;
			status = "okay";
			#clock-cells = <1>;
			#power-domain-cells = <0>;

			clocks = <&ext_mclk>, <&ext_rtc_clk>,
					<&ext_jtag_clk>, <&ext_rgmii_ref>;
			clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
			#address-cells = <1>;
			#size-cells = <1>;

			dmamux: dma-router@a0 {
				compatible = "renesas,rzn1-dmamux";
				reg = <0xa0 4>;
				#dma-cells = <6>;
				dma-requests = <32>;
				dma-masters = <&dma0 &dma1>;
			};
		};

		udc: usb@4001e000 {
			compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf";
			reg = <0x4001e000 0x2000>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_USBF>,
				 <&sysctrl R9A06G032_HCLK_USBPM>;
			clock-names = "hclkf", "hclkpm";
			power-domains = <&sysctrl>;
			status = "disabled";
		};

		pci_usb: pci@40030000 {
			compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
			device_type = "pci";
			clocks = <&sysctrl R9A06G032_HCLK_USBH>,
				 <&sysctrl R9A06G032_HCLK_USBPM>,
				 <&sysctrl R9A06G032_CLK_PCI_USB>;
			clock-names = "hclkh", "hclkpm", "pciclk";
			power-domains = <&sysctrl>;
			reg = <0x40030000 0xc00>,
			      <0x40020000 0x1100>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";

			bus-range = <0 0>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
			/* Should map all possible DDR as inbound ranges, but
			 * the IP only supports a 256MB, 512MB, or 1GB window.
			 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
			 */
			dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
			interrupt-map-mask = <0xf800 0 0 0x7>;
			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
					 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
					 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;

			usb@1,0 {
				reg = <0x800 0 0 0 0>;
				phys = <&usbphy>;
				phy-names = "usb";
			};

			usb@2,0 {
				reg = <0x1000 0 0 0 0>;
				phys = <&usbphy>;
				phy-names = "usb";
			};
		};

		uart0: serial@40060000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40060000 0x400>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart1: serial@40061000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40061000 0x400>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart2: serial@40062000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart";
			reg = <0x40062000 0x400>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
			clock-names = "baudclk", "apb_pclk";
			status = "disabled";
		};

		uart3: serial@50000000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50000000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart4: serial@50001000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50001000 0x400>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart5: serial@50002000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50002000 0x400>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart6: serial@50003000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50003000 0x400>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		uart7: serial@50004000 {
			compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart";
			reg = <0x50004000 0x400>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
			clock-names = "baudclk", "apb_pclk";
			dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		i2c1: i2c@40063000 {
			compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c";
			reg = <0x40063000 0x100>;
			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_I2C0>, <&sysctrl R9A06G032_CLK_I2C0>;
			clock-names = "ref", "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@40064000 {
			compatible = "renesas,r9a06g032-i2c", "renesas,rzn1-i2c", "snps,designware-i2c";
			reg = <0x40064000 0x100>;
			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_I2C1>, <&sysctrl R9A06G032_CLK_I2C1>;
			clock-names = "ref", "pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		adc: adc@40065000 {
			compatible = "renesas,r9a06g032-adc", "renesas,rzn1-adc";
			reg = <0x40065000 0x200>;
			clocks = <&sysctrl R9A06G032_HCLK_ADC>, <&sysctrl R9A06G032_CLK_ADC>;
			clock-names = "pclk", "adc";
			power-domains = <&sysctrl>;
			#io-channel-cells = <1>;
			status = "disabled";
		};

		pinctrl: pinctrl@40067000 {
			compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl";
			reg = <0x40067000 0x1000>, <0x51000000 0x480>;
			clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
			clock-names = "bus";
			status = "okay";
		};

		sdio1: mmc@40100000 {
			compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a";
			reg = <0x40100000 0x1000>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int", "wakeup";
			clocks = <&sysctrl R9A06G032_CLK_SDIO0>, <&sysctrl R9A06G032_HCLK_SDIO0>;
			clock-names = "clk_xin", "clk_ahb";
			no-1-8-v;
			status = "disabled";
		};

		sdio2: mmc@40101000 {
			compatible = "renesas,r9a06g032-sdhci", "renesas,rzn1-sdhci", "arasan,sdhci-8.9a";
			reg = <0x40101000 0x1000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "int", "wakeup";
			clocks = <&sysctrl R9A06G032_CLK_SDIO1>, <&sysctrl R9A06G032_HCLK_SDIO1>;
			clock-names = "clk_xin", "clk_ahb";
			no-1-8-v;
			status = "disabled";
		};

		nand_controller: nand-controller@40102000 {
			compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc";
			reg = <0x40102000 0x2000>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
			clock-names = "hclk", "eclk";
			power-domains = <&sysctrl>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		dma0: dma-controller@40104000 {
			compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
			reg = <0x40104000 0x1000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "hclk";
			clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
			dma-channels = <8>;
			dma-requests = <16>;
			dma-masters = <1>;
			#dma-cells = <3>;
			block_size = <0xfff>;
			data-width = <8>;
		};

		dma1: dma-controller@40105000 {
			compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
			reg = <0x40105000 0x1000>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "hclk";
			clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
			dma-channels = <8>;
			dma-requests = <16>;
			dma-masters = <1>;
			#dma-cells = <3>;
			block_size = <0xfff>;
			data-width = <8>;
		};

		gmac1: ethernet@44000000 {
			compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
			reg = <0x44000000 0x2000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			clocks = <&sysctrl R9A06G032_HCLK_GMAC0>;
			clock-names = "stmmaceth";
			power-domains = <&sysctrl>;
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <2048>;
			rx-fifo-depth = <4096>;
			pcs-handle = <&mii_conv1>;
			status = "disabled";
		};

		gmac2: ethernet@44002000 {
			compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac";
			reg = <0x44002000 0x2000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
			clock-names = "stmmaceth";
			power-domains = <&sysctrl>;
			snps,multicast-filter-bins = <256>;
			snps,perfect-filter-entries = <128>;
			tx-fifo-depth = <2048>;
			rx-fifo-depth = <4096>;
			status = "disabled";
		};

		eth_miic: eth-miic@44030000 {
			compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x44030000 0x10000>;
			clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
				 <&sysctrl R9A06G032_CLK_RGMII_REF>,
				 <&sysctrl R9A06G032_CLK_RMII_REF>,
				 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
			clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
			power-domains = <&sysctrl>;
			status = "disabled";

			mii_conv1: mii-conv@1 {
				reg = <1>;
				status = "disabled";
			};

			mii_conv2: mii-conv@2 {
				reg = <2>;
				status = "disabled";
			};

			mii_conv3: mii-conv@3 {
				reg = <3>;
				status = "disabled";
			};

			mii_conv4: mii-conv@4 {
				reg = <4>;
				status = "disabled";
			};

			mii_conv5: mii-conv@5 {
				reg = <5>;
				status = "disabled";
			};
		};

		switch: switch@44050000 {
			compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";
			reg = <0x44050000 0x10000>;
			clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
				 <&sysctrl R9A06G032_CLK_SWITCH>;
			clock-names = "hclk", "clk";
			power-domains = <&sysctrl>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dlr", "switch", "prp", "hub", "ptrn";
			status = "disabled";

			ethernet-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				switch_port0: port@0 {
					reg = <0>;
					pcs-handle = <&mii_conv5>;
					status = "disabled";
				};

				switch_port1: port@1 {
					reg = <1>;
					pcs-handle = <&mii_conv4>;
					status = "disabled";
				};

				switch_port2: port@2 {
					reg = <2>;
					pcs-handle = <&mii_conv3>;
					status = "disabled";
				};

				switch_port3: port@3 {
					reg = <3>;
					pcs-handle = <&mii_conv2>;
					status = "disabled";
				};

				switch_port4: port@4 {
					reg = <4>;
					ethernet = <&gmac2>;
					label = "cpu";
					phy-mode = "internal";
					status = "disabled";
					fixed-link {
						speed = <1000>;
						full-duplex;
					};
				};
			};
		};

		gic: interrupt-controller@44101000 {
			compatible = "arm,gic-400", "arm,cortex-a7-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			#address-cells = <0>;
			reg = <0x44101000 0x1000>, /* Distributer */
			      <0x44102000 0x2000>, /* CPU interface */
			      <0x44104000 0x2000>, /* Virt interface control */
			      <0x44106000 0x2000>; /* Virt CPU interface */
			interrupts =
				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		/* Controller only */
		spi1: spi@50005000 {
			compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
			reg = <0x50005000 0x200>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_CLK_SPI0>, <&sysctrl R9A06G032_HCLK_SPI0>;
			clock-names = "ssi_clk", "pclk";
			power-domains = <&sysctrl>;
			num-cs = <4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* Controller only */
		spi2: spi@50006000 {
			compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
			reg = <0x50006000 0x200>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_CLK_SPI1>, <&sysctrl R9A06G032_HCLK_SPI1>;
			clock-names = "ssi_clk", "pclk";
			power-domains = <&sysctrl>;
			num-cs = <4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* Controller only */
		spi3: spi@50007000 {
			compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
			reg = <0x50007000 0x200>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_CLK_SPI2>, <&sysctrl R9A06G032_HCLK_SPI2>;
			clock-names = "ssi_clk", "pclk";
			power-domains = <&sysctrl>;
			num-cs = <4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* Controller only */
		spi4: spi@50008000 {
			compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
			reg = <0x50008000 0x200>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_CLK_SPI3>, <&sysctrl R9A06G032_HCLK_SPI3>;
			clock-names = "ssi_clk", "pclk";
			power-domains = <&sysctrl>;
			num-cs = <4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* Target only */
		spi5: spi@50009000 {
			compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
			reg = <0x50009000 0x200>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_CLK_SPI4>, <&sysctrl R9A06G032_HCLK_SPI4>;
			clock-names = "ssi_clk", "pclk";
			power-domains = <&sysctrl>;
			spi-slave;
			#address-cells = <0>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* Target only */
		spi6: spi@5000a000 {
			compatible = "renesas,r9a06g032-spi", "renesas,rzn1-spi";
			reg = <0x5000a000 0x200>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_CLK_SPI5>, <&sysctrl R9A06G032_HCLK_SPI5>;
			clock-names = "ssi_clk", "pclk";
			power-domains = <&sysctrl>;
			spi-slave;
			#address-cells = <0>;
			#size-cells = <0>;
			status = "disabled";
		};

		/*
		 * The GPIO mapping to the corresponding pins is not obvious.
		 * See the hardware documentation for details.
		 */
		gpio0: gpio@5000b000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x5000b000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&sysctrl R9A06G032_HCLK_GPIO0>;
			clock-names = "bus";

			/* GPIO0a[0]      connected to pin  GPIO0      */
			/* GPIO0a[1..2]   connected to pins GPIO3..4   */
			/* GPIO0a[3..4]   connected to pins GPIO9..10  */
			/* GPIO0a[5]      connected to pin  GPIO12     */
			/* GPIO0a[6..7]   connected to pins GPIO15..16 */
			/* GPIO0a[8..9]   connected to pins GPIO21..22 */
			/* GPIO0a[10]     connected to pin  GPIO24     */
			/* GPIO0a[11..12] connected to pins GPIO27..28 */
			/* GPIO0a[13..14] connected to pins GPIO33..34 */
			/* GPIO0a[15]     connected to pin  GPIO36     */
			/* GPIO0a[16..17] connected to pins GPIO39..40 */
			/* GPIO0a[18..19] connected to pins GPIO45..46 */
			/* GPIO0a[20]     connected to pin  GPIO48     */
			/* GPIO0a[21..22] connected to pins GPIO51..52 */
			/* GPIO0a[23..24] connected to pins GPIO57..58 */
			/* GPIO0a[25..31] connected to pins GPIO62..68 */
			gpio0a: gpio-port@0 {
				compatible = "snps,dw-apb-gpio-port";
				reg = <0>;
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;

				interrupt-controller;
				interrupt-parent = <&gpioirqmux>;
				interrupts = < 0  1  2  3  4  5  6  7
					       8  9 10 11 12 13 14 15
					      16 17 18 19 20 21 22 23
					      24 25 26 27 28 29 30 31>;
				#interrupt-cells = <2>;
			};

			/* GPIO0b[0..1]   connected to pins GPIO1..2   */
			/* GPIO0b[2..5]   connected to pins GPIO5..8   */
			/* GPIO0b[6]      connected to pin  GPIO11     */
			/* GPIO0b[7..8]   connected to pins GPIO13..14 */
			/* GPIO0b[9..12]  connected to pins GPIO17..20 */
			/* GPIO0b[13]     connected to pin  GPIO23     */
			/* GPIO0b[14..15] connected to pins GPIO25..26 */
			/* GPIO0b[16..19] connected to pins GPIO29..32 */
			/* GPIO0b[20]     connected to pin  GPIO35     */
			/* GPIO0b[21..22] connected to pins GPIO37..38 */
			/* GPIO0b[23..26] connected to pins GPIO41..44 */
			/* GPIO0b[27]     connected to pin  GPIO47     */
			/* GPIO0b[28..29] connected to pins GPIO49..50 */
			/* GPIO0b[30..31] connected to pins GPIO53..54 */
			gpio0b: gpio-port@1 {
				compatible = "snps,dw-apb-gpio-port";
				reg = <1>;
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
			};
		};

		gpio1: gpio@5000c000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x5000c000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&sysctrl R9A06G032_HCLK_GPIO1>;
			clock-names = "bus";

			/* GPIO1a[0..4]  connected to pins GPIO69..73 */
			/* GPIO1a[5..31] connected to pins GPIO95..121 */
			gpio1a: gpio-port@0 {
				compatible = "snps,dw-apb-gpio-port";
				reg = <0>;
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;

				interrupt-controller;
				interrupt-parent = <&gpioirqmux>;
				interrupts = <32 33 34 35 36 37 38 39
					      40 41 42 43 44 45 46 47
					      48 49 50 51 52 53 54 55
					      56 57 58 59 60 61 62 63>;
				#interrupt-cells = <2>;
			};

			/* GPIO1b[0..1]   connected to pins GPIO55..56 */
			/* GPIO1b[2..4]   connected to pins GPIO59..61 */
			/* GPIO1b[5..25]  connected to pins GPIO74..94 */
			/* GPIO1b[26..31] connected to pins GPIO150..155 */
			gpio1b: gpio-port@1 {
				compatible = "snps,dw-apb-gpio-port";
				reg = <1>;
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
			};
		};

		gpio2: gpio@5000d000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0x5000d000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&sysctrl R9A06G032_HCLK_GPIO2>;
			clock-names = "bus";

			/* GPIO2a[0..27]  connected to pins GPIO122..149 */
			/* GPIO2a[28..31] connected to pins GPIO156..159 */
			gpio2a: gpio-port@0 {
				compatible = "snps,dw-apb-gpio-port";
				reg = <0>;
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;

				interrupt-controller;
				interrupt-parent = <&gpioirqmux>;
				interrupts = <64 65 66 67 68 69 70 71
					      72 73 74 75 76 77 78 79
					      80 81 82 83 84 85 86 87
					      88 89 90 91 92 93 94 95>;
				#interrupt-cells = <2>;
			};

			/* GPIO2b[0..9] connected to pins GPIO160..169 */
			gpio2b: gpio-port@1 {
				compatible = "snps,dw-apb-gpio-port";
				reg = <1>;
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <10>;
			};
		};

		gpioirqmux: interrupt-controller@51000480 {
			compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
			reg = <0x51000480 0x20>;
			#interrupt-cells = <1>;
			#address-cells = <0>;
			interrupt-map-mask = <0x7f>;

			/*
			 * Example mapping entry. Board DTs need to overwrite
			 * 'interrupt-map' with their specific mapping. Check
			 * the irqmux binding documentation for details.
			 */
			interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

			status = "disabled";
		};

		can0: can@52104000 {
			compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
			reg = <0x52104000 0x800>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
			power-domains = <&sysctrl>;
			status = "disabled";
		};

		can1: can@52105000 {
			compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
			reg = <0x52105000 0x800>;
			reg-io-width = <4>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
			power-domains = <&sysctrl>;
			status = "disabled";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		always-on;
		interrupts =
			<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
			<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys";
	};

	usbphy: usb-phy {
		#phy-cells = <0>;
		compatible = "usb-nop-xceiv";
		status = "disabled";
	};
};