blob: 67ad4f1eda8de0799954cb5a87df613ea53a2864 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/mpc8xxx-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale MPC8xxx watchdog timer (For 83xx, 86xx and 8xx)
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
properties:
compatible:
enum:
- mpc83xx_wdt # for an mpc83xx
- fsl,mpc8610-wdt # for an mpc86xx
- fsl,mpc823-wdt # for an mpc8xx
device_type:
const: watchdog
reg:
minItems: 1
items:
- description: |
Base physical address and length of the area hosting the watchdog
registers.
On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
On the 8xx, "General System Interface Unit" area: <0x0 0x10>
- description: |
Additional optional physical address and length (4) of location of
the Reset Status Register (called RSTRSCR on the mpc86xx)
On the 83xx, it is located at offset 0x910
On the 86xx, it is located at offset 0xe0094
On the 8xx, it is located at offset 0x288
required:
- compatible
- reg
allOf:
- $ref: watchdog.yaml#
additionalProperties: false
examples:
- |
watchdog@0 {
compatible = "fsl,mpc823-wdt";
reg = <0x0 0x10 0x288 0x4>;
};
- |
watchdog@200 {
compatible = "mpc83xx_wdt";
reg = <0x200 0x100>;
device_type = "watchdog";
};
...
|
