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|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mt8192-afe-pcm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek AFE PCM controller for mt8192
maintainers:
- Jiaxin Yu <jiaxin.yu@mediatek.com>
- Shane Chien <shane.chien@mediatek.com>
properties:
compatible:
const: mediatek,mt8192-audio
interrupts:
maxItems: 1
resets:
maxItems: 1
reset-names:
const: audiosys
memory-region:
description: memory region for audio DMA buffers
maxItems: 1
mediatek,apmixedsys:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the mediatek apmixedsys controller
mediatek,infracfg:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the mediatek infracfg controller
mediatek,topckgen:
$ref: /schemas/types.yaml#/definitions/phandle
description: The phandle of the mediatek topckgen controller
power-domains:
maxItems: 1
clocks:
items:
- description: AFE clock
- description: ADDA DAC clock
- description: ADDA DAC pre-distortion clock
- description: ADDA ADC clock
- description: ADDA6 ADC clock
- description: Audio low-jitter 22.5792m clock
- description: Audio low-jitter 24.576m clock
- description: Audio PLL1 tuner clock
- description: Audio PLL2 tuner clock
- description: Audio Time-Division Multiplexing interface clock
- description: ADDA ADC Sine Generator clock
- description: audio Non-LE clock
- description: Audio DAC High-Resolution clock
- description: Audio High-Resolution ADC clock
- description: Audio High-Resolution ADC SineGen clock
- description: Audio ADDA6 High-Resolution ADC clock
- description: Tertiary ADDA DAC clock
- description: Tertiary ADDA DAC pre-distortion clock
- description: Tertiary ADDA DAC Sine Generator clock
- description: Tertiary ADDA DAC High-Resolution clock
- description: Audio infra sys clock
- description: Audio infra 26M clock
- description: Mux for audio clock
- description: Mux for audio internal bus clock
- description: Mux main divider by 4
- description: Primary audio mux
- description: Primary audio PLL
- description: Secondary audio mux
- description: Secondary audio PLL
- description: Primary audio en-generator clock
- description: Primary PLL divider by 4 for IEC
- description: Secondary audio en-generator clock
- description: Secondary PLL divider by 4 for IEC
- description: Mux selector for I2S port 0
- description: Mux selector for I2S port 1
- description: Mux selector for I2S port 2
- description: Mux selector for I2S port 3
- description: Mux selector for I2S port 4
- description: Mux selector for I2S port 5
- description: Mux selector for I2S port 6
- description: Mux selector for I2S port 7
- description: Mux selector for I2S port 8
- description: Mux selector for I2S port 9
- description: APLL1 and APLL2 divider for I2S port 0
- description: APLL1 and APLL2 divider for I2S port 1
- description: APLL1 and APLL2 divider for I2S port 2
- description: APLL1 and APLL2 divider for I2S port 3
- description: APLL1 and APLL2 divider for I2S port 4
- description: APLL1 and APLL2 divider for IEC
- description: APLL1 and APLL2 divider for I2S port 5
- description: APLL1 and APLL2 divider for I2S port 6
- description: APLL1 and APLL2 divider for I2S port 7
- description: APLL1 and APLL2 divider for I2S port 8
- description: APLL1 and APLL2 divider for I2S port 9
- description: Top mux for audio subsystem
- description: 26MHz clock for audio subsystem
clock-names:
items:
- const: aud_afe_clk
- const: aud_dac_clk
- const: aud_dac_predis_clk
- const: aud_adc_clk
- const: aud_adda6_adc_clk
- const: aud_apll22m_clk
- const: aud_apll24m_clk
- const: aud_apll1_tuner_clk
- const: aud_apll2_tuner_clk
- const: aud_tdm_clk
- const: aud_tml_clk
- const: aud_nle
- const: aud_dac_hires_clk
- const: aud_adc_hires_clk
- const: aud_adc_hires_tml
- const: aud_adda6_adc_hires_clk
- const: aud_3rd_dac_clk
- const: aud_3rd_dac_predis_clk
- const: aud_3rd_dac_tml
- const: aud_3rd_dac_hires_clk
- const: aud_infra_clk
- const: aud_infra_26m_clk
- const: top_mux_audio
- const: top_mux_audio_int
- const: top_mainpll_d4_d4
- const: top_mux_aud_1
- const: top_apll1_ck
- const: top_mux_aud_2
- const: top_apll2_ck
- const: top_mux_aud_eng1
- const: top_apll1_d4
- const: top_mux_aud_eng2
- const: top_apll2_d4
- const: top_i2s0_m_sel
- const: top_i2s1_m_sel
- const: top_i2s2_m_sel
- const: top_i2s3_m_sel
- const: top_i2s4_m_sel
- const: top_i2s5_m_sel
- const: top_i2s6_m_sel
- const: top_i2s7_m_sel
- const: top_i2s8_m_sel
- const: top_i2s9_m_sel
- const: top_apll12_div0
- const: top_apll12_div1
- const: top_apll12_div2
- const: top_apll12_div3
- const: top_apll12_div4
- const: top_apll12_divb
- const: top_apll12_div5
- const: top_apll12_div6
- const: top_apll12_div7
- const: top_apll12_div8
- const: top_apll12_div9
- const: top_mux_audio_h
- const: top_clk26m_clk
required:
- compatible
- interrupts
- resets
- reset-names
- mediatek,apmixedsys
- mediatek,infracfg
- mediatek,topckgen
- power-domains
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8192-power.h>
#include <dt-bindings/reset/mt8192-resets.h>
afe: mt8192-afe-pcm {
compatible = "mediatek,mt8192-audio";
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&audsys CLK_AUD_AFE>, <&audsys CLK_AUD_DAC>,
<&audsys CLK_AUD_DAC_PREDIS>, <&audsys CLK_AUD_ADC>,
<&audsys CLK_AUD_ADDA6_ADC>, <&audsys CLK_AUD_22M>,
<&audsys CLK_AUD_24M>, <&audsys CLK_AUD_APLL_TUNER>,
<&audsys CLK_AUD_APLL2_TUNER>, <&audsys CLK_AUD_TDM>,
<&audsys CLK_AUD_TML>, <&audsys CLK_AUD_NLE>,
<&audsys CLK_AUD_DAC_HIRES>, <&audsys CLK_AUD_ADC_HIRES>,
<&audsys CLK_AUD_ADC_HIRES_TML>, <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
<&audsys CLK_AUD_3RD_DAC>, <&audsys CLK_AUD_3RD_DAC_PREDIS>,
<&audsys CLK_AUD_3RD_DAC_TML>, <&audsys CLK_AUD_3RD_DAC_HIRES>,
<&infracfg CLK_INFRA_AUDIO>, <&infracfg CLK_INFRA_AUDIO_26M_B>,
<&topckgen CLK_TOP_AUDIO_SEL>, <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&topckgen CLK_TOP_MAINPLL_D4_D4>, <&topckgen CLK_TOP_AUD_1_SEL>,
<&topckgen CLK_TOP_APLL1>, <&topckgen CLK_TOP_AUD_2_SEL>,
<&topckgen CLK_TOP_APLL2>, <&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
<&topckgen CLK_TOP_APLL1_D4>, <&topckgen CLK_TOP_AUD_ENGEN2_SEL>,
<&topckgen CLK_TOP_APLL2_D4>, <&topckgen CLK_TOP_APLL_I2S0_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S1_M_SEL>, <&topckgen CLK_TOP_APLL_I2S2_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S3_M_SEL>, <&topckgen CLK_TOP_APLL_I2S4_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S5_M_SEL>, <&topckgen CLK_TOP_APLL_I2S6_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S7_M_SEL>, <&topckgen CLK_TOP_APLL_I2S8_M_SEL>,
<&topckgen CLK_TOP_APLL_I2S9_M_SEL>, <&topckgen CLK_TOP_APLL12_DIV0>,
<&topckgen CLK_TOP_APLL12_DIV1>, <&topckgen CLK_TOP_APLL12_DIV2>,
<&topckgen CLK_TOP_APLL12_DIV3>, <&topckgen CLK_TOP_APLL12_DIV4>,
<&topckgen CLK_TOP_APLL12_DIVB>, <&topckgen CLK_TOP_APLL12_DIV5>,
<&topckgen CLK_TOP_APLL12_DIV6>, <&topckgen CLK_TOP_APLL12_DIV7>,
<&topckgen CLK_TOP_APLL12_DIV8>, <&topckgen CLK_TOP_APLL12_DIV9>,
<&topckgen CLK_TOP_AUDIO_H_SEL>, <&clk26m>;
clock-names = "aud_afe_clk", "aud_dac_clk",
"aud_dac_predis_clk", "aud_adc_clk",
"aud_adda6_adc_clk", "aud_apll22m_clk",
"aud_apll24m_clk", "aud_apll1_tuner_clk",
"aud_apll2_tuner_clk", "aud_tdm_clk",
"aud_tml_clk", "aud_nle",
"aud_dac_hires_clk", "aud_adc_hires_clk",
"aud_adc_hires_tml", "aud_adda6_adc_hires_clk",
"aud_3rd_dac_clk", "aud_3rd_dac_predis_clk",
"aud_3rd_dac_tml", "aud_3rd_dac_hires_clk",
"aud_infra_clk", "aud_infra_26m_clk",
"top_mux_audio", "top_mux_audio_int",
"top_mainpll_d4_d4", "top_mux_aud_1",
"top_apll1_ck", "top_mux_aud_2",
"top_apll2_ck", "top_mux_aud_eng1",
"top_apll1_d4", "top_mux_aud_eng2",
"top_apll2_d4", "top_i2s0_m_sel",
"top_i2s1_m_sel", "top_i2s2_m_sel",
"top_i2s3_m_sel", "top_i2s4_m_sel",
"top_i2s5_m_sel", "top_i2s6_m_sel",
"top_i2s7_m_sel", "top_i2s8_m_sel",
"top_i2s9_m_sel", "top_apll12_div0",
"top_apll12_div1", "top_apll12_div2",
"top_apll12_div3", "top_apll12_div4",
"top_apll12_divb", "top_apll12_div5",
"top_apll12_div6", "top_apll12_div7",
"top_apll12_div8", "top_apll12_div9",
"top_mux_audio_h", "top_clk26m_clk";
memory-region = <&afe_dma_mem>;
power-domains = <&scpsys MT8192_POWER_DOMAIN_AUDIO>;
resets = <&watchdog MT8192_TOPRGU_AUDIO_SW_RST>;
reset-names = "audiosys";
mediatek,apmixedsys = <&apmixedsys>;
mediatek,infracfg = <&infracfg>;
mediatek,topckgen = <&topckgen>;
};
...
|
