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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Audio Front End PCM controller for MT8196
maintainers:
- Darren Ye <darren.ye@mediatek.com>
properties:
compatible:
const: mediatek,mt8196-afe
reg:
maxItems: 1
interrupts:
maxItems: 1
memory-region:
maxItems: 1
power-domains:
maxItems: 1
clocks:
items:
- description: mux for audio intbus
- description: mux for audio engen1
- description: mux for audio engen2
- description: mux for audio h
- description: audio apll1 clock
- description: audio apll2 clock
- description: audio apll12 divide for i2sin0
- description: audio apll12 divide for i2sin1
- description: audio apll12 divide for fmi2s
- description: audio apll12 divide for tdmout mck
- description: audio apll12 divide for tdmout bck
- description: mux for adsp clock
clock-names:
items:
- const: top_aud_intbus
- const: top_aud_eng1
- const: top_aud_eng2
- const: top_aud_h
- const: apll1
- const: apll2
- const: apll12_div_i2sin0
- const: apll12_div_i2sin1
- const: apll12_div_fmi2s
- const: apll12_div_tdmout_m
- const: apll12_div_tdmout_b
- const: top_adsp
required:
- compatible
- reg
- interrupts
- memory-region
- power-domains
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
afe@1a110000 {
compatible = "mediatek,mt8196-afe";
reg = <0 0x1a110000 0 0x9000>;
interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH 0>;
memory-region = <&afe_dma_mem_reserved>;
power-domains = <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO
pinctrl-names = "default";
pinctrl-0 = <&aud_pins_default>;
clocks = <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL
<&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL
<&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL
<&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL
<&vlp_cksys_clk 0>, //CLK_VLP_CK_VLP_APLL1
<&vlp_cksys_clk 1>, //CLK_VLP_CK_VLP_APLL2
<&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0
<&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1
<&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S
<&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M
<&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B
<&cksys_clk 45>; //CLK_CK_ADSP_SEL
clock-names = "top_aud_intbus",
"top_aud_eng1",
"top_aud_eng2",
"top_aud_h",
"apll1",
"apll2",
"apll12_div_i2sin0",
"apll12_div_i2sin1",
"apll12_div_fmi2s",
"apll12_div_tdmout_m",
"apll12_div_tdmout_b",
"top_adsp";
};
};
...
|
