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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra264 UPHY Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra264-pinmux-uphy
reg:
maxItems: 1
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra264-pinmux-common.yaml
properties:
nvidia,pins:
items:
enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1,
pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4,
eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3,
eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0,
pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3,
pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5,
sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6,
soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3,
ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0,
drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1,
drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3,
drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1,
drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6,
drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0,
drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2,
drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2,
drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5,
drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1,
drive_soc_gpio113_pb6, drive_soc_gpio114_pb7,
drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2,
drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@82e0000 {
compatible = "nvidia,tegra264-pinmux-uphy";
reg = <0x82e0000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinmux_default>;
pinmux_default: pinmux-default {
pex {
nvidia,pins = "pex_l1_rst_n_pb1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
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