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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra264 AON Pinmux Controller
maintainers:
- Thierry Reding <thierry.reding@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
properties:
compatible:
const: nvidia,tegra264-pinmux-aon
reg:
maxItems: 1
patternProperties:
"^pinmux(-[a-z0-9-]+)?$":
type: object
# pin groups
additionalProperties:
$ref: nvidia,tegra264-pinmux-common.yaml
properties:
nvidia,pins:
items:
enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2,
batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5,
hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0,
soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1,
gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4,
uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7,
spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2,
soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5,
soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0,
soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3,
drive_ao_retention_n_paa2, drive_batt_oc_paa3,
drive_power_on_paa5, drive_vcomp_alert_paa1,
drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0,
drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0,
drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6,
drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1,
drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3,
drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5,
drive_uart0_rx_pcc6, drive_spi2_sck_pcc7,
drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1,
drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3,
drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5,
drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7,
drive_soc_gpio26_pee0, drive_soc_gpio27_pee1,
drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ]
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
pinmux@c7a2000 {
compatible = "nvidia,tegra264-pinmux-aon";
reg = <0xc7a2000 0x2000>;
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux-default {
uart0 {
nvidia,pins = "uart0_tx_pcc5";
nvidia,function = "uarta_txd";
};
};
};
|
