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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Spacemit K3 PCIE/USB3 Comb PHY
maintainers:
- Inochi Amaoto <inochiama@gmail.com>
properties:
compatible:
const: spacemit,k3-combo-phy
reg:
maxItems: 1
"#phy-cells":
const: 2
description:
The first one is phy id, the second one is phy type. This
only supports types are PCIe and USB .
spacemit,apb-spare:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to APB SPARE system controller interface, used for
PHY calibration.
spacemit,apmu:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle of APMU syscon
- description: configuration of the PHY lanes
description: |
Phandle to control PHY mux configuration. The configuration
is described as follows:
bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode
bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode
bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode
bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode
bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode
The bit[3:0] is only valid when bit 4 is 1.
This mux control does not affect the PHY for PCIe E, it is always
in PCIe mode.
required:
- compatible
- reg
- "#phy-cells"
- spacemit,apb-spare
- spacemit,apmu
additionalProperties: false
examples:
- |
phy@81d00000 {
compatible = "spacemit,k3-combo-phy";
reg = <0x81d00000 0x600000>;
#phy-cells = <2>;
spacemit,apb-spare = <&apb_spare>;
spacemit,apmu = <&apmu 0x00>;
};
|
