Documentation/devicetree/bindings/phy/renesas,rzg3e-usb3-phy.yaml


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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/renesas,rzg3e-usb3-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G3E USB 3.0 PHY

maintainers:
  - Biju Das <biju.das.jz@bp.renesas.com>

properties:
  compatible:
    oneOf:
      - const: renesas,r9a09g047-usb3-phy # RZ/G3E

      - items:
          - enum:
              - renesas,r9a09g056-usb3-phy # RZ/V2N
              - renesas,r9a09g057-usb3-phy # RZ/V2H(P)
          - const: renesas,r9a09g047-usb3-phy

  reg:
    maxItems: 1

  clocks:
    items:
      - description: APB bus clock
      - description: USB 2.0 PHY reference clock
      - description: USB 3.0 PHY reference clock

  clock-names:
    items:
      - const: pclk
      - const: core
      - const: ref_alt_clk_p

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  '#phy-cells':
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - resets
  - '#phy-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>

    usb-phy@15870000 {
        compatible = "renesas,r9a09g047-usb3-phy";
        reg = <0x15870000 0x10000>;
        clocks = <&cpg CPG_MOD 0xb0>, <&cpg CPG_CORE 13>, <&cpg CPG_CORE 12>;
        clock-names = "pclk", "core", "ref_alt_clk_p";
        power-domains = <&cpg>;
        resets = <&cpg 0xaa>;
        #phy-cells = <0>;
    };