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|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Lynx 10G SerDes PHY
maintainers:
- Vladimir Oltean <vladimir.oltean@nxp.com>
description:
The 10G Lynx is a multi-protocol SerDes block which handles networking, PCIe,
SATA and other high-speed interfaces. It is present on most QorIQ and
Layerscape SoCs. The register map is common, but the integration is
SoC-specific, with the differences consisting in register endianness, the
number of lanes, protocol converters available per lane and their location in
the PCCR registers. Some SoCs have multiple SerDes blocks and those differ in
their protocol capabilities per lane.
properties:
compatible:
enum:
- fsl,ls1028a-serdes
- fsl,ls1046a-serdes1
- fsl,ls1046a-serdes2
- fsl,ls1088a-serdes1
- fsl,ls1088a-serdes2
- fsl,ls2088a-serdes1
- fsl,ls2088a-serdes2
reg:
maxItems: 1
big-endian: true
"#phy-cells":
const: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^phy@[0-7]$":
type: object
description: SerDes lane (single RX/TX differential pair)
properties:
reg:
minimum: 0
maximum: 7
description: Lane index as seen in register map
"#phy-cells":
const: 0
required:
- reg
- "#phy-cells"
additionalProperties: false
required:
- compatible
- reg
- "#phy-cells"
- "#address-cells"
- "#size-cells"
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,ls1028a-serdes
- fsl,ls1046a-serdes1
- fsl,ls1046a-serdes2
- fsl,ls1088a-serdes1
- fsl,ls1088a-serdes2
then:
patternProperties:
"^phy@[0-7]$":
properties:
reg:
minimum: 0
maximum: 3
- if:
properties:
compatible:
enum:
- fsl,ls1046a-serdes1
- fsl,ls1046a-serdes2
then:
required:
- big-endian
else:
properties:
big-endian: false
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
serdes@1ea0000 {
compatible = "fsl,ls1028a-serdes";
reg = <0x0 0x1ea0000 0x0 0xffff>;
#address-cells = <1>;
#size-cells = <0>;
#phy-cells = <1>;
phy@0 {
reg = <0>;
#phy-cells = <0>;
};
phy@1 {
reg = <1>;
#phy-cells = <0>;
};
phy@2 {
reg = <2>;
#phy-cells = <0>;
};
phy@3 {
reg = <3>;
#phy-cells = <0>;
};
};
};
|
