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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32MP25 PCIe Root Complex
maintainers:
- Christian Bruel <christian.bruel@foss.st.com>
description:
PCIe root complex controller based on the Synopsys DesignWare PCIe core.
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
- $ref: /schemas/pci/st,stm32-pcie-common.yaml#
properties:
compatible:
const: st,stm32mp25-pcie-rc
reg:
items:
- description: Data Bus Interface (DBI) registers.
- description: PCIe configuration registers.
reg-names:
items:
- const: dbi
- const: config
msi-parent:
maxItems: 1
patternProperties:
'^pcie@[0-2],0$':
type: object
$ref: /schemas/pci/pci-pci-bridge.yaml#
properties:
reg:
maxItems: 1
phys:
maxItems: 1
reset-gpios:
description: GPIO controlled connection to PERST# signal
maxItems: 1
wake-gpios:
description: GPIO used as WAKE# input signal
maxItems: 1
required:
- phys
- ranges
unevaluatedProperties: false
required:
- interrupt-map
- interrupt-map-mask
- ranges
- dma-ranges
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
pcie@48400000 {
compatible = "st,stm32mp25-pcie-rc";
device_type = "pci";
reg = <0x48400000 0x400000>,
<0x10000000 0x10000>;
reg-names = "dbi", "config";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>,
<0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>,
<0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>;
dma-ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>;
clocks = <&rcc CK_BUS_PCIE>;
resets = <&rcc PCIE_R>;
msi-parent = <&v2m0>;
access-controllers = <&rifsc 68>;
power-domains = <&CLUSTER_PD>;
pcie@0,0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
phys = <&combophy PHY_TYPE_PCIE>;
wake-gpios = <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
|
