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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-apq8084.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm APQ8084 PCI Express Root Complex
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Manivannan Sadhasivam <mani@kernel.org>
properties:
compatible:
enum:
- qcom,pcie-apq8084
reg:
minItems: 4
maxItems: 5
reg-names:
minItems: 4
items:
- const: parf
- const: dbi
- const: elbi
- const: config
- const: mhi
clocks:
maxItems: 4
clock-names:
items:
- const: iface # Configuration AHB clock
- const: master_bus # Master AXI clock
- const: slave_bus # Slave AXI clock
- const: aux
interrupts:
maxItems: 1
interrupt-names:
items:
- const: msi
resets:
maxItems: 1
reset-names:
items:
- const: core
vdda-supply:
description: A phandle to the core analog power supply
required:
- power-domains
- resets
- reset-names
allOf:
- $ref: qcom,pcie-common.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
pcie@fc520000 {
compatible = "qcom,pcie-apq8084";
reg = <0xfc520000 0x2000>,
<0xff000000 0x1000>,
<0xff001000 0x1000>,
<0xff002000 0x2000>;
reg-names = "parf", "dbi", "elbi", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0xff200000 0 0x00100000>,
<0x82000000 0 0x00300000 0xff300000 0 0x00d00000>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc 324>,
<&gcc 325>,
<&gcc 327>,
<&gcc 323>;
clock-names = "iface", "master_bus", "slave_bus", "aux";
resets = <&gcc 81>;
reset-names = "core";
power-domains = <&gcc 1>;
vdda-supply = <&pma8084_l3>;
phys = <&pciephy0>;
phy-names = "pciephy";
perst-gpios = <&tlmm 70 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins_default>;
pinctrl-names = "default";
};
|
