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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Eswin EIC7700 SOC Eth Controller
maintainers:
- Shuang Liang <liangshuang@eswincomputing.com>
- Zhi Li <lizhi2@eswincomputing.com>
- Shangjuan Wei <weishangjuan@eswincomputing.com>
description:
Platform glue layer implementation for STMMAC Ethernet driver.
select:
properties:
compatible:
contains:
enum:
- eswin,eic7700-qos-eth
- eswin,eic7700-qos-eth-clk-inversion
required:
- compatible
allOf:
- $ref: snps,dwmac.yaml#
- if:
properties:
compatible:
contains:
const: eswin,eic7700-qos-eth
then:
properties:
tx-internal-delay-ps:
maximum: 2540
- if:
properties:
compatible:
contains:
const: eswin,eic7700-qos-eth-clk-inversion
then:
properties:
tx-internal-delay-ps:
minimum: 2000
properties:
compatible:
items:
- enum:
- eswin,eic7700-qos-eth
- eswin,eic7700-qos-eth-clk-inversion
- const: snps,dwmac-5.20
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-names:
const: macirq
clocks:
items:
- description: AXI clock
- description: Configuration clock
- description: GMAC main clock
- description: Tx clock
clock-names:
items:
- const: axi
- const: cfg
- const: stmmaceth
- const: tx
resets:
maxItems: 1
reset-names:
items:
- const: stmmaceth
rx-internal-delay-ps:
minimum: 0
maximum: 2540
multipleOf: 20
tx-internal-delay-ps:
minimum: 0
maximum: 4540
multipleOf: 20
eswin,hsp-sp-csr:
description:
HSP CSR is to control and get status of different high-speed peripherals
(such as Ethernet, USB, SATA, etc.) via register, which can tune
board-level's parameters of PHY, etc.
Additional background information about the High-Speed Subsystem
and the HSP CSR block is available in Chapter 10 ("High-Speed Interface")
of the EIC7700X SoC Technical Reference Manual, Part 4
(EIC7700X_SoC_Technical_Reference_Manual_Part4.pdf). The manual is
publicly available at
https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases
This reference is provided for background information only.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- minItems: 4
items:
- description: Phandle to HSP(High-Speed Peripheral) device
- description: Offset of phy control register for internal
or external clock selection
- description: Offset of AXI clock controller Low-Power request
register
- description: Offset of register controlling TX/RX clock delay
- description: Optional offset of register controlling TXD delay
- description: Optional offset of register controlling RXD delay
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- phy-mode
- resets
- reset-names
- eswin,hsp-sp-csr
unevaluatedProperties: false
examples:
- |
ethernet@50400000 {
compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20";
reg = <0x50400000 0x10000>;
interrupt-parent = <&plic>;
interrupts = <61>;
interrupt-names = "macirq";
clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
<&d0_clock 193>;
clock-names = "axi", "cfg", "stmmaceth", "tx";
resets = <&reset 95>;
reset-names = "stmmaceth";
eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>;
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
snps,aal;
snps,fixed-burst;
snps,tso;
snps,axi-config = <&stmmac_axi_setup>;
stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <2>;
snps,wr_osr_lmt = <2>;
};
};
ethernet@50410000 {
compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20";
reg = <0x50410000 0x10000>;
interrupt-parent = <&plic>;
interrupts = <70>;
interrupt-names = "macirq";
clocks = <&d0_clock 186>, <&d0_clock 171>, <&d0_clock 40>,
<&d0_clock 194>;
clock-names = "axi", "cfg", "stmmaceth", "tx";
resets = <&reset 94>;
reset-names = "stmmaceth";
eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>;
phy-handle = <&gmac1_phy0>;
phy-mode = "rgmii-id";
snps,aal;
snps,fixed-burst;
snps,tso;
snps,axi-config = <&stmmac_axi_setup_gmac1>;
stmmac_axi_setup_gmac1: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <2>;
snps,wr_osr_lmt = <2>;
};
};
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