blob: 8358bb70c3335340d6da12690577bfbc4a7d3cad (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mmc/bst,c1200-sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Black Sesame Technologies DWCMSHC SDHCI Controller
maintainers:
- Ge Gordon <gordon.ge@bst.ai>
allOf:
- $ref: sdhci-common.yaml#
properties:
compatible:
const: bst,c1200-sdhci
reg:
items:
- description: Core SDHCI registers
- description: CRM registers
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: core
memory-region:
maxItems: 1
dma-coherent: true
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
mmc@22200000 {
compatible = "bst,c1200-sdhci";
reg = <0x0 0x22200000 0x0 0x1000>,
<0x0 0x23006000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_mmc>;
clock-names = "core";
memory-region = <&mmc0_reserved>;
max-frequency = <200000000>;
bus-width = <8>;
non-removable;
dma-coherent;
};
};
|