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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Aspeed System Control Unit
description:
The Aspeed System Control Unit manages the global behaviour of the SoC,
configuring elements such as clocks, pinmux, and reset.
In AST2700 SOC which has two soc connection, each soc have its own scu
register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
maintainers:
- Joel Stanley <joel@jms.id.au>
- Andrew Jeffery <andrew@aj.id.au>
properties:
compatible:
items:
- enum:
- aspeed,ast2400-scu
- aspeed,ast2500-scu
- aspeed,ast2600-scu
- aspeed,ast2700-scu0
- aspeed,ast2700-scu1
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
ranges: true
'#address-cells':
minimum: 1
maximum: 2
'#size-cells':
const: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
memory-region:
items:
- description: Region mapped through the first SSP address window.
- description: Region mapped through the second SSP address window.
- description: Region mapped through the TSP address window.
memory-region-names:
items:
- const: ssp-0
- const: ssp-1
- const: tsp
patternProperties:
'^p2a-control@[0-9a-f]+$':
description: >
PCI-to-AHB Bridge Control
The bridge is available on platforms with the VGA enabled on the Aspeed
device. In this case, the host has access to a 64KiB window into all of
the BMC's memory. The BMC can disable this bridge. If the bridge is
enabled, the host has read access to all the regions of memory, however
the host only has read and write access depending on a register
controlled by the BMC.
type: object
additionalProperties: false
properties:
compatible:
enum:
- aspeed,ast2400-p2a-ctrl
- aspeed,ast2500-p2a-ctrl
reg:
maxItems: 1
memory-region:
maxItems: 1
description:
A reserved_memory region to be used for the PCI to AHB mapping
required:
- compatible
- reg
'^pinctrl(@[0-9a-f]+)?$':
type: object
additionalProperties: true
properties:
compatible:
contains:
enum:
- aspeed,ast2400-pinctrl
- aspeed,ast2500-pinctrl
- aspeed,ast2600-pinctrl
- aspeed,ast2700-soc0-pinctrl
- aspeed,ast2700-soc1-pinctrl
required:
- compatible
'^interrupt-controller@[0-9a-f]+$':
type: object
additionalProperties: true
properties:
compatible:
contains:
enum:
- aspeed,ast2500-scu-ic
- aspeed,ast2600-scu-ic0
- aspeed,ast2600-scu-ic1
- aspeed,ast2700-scu-ic0
- aspeed,ast2700-scu-ic1
- aspeed,ast2700-scu-ic2
- aspeed,ast2700-scu-ic3
'^silicon-id@[0-9a-f]+$':
description: Unique hardware silicon identifiers within the SoC
type: object
additionalProperties: false
properties:
compatible:
items:
- enum:
- aspeed,ast2400-silicon-id
- aspeed,ast2500-silicon-id
- aspeed,ast2600-silicon-id
- aspeed,ast2700-silicon-id
- const: aspeed,silicon-id
reg:
description:
The reg should be the unique silicon id register, and not backwards
compatible one in eg. the 2600.
minItems: 1
items:
- description: silicon id information registers
- description: unique chip id registers
'^smp-memram@[0-9a-f]+$':
description: Memory region used for the AST2600's custom SMP bringup protocol
type: object
additionalProperties: false
properties:
compatible:
const: aspeed,ast2600-smpmem
reg:
description: The SMP memory region
maxItems: 1
required:
- compatible
- reg
required:
- compatible
- reg
- ranges
- '#address-cells'
- '#size-cells'
- '#clock-cells'
- '#reset-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- aspeed,ast2700-scu0
- aspeed,ast2700-scu1
then:
patternProperties:
'^p2a-control@[0-9a-f]+$': false
'^smp-memram@[0-9a-f]+$': false
- if:
not:
properties:
compatible:
contains:
const: aspeed,ast2700-scu0
then:
properties:
memory-region: false
memory-region-names: false
additionalProperties: false
examples:
- |
syscon@1e6e2000 {
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1a8>;
#clock-cells = <1>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e6e2000 0x1000>;
p2a-control@2c {
compatible = "aspeed,ast2400-p2a-ctrl";
reg = <0x2c 0x4>;
};
silicon-id@7c {
compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
reg = <0x7c 0x4>, <0x150 0x8>;
};
};
- |
/ {
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ssp_region_0: memory@400000000 {
reg = <0x4 0x00000000 0x0 0x01000000>;
no-map;
};
ssp_region_1: memory@401000000 {
reg = <0x4 0x01000000 0x0 0x01000000>;
no-map;
};
tsp_region: memory@402000000 {
reg = <0x4 0x02000000 0x0 0x01000000>;
no-map;
};
};
bus {
#address-cells = <2>;
#size-cells = <2>;
syscon@12c02000 {
compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd";
reg = <0 0x12c02000 0 0x1000>;
ranges = <0x0 0x0 0x12c02000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
memory-region = <&ssp_region_0>, <&ssp_region_1>,
<&tsp_region>;
memory-region-names = "ssp-0", "ssp-1", "tsp";
silicon-id@0 {
compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id";
reg = <0x0 0x4>;
};
interrupt-controller@1b0 {
compatible = "aspeed,ast2700-scu-ic0";
reg = <0x1b0 0x4>;
#interrupt-cells = <1>;
interrupts-extended = <&intc0 97>;
interrupt-controller;
};
interrupt-controller@1e0 {
compatible = "aspeed,ast2700-scu-ic1";
reg = <0x1e0 0x4>;
#interrupt-cells = <1>;
interrupts-extended = <&intc0 98>;
interrupt-controller;
};
pinctrl@400 {
compatible = "aspeed,ast2700-soc0-pinctrl";
reg = <0x400 0x318>;
emmc-state {
function = "EMMC";
groups = "EMMCG1";
};
};
};
};
};
...
|
