1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mailbox/axiado,ax3005-mailbox.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axiado AX3005 Mailbox Controller
maintainers:
- Krishnakumar Kesavan <kkesavan@axiado.com>
- Prasad Bolisetty <pbolisetty@axiado.com>
- Swark Yang <syang@axiado.com>
description:
The Axiado mailbox controller provides inter-processor communication
channels between subsystems within the Axiado SoC. The hardware has
separate TX and RX register regions. Only the RX channels (channels 8-15)
generate interrupts; TX channels are purely poll/write-based.
properties:
compatible:
const: axiado,ax3005-mailbox
reg:
items:
- description: TX mailbox register region
- description: RX mailbox register region
reg-names:
items:
- const: tx
- const: rx
interrupts:
description:
One interrupt per RX channel. The hardware exposes eight RX interrupt
lines corresponding to channels 8 through 15.
maxItems: 8
interrupt-names:
description:
Named interrupt lines for each RX channel, from ch8 to ch15.
items:
- const: ch8
- const: ch9
- const: ch10
- const: ch11
- const: ch12
- const: ch13
- const: ch14
- const: ch15
"#mbox-cells":
description:
Number of cells in a mailbox specifier. A single cell encodes the
channel index as seen by the client.
const: 1
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- "#mbox-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
mailbox@330f2000 {
compatible = "axiado,ax3005-mailbox";
reg = <0x0 0x330f2000 0x0 0x2000>,
<0x0 0x331b0000 0x0 0x1000>;
reg-names = "tx", "rx";
/* Only RX channels (8-15) have IRQs */
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
interrupt-parent = <&gic500>;
#mbox-cells = <1>;
};
};
|