1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Azurite DPLL device
maintainers:
- Ivan Vecera <ivecera@redhat.com>
description:
Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
provides up to 5 independent DPLL channels, up to 10 differential or
single-ended inputs and 10 differential or 20 single-ended outputs.
These devices support both I2C and SPI interfaces.
The ZL3064x line card timing ICs share the ZL3073x register map
and are described with a fallback to the register equivalent ZL3073x
part.
properties:
compatible:
oneOf:
- enum:
- microchip,zl30731
- microchip,zl30732
- microchip,zl30733
- microchip,zl30734
- microchip,zl30735
- items:
- const: microchip,zl30643
- const: microchip,zl30733
reg:
maxItems: 1
required:
- compatible
- reg
allOf:
- $ref: /schemas/dpll/dpll-device.yaml#
- $ref: /schemas/spi/spi-peripheral-props.yaml#
unevaluatedProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
dpll@70 {
compatible = "microchip,zl30732";
reg = <0x70>;
dpll-types = "pps", "eec";
input-pins {
#address-cells = <1>;
#size-cells = <0>;
sync0: pin@0 { /* REF0P - 1 PPS sync source */
reg = <0>;
connection-type = "ext";
label = "SMA1";
supported-frequencies-hz = /bits/ 64 <1>;
};
pin@1 { /* REF0N - clock source, can pair with sync0 */
reg = <1>;
connection-type = "ext";
label = "SMA2";
supported-frequencies-hz = /bits/ 64 <10000 10000000>;
ref-sync-sources = <&sync0>;
};
};
output-pins {
#address-cells = <1>;
#size-cells = <0>;
pin@3 { /* OUT1N */
reg = <3>;
connection-type = "gnss";
esync-control;
label = "Output 1";
supported-frequencies-hz = /bits/ 64 <1 10000>;
};
};
};
};
- |
spi {
#address-cells = <1>;
#size-cells = <0>;
dpll@70 {
compatible = "microchip,zl30731";
reg = <0x70>;
spi-max-frequency = <12500000>;
dpll-types = "pps";
input-pins {
#address-cells = <1>;
#size-cells = <0>;
sync1: pin@0 { /* REF0P - 1 PPS sync source */
reg = <0>;
connection-type = "gnss";
label = "GNSS_1PPS_IN";
supported-frequencies-hz = /bits/ 64 <1>;
};
pin@1 { /* REF0N - clock source */
reg = <1>;
connection-type = "gnss";
label = "GNSS_10M_IN";
supported-frequencies-hz = /bits/ 64 <10000000>;
ref-sync-sources = <&sync1>;
};
};
output-pins {
#address-cells = <1>;
#size-cells = <0>;
pin@3 { /* OUT1N */
reg = <3>;
connection-type = "gnss";
esync-control;
label = "Output 1";
supported-frequencies-hz = /bits/ 64 <1 10000>;
};
};
};
};
...
|
