blob: 1a3105e86980a14069f8fb40c92d1f9cc71c6c1c (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
|
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/cpufreq/qcom,shikra-epss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Shikra SoC EPSS
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
EPSS is a hardware engine used by some Qualcomm SoCs to manage
frequency in hardware. It is capable of controlling frequency for
multiple clusters.
The Qualcomm Shikra SoC EPSS supports up to 12 frequency lookup table
(LUT) entries.
properties:
compatible:
enum:
- qcom,shikra-epss
reg:
items:
- description: Frequency domain 0 register region
- description: Frequency domain 1 register region
reg-names:
items:
- const: freq-domain0
- const: freq-domain1
clocks:
items:
- description: XO Clock
- description: GPLL0 Clock
clock-names:
items:
- const: xo
- const: alternate
interrupts:
items:
- description: IRQ line for DCVSH 0
- description: IRQ line for DCVSH 1
interrupt-names:
items:
- const: dcvsh-irq-0
- const: dcvsh-irq-1
'#freq-domain-cells':
const: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- interrupt-names
- '#freq-domain-cells'
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
cpufreq@fd91000 {
compatible = "qcom,shikra-epss";
reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gpll0>;
clock-names = "xo", "alternate";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";
#freq-domain-cells = <1>;
#clock-cells = <1>;
};
};
...
|
