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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/xlnx,versal-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal clock controller
maintainers:
- Michal Simek <michal.simek@amd.com>
description: |
The clock controller is a hardware block of Xilinx versal clock tree. It
reads required input clock frequencies from the devicetree and acts as clock
provider for all clock consumers of PS clocks.
properties:
compatible:
oneOf:
- const: xlnx,versal-clk
- items:
- enum:
- xlnx,versal-net-clk
- const: xlnx,versal-clk
"#clock-cells":
const: 1
clocks:
description: List of clock specifiers which are external input
clocks to the given clock controller.
minItems: 2
items:
- description: reference clock
- description: alternate reference clock for programmable logic
- description: alternate reference clock
clock-names:
minItems: 2
items:
- const: ref
- const: pl_alt_ref
- const: alt_ref
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- xlnx,versal-net-clk
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
else:
properties:
clocks:
maxItems: 2
clock-names:
maxItems: 2
examples:
- |
firmware {
versal-firmware {
compatible = "xlnx,versal-firmware";
method = "smc";
versal_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,versal-clk";
clocks = <&ref>, <&pl_alt_ref>;
clock-names = "ref", "pl_alt_ref";
};
};
};
- |
clock-controller {
compatible = "xlnx,versal-net-clk", "xlnx,versal-clk";
clocks = <&ref>, <&pl_alt_ref>, <&alt_ref>;
clock-names = "ref", "pl_alt_ref", "alt_ref";
#clock-cells = <1>;
};
...
|
