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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)
maintainers:
- Nicolas Ferre <nicolas.ferre@microchip.com>
- Claudiu Beznea <claudiu.beznea@tuxon.dev>
description:
The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various
Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external
SDRAM / DDR memory. It is typically exposed as a syscon node for
register access from other drivers (e.g. for initialization or mode
configuration). No interrupts or clocks are usually required in the
binding.
properties:
compatible:
oneOf:
- items:
- const: atmel,at91rm9200-sdramc
- const: syscon
- items:
- const: microchip,sama7d65-uddrc
- const: microchip,sama7g5-uddrc
- enum:
- atmel,at91sam9260-sdramc
- atmel,at91sam9g45-ddramc
- atmel,sama5d3-ddramc
- microchip,sam9x60-ddramc
- microchip,sam9x7-ddramc
- microchip,sama7g5-uddrc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: ddrck
- const: mpddr
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/at91.h>
ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe400 0x200>;
clocks = <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "ddrck";
};
...
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