diff options
Diffstat (limited to 'drivers/mfd/lpc_ich.c')
| -rw-r--r-- | drivers/mfd/lpc_ich.c | 1465 |
1 files changed, 1465 insertions, 0 deletions
diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c new file mode 100644 index 000000000..d2efcc92b --- /dev/null +++ b/drivers/mfd/lpc_ich.c @@ -0,0 +1,1465 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * lpc_ich.c - LPC interface for Intel ICH + * + * LPC bridge function of the Intel ICH contains many other + * functional units, such as Interrupt controllers, Timers, + * Power Management, System Management, GPIO, RTC, and LPC + * Configuration Registers. + * + * This driver is derived from lpc_sch. + * + * Copyright (c) 2017, 2021-2022 Intel Corporation + * Copyright (c) 2011 Extreme Engineering Solution, Inc. + * Author: Aaron Sierra <asierra@xes-inc.com> + * + * This driver supports the following I/O Controller hubs: + * (See the intel documentation on http://developer.intel.com.) + * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) + * document number 290687-002, 298242-027: 82801BA (ICH2) + * document number 290733-003, 290739-013: 82801CA (ICH3-S) + * document number 290716-001, 290718-007: 82801CAM (ICH3-M) + * document number 290744-001, 290745-025: 82801DB (ICH4) + * document number 252337-001, 252663-008: 82801DBM (ICH4-M) + * document number 273599-001, 273645-002: 82801E (C-ICH) + * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) + * document number 300641-004, 300884-013: 6300ESB + * document number 301473-002, 301474-026: 82801F (ICH6) + * document number 313082-001, 313075-006: 631xESB, 632xESB + * document number 307013-003, 307014-024: 82801G (ICH7) + * document number 322896-001, 322897-001: NM10 + * document number 313056-003, 313057-017: 82801H (ICH8) + * document number 316972-004, 316973-012: 82801I (ICH9) + * document number 319973-002, 319974-002: 82801J (ICH10) + * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) + * document number 320066-003, 320257-008: EP80597 (IICH) + * document number 324645-001, 324646-001: Cougar Point (CPT) + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include <linux/align.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/acpi.h> +#include <linux/pci.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/property.h> +#include <linux/mfd/core.h> +#include <linux/mfd/lpc_ich.h> +#include <linux/platform_data/itco_wdt.h> +#include <linux/platform_data/x86/p2sb.h> + +#define ACPIBASE 0x40 +#define ACPIBASE_GPE_OFF 0x28 +#define ACPIBASE_GPE_END 0x2f +#define ACPIBASE_SMI_OFF 0x30 +#define ACPIBASE_SMI_END 0x33 +#define ACPIBASE_PMC_OFF 0x08 +#define ACPIBASE_PMC_END 0x0c +#define ACPIBASE_TCO_OFF 0x60 +#define ACPIBASE_TCO_END 0x7f +#define ACPICTRL_PMCBASE 0x44 + +#define ACPIBASE_GCS_OFF 0x3410 +#define ACPIBASE_GCS_END 0x3414 + +#define SPIBASE_BYT 0x54 +#define SPIBASE_BYT_SZ 512 +#define SPIBASE_BYT_EN BIT(1) +#define BYT_BCR 0xfc +#define BYT_BCR_WPD BIT(0) + +#define SPIBASE_LPT 0x3800 +#define SPIBASE_LPT_SZ 512 +#define BCR 0xdc +#define BCR_WPD BIT(0) + +#define GPIOBASE_ICH0 0x58 +#define GPIOCTRL_ICH0 0x5C +#define GPIOBASE_ICH6 0x48 +#define GPIOCTRL_ICH6 0x4C + +#define RCBABASE 0xf0 + +#define wdt_io_res(i) wdt_res(0, i) +#define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) +#define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) + +static struct resource wdt_ich_res[] = { + /* ACPI - TCO */ + { + .flags = IORESOURCE_IO, + }, + /* ACPI - SMI */ + { + .flags = IORESOURCE_IO, + }, + /* GCS or PMC */ + { + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource gpio_ich_res[] = { + /* GPIO */ + { + .flags = IORESOURCE_IO, + }, + /* ACPI - GPE0 */ + { + .flags = IORESOURCE_IO, + }, +}; + +static struct resource intel_spi_res[] = { + { + .flags = IORESOURCE_MEM, + } +}; + +static struct mfd_cell lpc_ich_wdt_cell = { + .name = "iTCO_wdt", + .num_resources = ARRAY_SIZE(wdt_ich_res), + .resources = wdt_ich_res, + .ignore_resource_conflicts = true, +}; + +const struct software_node lpc_ich_gpio_swnode = { + .name = "gpio_ich", +}; +EXPORT_SYMBOL_NS(lpc_ich_gpio_swnode, "LPC_ICH"); + +static struct mfd_cell lpc_ich_gpio_cell = { + .name = "gpio_ich", + .num_resources = ARRAY_SIZE(gpio_ich_res), + .resources = gpio_ich_res, + .ignore_resource_conflicts = true, + .swnode = &lpc_ich_gpio_swnode, +}; + +#define INTEL_GPIO_RESOURCE_SIZE 0x1000 + +struct lpc_ich_gpio_info { + const char *hid; + const struct mfd_cell *devices; + size_t nr_devices; + struct resource **resources; + size_t nr_resources; + const resource_size_t *offsets; +}; + +#define APL_GPIO_NORTH 0 +#define APL_GPIO_NORTHWEST 1 +#define APL_GPIO_WEST 2 +#define APL_GPIO_SOUTHWEST 3 + +#define APL_GPIO_NR_DEVICES 4 +#define APL_GPIO_NR_RESOURCES 4 + +/* Offset data for Apollo Lake GPIO controllers */ +static const resource_size_t apl_gpio_offsets[APL_GPIO_NR_RESOURCES] = { + [APL_GPIO_NORTH] = 0xc50000, + [APL_GPIO_NORTHWEST] = 0xc40000, + [APL_GPIO_WEST] = 0xc70000, + [APL_GPIO_SOUTHWEST] = 0xc00000, +}; + +#define APL_GPIO_IRQ 14 + +static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = { + [APL_GPIO_NORTH] = { + DEFINE_RES_MEM(0, 0), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + [APL_GPIO_NORTHWEST] = { + DEFINE_RES_MEM(0, 0), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + [APL_GPIO_WEST] = { + DEFINE_RES_MEM(0, 0), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, + [APL_GPIO_SOUTHWEST] = { + DEFINE_RES_MEM(0, 0), + DEFINE_RES_IRQ(APL_GPIO_IRQ), + }, +}; + +static struct resource *apl_gpio_mem_resources[APL_GPIO_NR_RESOURCES] = { + [APL_GPIO_NORTH] = &apl_gpio_resources[APL_GPIO_NORTH][0], + [APL_GPIO_NORTHWEST] = &apl_gpio_resources[APL_GPIO_NORTHWEST][0], + [APL_GPIO_WEST] = &apl_gpio_resources[APL_GPIO_WEST][0], + [APL_GPIO_SOUTHWEST] = &apl_gpio_resources[APL_GPIO_SOUTHWEST][0], +}; + +static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = { + [APL_GPIO_NORTH] = { + .name = "apollolake-pinctrl", + .id = APL_GPIO_NORTH, + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]), + .resources = apl_gpio_resources[APL_GPIO_NORTH], + .ignore_resource_conflicts = true, + }, + [APL_GPIO_NORTHWEST] = { + .name = "apollolake-pinctrl", + .id = APL_GPIO_NORTHWEST, + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]), + .resources = apl_gpio_resources[APL_GPIO_NORTHWEST], + .ignore_resource_conflicts = true, + }, + [APL_GPIO_WEST] = { + .name = "apollolake-pinctrl", + .id = APL_GPIO_WEST, + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]), + .resources = apl_gpio_resources[APL_GPIO_WEST], + .ignore_resource_conflicts = true, + }, + [APL_GPIO_SOUTHWEST] = { + .name = "apollolake-pinctrl", + .id = APL_GPIO_SOUTHWEST, + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]), + .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST], + .ignore_resource_conflicts = true, + }, +}; + +static const struct lpc_ich_gpio_info apl_gpio_info = { + .hid = "INT3452", + .devices = apl_gpio_devices, + .nr_devices = ARRAY_SIZE(apl_gpio_devices), + .resources = apl_gpio_mem_resources, + .nr_resources = ARRAY_SIZE(apl_gpio_mem_resources), + .offsets = apl_gpio_offsets, +}; + +#define DNV_GPIO_NORTH 0 +#define DNV_GPIO_SOUTH 1 + +#define DNV_GPIO_NR_DEVICES 1 +#define DNV_GPIO_NR_RESOURCES 2 + +/* Offset data for Denverton GPIO controllers */ +static const resource_size_t dnv_gpio_offsets[DNV_GPIO_NR_RESOURCES] = { + [DNV_GPIO_NORTH] = 0xc20000, + [DNV_GPIO_SOUTH] = 0xc50000, +}; + +#define DNV_GPIO_IRQ 14 + +static struct resource dnv_gpio_resources[DNV_GPIO_NR_RESOURCES + 1] = { + [DNV_GPIO_NORTH] = DEFINE_RES_MEM(0, 0), + [DNV_GPIO_SOUTH] = DEFINE_RES_MEM(0, 0), + DEFINE_RES_IRQ(DNV_GPIO_IRQ), +}; + +static struct resource *dnv_gpio_mem_resources[DNV_GPIO_NR_RESOURCES] = { + [DNV_GPIO_NORTH] = &dnv_gpio_resources[DNV_GPIO_NORTH], + [DNV_GPIO_SOUTH] = &dnv_gpio_resources[DNV_GPIO_SOUTH], +}; + +static const struct mfd_cell dnv_gpio_devices[DNV_GPIO_NR_DEVICES] = { + { + .name = "denverton-pinctrl", + .num_resources = ARRAY_SIZE(dnv_gpio_resources), + .resources = dnv_gpio_resources, + .ignore_resource_conflicts = true, + }, +}; + +static const struct lpc_ich_gpio_info dnv_gpio_info = { + .hid = "INTC3000", + .devices = dnv_gpio_devices, + .nr_devices = ARRAY_SIZE(dnv_gpio_devices), + .resources = dnv_gpio_mem_resources, + .nr_resources = ARRAY_SIZE(dnv_gpio_mem_resources), + .offsets = dnv_gpio_offsets, +}; + +static struct mfd_cell lpc_ich_spi_cell = { + .name = "intel-spi", + .num_resources = ARRAY_SIZE(intel_spi_res), + .resources = intel_spi_res, + .ignore_resource_conflicts = true, +}; + +/* chipset related info */ +enum lpc_chipsets { + LPC_ICH = 0, /* ICH */ + LPC_ICH0, /* ICH0 */ + LPC_ICH2, /* ICH2 */ + LPC_ICH2M, /* ICH2-M */ + LPC_ICH3, /* ICH3-S */ + LPC_ICH3M, /* ICH3-M */ + LPC_ICH4, /* ICH4 */ + LPC_ICH4M, /* ICH4-M */ + LPC_CICH, /* C-ICH */ + LPC_ICH5, /* ICH5 & ICH5R */ + LPC_6300ESB, /* 6300ESB */ + LPC_ICH6, /* ICH6 & ICH6R */ + LPC_ICH6M, /* ICH6-M */ + LPC_ICH6W, /* ICH6W & ICH6RW */ + LPC_631XESB, /* 631xESB/632xESB */ + LPC_ICH7, /* ICH7 & ICH7R */ + LPC_ICH7DH, /* ICH7DH */ + LPC_ICH7M, /* ICH7-M & ICH7-U */ + LPC_ICH7MDH, /* ICH7-M DH */ + LPC_NM10, /* NM10 */ + LPC_ICH8, /* ICH8 & ICH8R */ + LPC_ICH8DH, /* ICH8DH */ + LPC_ICH8DO, /* ICH8DO */ + LPC_ICH8M, /* ICH8M */ + LPC_ICH8ME, /* ICH8M-E */ + LPC_ICH9, /* ICH9 */ + LPC_ICH9R, /* ICH9R */ + LPC_ICH9DH, /* ICH9DH */ + LPC_ICH9DO, /* ICH9DO */ + LPC_ICH9M, /* ICH9M */ + LPC_ICH9ME, /* ICH9M-E */ + LPC_ICH10, /* ICH10 */ + LPC_ICH10R, /* ICH10R */ + LPC_ICH10D, /* ICH10D */ + LPC_ICH10DO, /* ICH10DO */ + LPC_PCH, /* PCH Desktop Full Featured */ + LPC_PCHM, /* PCH Mobile Full Featured */ + LPC_P55, /* P55 */ + LPC_PM55, /* PM55 */ + LPC_H55, /* H55 */ + LPC_QM57, /* QM57 */ + LPC_H57, /* H57 */ + LPC_HM55, /* HM55 */ + LPC_Q57, /* Q57 */ + LPC_HM57, /* HM57 */ + LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ + LPC_QS57, /* QS57 */ + LPC_3400, /* 3400 */ + LPC_3420, /* 3420 */ + LPC_3450, /* 3450 */ + LPC_EP80579, /* EP80579 */ + LPC_CPT, /* Cougar Point */ + LPC_CPTD, /* Cougar Point Desktop */ + LPC_CPTM, /* Cougar Point Mobile */ + LPC_PBG, /* Patsburg */ + LPC_DH89XXCC, /* DH89xxCC */ + LPC_PPT, /* Panther Point */ + LPC_LPT, /* Lynx Point */ + LPC_LPT_LP, /* Lynx Point-LP */ + LPC_WBG, /* Wellsburg */ + LPC_AVN, /* Avoton SoC */ + LPC_BAYTRAIL, /* Bay Trail SoC */ + LPC_COLETO, /* Coleto Creek */ + LPC_WPT_LP, /* Wildcat Point-LP */ + LPC_BRASWELL, /* Braswell SoC */ + LPC_LEWISBURG, /* Lewisburg */ + LPC_9S, /* 9 Series */ + LPC_APL, /* Apollo Lake SoC */ + LPC_DNV, /* Denverton SoC */ + LPC_GLK, /* Gemini Lake SoC */ + LPC_COUGARMOUNTAIN,/* Cougar Mountain SoC*/ +}; + +struct lpc_ich_priv { + enum lpc_chipsets chipset; + + int abase; /* ACPI base */ + int actrl_pbase; /* ACPI control or PMC base */ + int gbase; /* GPIO base */ + int gctrl; /* GPIO control */ + + int abase_save; /* Cached ACPI base value */ + int actrl_pbase_save; /* Cached ACPI control or PMC base value */ + int gctrl_save; /* Cached GPIO control value */ +}; + +static struct lpc_ich_info lpc_chipset_info[] = { + [LPC_ICH] = { + .name = "ICH", + .iTCO_version = 1, + }, + [LPC_ICH0] = { + .name = "ICH0", + .iTCO_version = 1, + }, + [LPC_ICH2] = { + .name = "ICH2", + .iTCO_version = 1, + }, + [LPC_ICH2M] = { + .name = "ICH2-M", + .iTCO_version = 1, + }, + [LPC_ICH3] = { + .name = "ICH3-S", + .iTCO_version = 1, + }, + [LPC_ICH3M] = { + .name = "ICH3-M", + .iTCO_version = 1, + }, + [LPC_ICH4] = { + .name = "ICH4", + .iTCO_version = 1, + }, + [LPC_ICH4M] = { + .name = "ICH4-M", + .iTCO_version = 1, + }, + [LPC_CICH] = { + .name = "C-ICH", + .iTCO_version = 1, + }, + [LPC_ICH5] = { + .name = "ICH5 or ICH5R", + .iTCO_version = 1, + }, + [LPC_6300ESB] = { + .name = "6300ESB", + .iTCO_version = 1, + }, + [LPC_ICH6] = { + .name = "ICH6 or ICH6R", + .iTCO_version = 2, + .gpio_version = ICH_V6_GPIO, + }, + [LPC_ICH6M] = { + .name = "ICH6-M", + .iTCO_version = 2, + .gpio_version = ICH_V6_GPIO, + }, + [LPC_ICH6W] = { + .name = "ICH6W or ICH6RW", + .iTCO_version = 2, + .gpio_version = ICH_V6_GPIO, + }, + [LPC_631XESB] = { + .name = "631xESB/632xESB", + .iTCO_version = 2, + .gpio_version = ICH_V6_GPIO, + }, + [LPC_ICH7] = { + .name = "ICH7 or ICH7R", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH7DH] = { + .name = "ICH7DH", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH7M] = { + .name = "ICH7-M or ICH7-U", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH7MDH] = { + .name = "ICH7-M DH", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_NM10] = { + .name = "NM10", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH8] = { + .name = "ICH8 or ICH8R", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH8DH] = { + .name = "ICH8DH", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH8DO] = { + .name = "ICH8DO", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH8M] = { + .name = "ICH8M", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH8ME] = { + .name = "ICH8M-E", + .iTCO_version = 2, + .gpio_version = ICH_V7_GPIO, + }, + [LPC_ICH9] = { + .name = "ICH9", + .iTCO_version = 2, + .gpio_version = ICH_V9_GPIO, + }, + [LPC_ICH9R] = { + .name = "ICH9R", + .iTCO_version = 2, + .gpio_version = ICH_V9_GPIO, + }, + [LPC_ICH9DH] = { + .name = "ICH9DH", + .iTCO_version = 2, + .gpio_version = ICH_V9_GPIO, + }, + [LPC_ICH9DO] = { + .name = "ICH9DO", + .iTCO_version = 2, + .gpio_version = ICH_V9_GPIO, + }, + [LPC_ICH9M] = { + .name = "ICH9M", + .iTCO_version = 2, + .gpio_version = ICH_V9_GPIO, + }, + [LPC_ICH9ME] = { + .name = "ICH9M-E", + .iTCO_version = 2, + .gpio_version = ICH_V9_GPIO, + }, + [LPC_ICH10] = { + .name = "ICH10", + .iTCO_version = 2, + .gpio_version = ICH_V10CONS_GPIO, + }, + [LPC_ICH10R] = { + .name = "ICH10R", + .iTCO_version = 2, + .gpio_version = ICH_V10CONS_GPIO, + }, + [LPC_ICH10D] = { + .name = "ICH10D", + .iTCO_version = 2, + .gpio_version = ICH_V10CORP_GPIO, + }, + [LPC_ICH10DO] = { + .name = "ICH10DO", + .iTCO_version = 2, + .gpio_version = ICH_V10CORP_GPIO, + }, + [LPC_PCH] = { + .name = "PCH Desktop Full Featured", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_PCHM] = { + .name = "PCH Mobile Full Featured", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_P55] = { + .name = "P55", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_PM55] = { + .name = "PM55", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_H55] = { + .name = "H55", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_QM57] = { + .name = "QM57", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_H57] = { + .name = "H57", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_HM55] = { + .name = "HM55", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_Q57] = { + .name = "Q57", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_HM57] = { + .name = "HM57", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_PCHMSFF] = { + .name = "PCH Mobile SFF Full Featured", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_QS57] = { + .name = "QS57", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_3400] = { + .name = "3400", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_3420] = { + .name = "3420", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_3450] = { + .name = "3450", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_EP80579] = { + .name = "EP80579", + .iTCO_version = 2, + }, + [LPC_CPT] = { + .name = "Cougar Point", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_CPTD] = { + .name = "Cougar Point Desktop", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_CPTM] = { + .name = "Cougar Point Mobile", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_PBG] = { + .name = "Patsburg", + .iTCO_version = 2, + }, + [LPC_DH89XXCC] = { + .name = "DH89xxCC", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_PPT] = { + .name = "Panther Point", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_LPT] = { + .name = "Lynx Point", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + .spi_type = INTEL_SPI_LPT, + }, + [LPC_LPT_LP] = { + .name = "Lynx Point_LP", + .iTCO_version = 2, + .spi_type = INTEL_SPI_LPT, + }, + [LPC_WBG] = { + .name = "Wellsburg", + .iTCO_version = 2, + }, + [LPC_AVN] = { + .name = "Avoton SoC", + .iTCO_version = 3, + .gpio_version = AVOTON_GPIO, + .spi_type = INTEL_SPI_BYT, + }, + [LPC_BAYTRAIL] = { + .name = "Bay Trail SoC", + .iTCO_version = 3, + .spi_type = INTEL_SPI_BYT, + }, + [LPC_COLETO] = { + .name = "Coleto Creek", + .iTCO_version = 2, + }, + [LPC_WPT_LP] = { + .name = "Wildcat Point_LP", + .iTCO_version = 2, + .spi_type = INTEL_SPI_LPT, + }, + [LPC_BRASWELL] = { + .name = "Braswell SoC", + .iTCO_version = 3, + .spi_type = INTEL_SPI_BYT, + }, + [LPC_LEWISBURG] = { + .name = "Lewisburg", + .iTCO_version = 2, + }, + [LPC_9S] = { + .name = "9 Series", + .iTCO_version = 2, + .gpio_version = ICH_V5_GPIO, + }, + [LPC_APL] = { + .name = "Apollo Lake SoC", + .iTCO_version = 5, + .gpio_info = &apl_gpio_info, + .spi_type = INTEL_SPI_BXT, + }, + [LPC_DNV] = { + .name = "Denverton SoC", + .gpio_info = &dnv_gpio_info, + }, + [LPC_GLK] = { + .name = "Gemini Lake SoC", + .spi_type = INTEL_SPI_BXT, + }, + [LPC_COUGARMOUNTAIN] = { + .name = "Cougar Mountain SoC", + .iTCO_version = 3, + }, +}; + +/* + * This data only exists for exporting the supported PCI ids + * via MODULE_DEVICE_TABLE. We do not actually register a + * pci_driver, because the I/O Controller Hub has also other + * functions that probably will be registered by other drivers. + */ +static const struct pci_device_id lpc_ich_ids[] = { + { PCI_VDEVICE(INTEL, 0x0f1c), .driver_data = LPC_BAYTRAIL }, + { PCI_VDEVICE(INTEL, 0x19dc), .driver_data = LPC_DNV }, + { PCI_VDEVICE(INTEL, 0x1c41), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c42), .driver_data = LPC_CPTD }, + { PCI_VDEVICE(INTEL, 0x1c43), .driver_data = LPC_CPTM }, + { PCI_VDEVICE(INTEL, 0x1c44), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c45), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c46), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c47), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c48), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c49), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4a), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4b), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4c), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4d), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4e), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c4f), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c50), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c51), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c52), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c53), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c54), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c55), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c56), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c57), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c58), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c59), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5a), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5b), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5c), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5d), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5e), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1c5f), .driver_data = LPC_CPT }, + { PCI_VDEVICE(INTEL, 0x1d40), .driver_data = LPC_PBG }, + { PCI_VDEVICE(INTEL, 0x1d41), .driver_data = LPC_PBG }, + { PCI_VDEVICE(INTEL, 0x1e40), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e41), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e42), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e43), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e44), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e45), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e46), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e47), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e48), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e49), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4a), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4b), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4c), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4d), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4e), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e4f), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e50), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e51), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e52), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e53), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e54), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e55), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e56), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e57), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e58), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e59), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5a), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5b), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5c), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5d), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5e), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1e5f), .driver_data = LPC_PPT }, + { PCI_VDEVICE(INTEL, 0x1f38), .driver_data = LPC_AVN }, + { PCI_VDEVICE(INTEL, 0x1f39), .driver_data = LPC_AVN }, + { PCI_VDEVICE(INTEL, 0x1f3a), .driver_data = LPC_AVN }, + { PCI_VDEVICE(INTEL, 0x1f3b), .driver_data = LPC_AVN }, + { PCI_VDEVICE(INTEL, 0x229c), .driver_data = LPC_BRASWELL }, + { PCI_VDEVICE(INTEL, 0x2310), .driver_data = LPC_DH89XXCC }, + { PCI_VDEVICE(INTEL, 0x2390), .driver_data = LPC_COLETO }, + { PCI_VDEVICE(INTEL, 0x2410), .driver_data = LPC_ICH }, + { PCI_VDEVICE(INTEL, 0x2420), .driver_data = LPC_ICH0 }, + { PCI_VDEVICE(INTEL, 0x2440), .driver_data = LPC_ICH2 }, + { PCI_VDEVICE(INTEL, 0x244c), .driver_data = LPC_ICH2M }, + { PCI_VDEVICE(INTEL, 0x2450), .driver_data = LPC_CICH }, + { PCI_VDEVICE(INTEL, 0x2480), .driver_data = LPC_ICH3 }, + { PCI_VDEVICE(INTEL, 0x248c), .driver_data = LPC_ICH3M }, + { PCI_VDEVICE(INTEL, 0x24c0), .driver_data = LPC_ICH4 }, + { PCI_VDEVICE(INTEL, 0x24cc), .driver_data = LPC_ICH4M }, + { PCI_VDEVICE(INTEL, 0x24d0), .driver_data = LPC_ICH5 }, + { PCI_VDEVICE(INTEL, 0x25a1), .driver_data = LPC_6300ESB }, + { PCI_VDEVICE(INTEL, 0x2640), .driver_data = LPC_ICH6 }, + { PCI_VDEVICE(INTEL, 0x2641), .driver_data = LPC_ICH6M }, + { PCI_VDEVICE(INTEL, 0x2642), .driver_data = LPC_ICH6W }, + { PCI_VDEVICE(INTEL, 0x2670), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2671), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2672), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2673), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2674), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2675), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2676), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2677), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2678), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x2679), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267a), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267b), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267c), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267d), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267e), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x267f), .driver_data = LPC_631XESB }, + { PCI_VDEVICE(INTEL, 0x27b0), .driver_data = LPC_ICH7DH }, + { PCI_VDEVICE(INTEL, 0x27b8), .driver_data = LPC_ICH7 }, + { PCI_VDEVICE(INTEL, 0x27b9), .driver_data = LPC_ICH7M }, + { PCI_VDEVICE(INTEL, 0x27bc), .driver_data = LPC_NM10 }, + { PCI_VDEVICE(INTEL, 0x27bd), .driver_data = LPC_ICH7MDH }, + { PCI_VDEVICE(INTEL, 0x2810), .driver_data = LPC_ICH8 }, + { PCI_VDEVICE(INTEL, 0x2811), .driver_data = LPC_ICH8ME }, + { PCI_VDEVICE(INTEL, 0x2812), .driver_data = LPC_ICH8DH }, + { PCI_VDEVICE(INTEL, 0x2814), .driver_data = LPC_ICH8DO }, + { PCI_VDEVICE(INTEL, 0x2815), .driver_data = LPC_ICH8M }, + { PCI_VDEVICE(INTEL, 0x2912), .driver_data = LPC_ICH9DH }, + { PCI_VDEVICE(INTEL, 0x2914), .driver_data = LPC_ICH9DO }, + { PCI_VDEVICE(INTEL, 0x2916), .driver_data = LPC_ICH9R }, + { PCI_VDEVICE(INTEL, 0x2917), .driver_data = LPC_ICH9ME }, + { PCI_VDEVICE(INTEL, 0x2918), .driver_data = LPC_ICH9 }, + { PCI_VDEVICE(INTEL, 0x2919), .driver_data = LPC_ICH9M }, + { PCI_VDEVICE(INTEL, 0x2b9c), .driver_data = LPC_COUGARMOUNTAIN }, + { PCI_VDEVICE(INTEL, 0x3197), .driver_data = LPC_GLK }, + { PCI_VDEVICE(INTEL, 0x31e8), .driver_data = LPC_GLK }, + { PCI_VDEVICE(INTEL, 0x3a14), .driver_data = LPC_ICH10DO }, + { PCI_VDEVICE(INTEL, 0x3a16), .driver_data = LPC_ICH10R }, + { PCI_VDEVICE(INTEL, 0x3a18), .driver_data = LPC_ICH10 }, + { PCI_VDEVICE(INTEL, 0x3a1a), .driver_data = LPC_ICH10D }, + { PCI_VDEVICE(INTEL, 0x3b00), .driver_data = LPC_PCH }, + { PCI_VDEVICE(INTEL, 0x3b01), .driver_data = LPC_PCHM }, + { PCI_VDEVICE(INTEL, 0x3b02), .driver_data = LPC_P55 }, + { PCI_VDEVICE(INTEL, 0x3b03), .driver_data = LPC_PM55 }, + { PCI_VDEVICE(INTEL, 0x3b06), .driver_data = LPC_H55 }, + { PCI_VDEVICE(INTEL, 0x3b07), .driver_data = LPC_QM57 }, + { PCI_VDEVICE(INTEL, 0x3b08), .driver_data = LPC_H57 }, + { PCI_VDEVICE(INTEL, 0x3b09), .driver_data = LPC_HM55 }, + { PCI_VDEVICE(INTEL, 0x3b0a), .driver_data = LPC_Q57 }, + { PCI_VDEVICE(INTEL, 0x3b0b), .driver_data = LPC_HM57 }, + { PCI_VDEVICE(INTEL, 0x3b0d), .driver_data = LPC_PCHMSFF }, + { PCI_VDEVICE(INTEL, 0x3b0f), .driver_data = LPC_QS57 }, + { PCI_VDEVICE(INTEL, 0x3b12), .driver_data = LPC_3400 }, + { PCI_VDEVICE(INTEL, 0x3b14), .driver_data = LPC_3420 }, + { PCI_VDEVICE(INTEL, 0x3b16), .driver_data = LPC_3450 }, + { PCI_VDEVICE(INTEL, 0x5031), .driver_data = LPC_EP80579 }, + { PCI_VDEVICE(INTEL, 0x5ae8), .driver_data = LPC_APL }, + { PCI_VDEVICE(INTEL, 0x8c40), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c41), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c42), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c43), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c44), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c45), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c46), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c47), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c48), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c49), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4a), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4b), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4c), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4d), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4e), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c4f), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c50), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c51), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c52), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c53), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c54), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c55), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c56), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c57), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c58), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c59), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5a), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5b), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5c), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5d), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5e), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8c5f), .driver_data = LPC_LPT }, + { PCI_VDEVICE(INTEL, 0x8cc1), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8cc2), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8cc3), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8cc4), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8cc6), .driver_data = LPC_9S }, + { PCI_VDEVICE(INTEL, 0x8d40), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d41), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d42), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d43), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d44), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d45), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d46), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d47), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d48), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d49), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4a), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4b), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4c), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4d), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4e), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d4f), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d50), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d51), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d52), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d53), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d54), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d55), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d56), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d57), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d58), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d59), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5a), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5b), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5c), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5d), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5e), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x8d5f), .driver_data = LPC_WBG }, + { PCI_VDEVICE(INTEL, 0x9c40), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c41), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c42), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c43), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c44), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c45), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c46), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9c47), .driver_data = LPC_LPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc1), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc2), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc3), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc5), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc6), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc7), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0x9cc9), .driver_data = LPC_WPT_LP }, + { PCI_VDEVICE(INTEL, 0xa1c1), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c2), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c3), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c4), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c5), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c6), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa1c7), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa242), .driver_data = LPC_LEWISBURG }, + { PCI_VDEVICE(INTEL, 0xa243), .driver_data = LPC_LEWISBURG }, + { }, /* End of list */ +}; +MODULE_DEVICE_TABLE(pci, lpc_ich_ids); + +static void lpc_ich_restore_config_space(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + + if (priv->abase_save >= 0) { + pci_write_config_byte(dev, priv->abase, priv->abase_save); + priv->abase_save = -1; + } + + if (priv->actrl_pbase_save >= 0) { + pci_write_config_byte(dev, priv->actrl_pbase, + priv->actrl_pbase_save); + priv->actrl_pbase_save = -1; + } + + if (priv->gctrl_save >= 0) { + pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); + priv->gctrl_save = -1; + } +} + +static void lpc_ich_enable_acpi_space(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + u8 reg_save; + + switch (lpc_chipset_info[priv->chipset].iTCO_version) { + case 3: + /* + * Some chipsets (eg Avoton) enable the ACPI space in the + * ACPI BASE register. + */ + pci_read_config_byte(dev, priv->abase, ®_save); + pci_write_config_byte(dev, priv->abase, reg_save | 0x2); + priv->abase_save = reg_save; + break; + default: + /* + * Most chipsets enable the ACPI space in the ACPI control + * register. + */ + pci_read_config_byte(dev, priv->actrl_pbase, ®_save); + pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); + priv->actrl_pbase_save = reg_save; + break; + } +} + +static void lpc_ich_enable_gpio_space(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + u8 reg_save; + + pci_read_config_byte(dev, priv->gctrl, ®_save); + pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); + priv->gctrl_save = reg_save; +} + +static void lpc_ich_enable_pmc_space(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + u8 reg_save; + + pci_read_config_byte(dev, priv->actrl_pbase, ®_save); + pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); + + priv->actrl_pbase_save = reg_save; +} + +static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev) +{ + struct itco_wdt_platform_data *pdata; + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + struct lpc_ich_info *info; + struct mfd_cell *cell = &lpc_ich_wdt_cell; + + pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + info = &lpc_chipset_info[priv->chipset]; + + pdata->version = info->iTCO_version; + strscpy(pdata->name, info->name, sizeof(pdata->name)); + + cell->platform_data = pdata; + cell->pdata_size = sizeof(*pdata); + return 0; +} + +static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + struct mfd_cell *cell = &lpc_ich_gpio_cell; + + cell->platform_data = &lpc_chipset_info[priv->chipset]; + cell->pdata_size = sizeof(struct lpc_ich_info); +} + +/* + * We don't check for resource conflict globally. There are 2 or 3 independent + * GPIO groups and it's enough to have access to one of these to instantiate + * the device. + */ +static int lpc_ich_check_conflict_gpio(struct resource *res) +{ + int ret; + u8 use_gpio = 0; + + if (resource_size(res) >= 0x50 && + !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) + use_gpio |= 1 << 2; + + if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) + use_gpio |= 1 << 1; + + ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); + if (!ret) + use_gpio |= 1 << 0; + + return use_gpio ? use_gpio : ret; +} + +static int lpc_ich_init_gpio(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + u32 base_addr_cfg; + u32 base_addr; + int ret; + bool acpi_conflict = false; + struct resource *res; + + /* Setup power management base register */ + pci_read_config_dword(dev, priv->abase, &base_addr_cfg); + base_addr = base_addr_cfg & 0x0000ff80; + if (!base_addr) { + dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); + lpc_ich_gpio_cell.num_resources--; + goto gpe0_done; + } + + res = &gpio_ich_res[ICH_RES_GPE0]; + res->start = base_addr + ACPIBASE_GPE_OFF; + res->end = base_addr + ACPIBASE_GPE_END; + ret = acpi_check_resource_conflict(res); + if (ret) { + /* + * This isn't fatal for the GPIO, but we have to make sure that + * the platform_device subsystem doesn't see this resource + * or it will register an invalid region. + */ + lpc_ich_gpio_cell.num_resources--; + acpi_conflict = true; + } else { + lpc_ich_enable_acpi_space(dev); + } + +gpe0_done: + /* Setup GPIO base register */ + pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); + base_addr = base_addr_cfg & 0x0000ff80; + if (!base_addr) { + dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); + ret = -ENODEV; + goto gpio_done; + } + + /* Older devices provide fewer GPIO and have a smaller resource size. */ + res = &gpio_ich_res[ICH_RES_GPIO]; + res->start = base_addr; + switch (lpc_chipset_info[priv->chipset].gpio_version) { + case ICH_V5_GPIO: + case ICH_V10CORP_GPIO: + res->end = res->start + 128 - 1; + break; + default: + res->end = res->start + 64 - 1; + break; + } + + ret = lpc_ich_check_conflict_gpio(res); + if (ret < 0) { + /* this isn't necessarily fatal for the GPIO */ + acpi_conflict = true; + goto gpio_done; + } + lpc_chipset_info[priv->chipset].use_gpio = ret; + lpc_ich_enable_gpio_space(dev); + + lpc_ich_finalize_gpio_cell(dev); + ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, + &lpc_ich_gpio_cell, 1, NULL, 0, NULL); + +gpio_done: + if (acpi_conflict) + pr_warn("Resource conflict(s) found affecting %s\n", + lpc_ich_gpio_cell.name); + return ret; +} + +static int lpc_ich_init_wdt(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + u32 base_addr_cfg; + u32 base_addr; + int ret; + struct resource *res; + + /* If we have ACPI based watchdog use that instead */ + if (acpi_has_watchdog()) + return -ENODEV; + + /* Setup power management base register */ + pci_read_config_dword(dev, priv->abase, &base_addr_cfg); + base_addr = base_addr_cfg & 0x0000ff80; + if (!base_addr) { + dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); + ret = -ENODEV; + goto wdt_done; + } + + res = wdt_io_res(ICH_RES_IO_TCO); + res->start = base_addr + ACPIBASE_TCO_OFF; + res->end = base_addr + ACPIBASE_TCO_END; + + res = wdt_io_res(ICH_RES_IO_SMI); + res->start = base_addr + ACPIBASE_SMI_OFF; + res->end = base_addr + ACPIBASE_SMI_END; + + lpc_ich_enable_acpi_space(dev); + + /* + * iTCO v2: + * Get the Memory-Mapped GCS register. To get access to it + * we have to read RCBA from PCI Config space 0xf0 and use + * it as base. GCS = RCBA + ICH6_GCS(0x3410). + * + * iTCO v3: + * Get the Power Management Configuration register. To get access + * to it we have to read the PMC BASE from config space and address + * the register at offset 0x8. + */ + if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { + /* Don't register iomem for TCO ver 1 */ + lpc_ich_wdt_cell.num_resources--; + } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { + pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); + base_addr = base_addr_cfg & 0xffffc000; + if (!(base_addr_cfg & 1)) { + dev_notice(&dev->dev, "RCBA is disabled by " + "hardware/BIOS, device disabled\n"); + ret = -ENODEV; + goto wdt_done; + } + res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); + res->start = base_addr + ACPIBASE_GCS_OFF; + res->end = base_addr + ACPIBASE_GCS_END; + } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { + lpc_ich_enable_pmc_space(dev); + pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg); + base_addr = base_addr_cfg & 0xfffffe00; + + res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); + res->start = base_addr + ACPIBASE_PMC_OFF; + res->end = base_addr + ACPIBASE_PMC_END; + } + + ret = lpc_ich_finalize_wdt_cell(dev); + if (ret) + goto wdt_done; + + ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, + &lpc_ich_wdt_cell, 1, NULL, 0, NULL); + +wdt_done: + return ret; +} + +static int lpc_ich_init_pinctrl(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info; + struct resource base; + unsigned int i; + int ret; + + /* Check, if GPIO has been exported as an ACPI device */ + if (acpi_dev_present(info->hid, NULL, -1)) + return -EEXIST; + + ret = p2sb_bar(dev->bus, 0, &base); + if (ret) + return ret; + + for (i = 0; i < info->nr_resources; i++) { + struct resource *mem = info->resources[i]; + resource_size_t offset = info->offsets[i]; + + /* Fill MEM resource */ + mem->start = base.start + offset; + mem->end = base.start + offset + INTEL_GPIO_RESOURCE_SIZE - 1; + mem->flags = base.flags; + } + + return mfd_add_devices(&dev->dev, 0, info->devices, info->nr_devices, + NULL, 0, NULL); +} + +static bool lpc_ich_byt_set_writeable(void __iomem *base, void *data) +{ + u32 val; + + val = readl(base + BYT_BCR); + if (!(val & BYT_BCR_WPD)) { + val |= BYT_BCR_WPD; + writel(val, base + BYT_BCR); + val = readl(base + BYT_BCR); + } + + return val & BYT_BCR_WPD; +} + +static bool lpc_ich_set_writeable(struct pci_bus *bus, unsigned int devfn) +{ + u32 bcr; + + pci_bus_read_config_dword(bus, devfn, BCR, &bcr); + if (!(bcr & BCR_WPD)) { + bcr |= BCR_WPD; + pci_bus_write_config_dword(bus, devfn, BCR, bcr); + pci_bus_read_config_dword(bus, devfn, BCR, &bcr); + } + + return bcr & BCR_WPD; +} + +static bool lpc_ich_lpt_set_writeable(void __iomem *base, void *data) +{ + struct pci_dev *pdev = data; + + return lpc_ich_set_writeable(pdev->bus, pdev->devfn); +} + +static bool lpc_ich_bxt_set_writeable(void __iomem *base, void *data) +{ + struct pci_dev *pdev = data; + + return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2)); +} + +static int lpc_ich_init_spi(struct pci_dev *dev) +{ + struct lpc_ich_priv *priv = pci_get_drvdata(dev); + struct resource *res = &intel_spi_res[0]; + struct intel_spi_boardinfo *info; + u32 spi_base, rcba; + int ret; + + info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + info->type = lpc_chipset_info[priv->chipset].spi_type; + + switch (info->type) { + case INTEL_SPI_BYT: + pci_read_config_dword(dev, SPIBASE_BYT, &spi_base); + if (spi_base & SPIBASE_BYT_EN) { + res->start = ALIGN_DOWN(spi_base, SPIBASE_BYT_SZ); + res->end = res->start + SPIBASE_BYT_SZ - 1; + + info->set_writeable = lpc_ich_byt_set_writeable; + } + break; + + case INTEL_SPI_LPT: + pci_read_config_dword(dev, RCBABASE, &rcba); + if (rcba & 1) { + spi_base = round_down(rcba, SPIBASE_LPT_SZ); + res->start = spi_base + SPIBASE_LPT; + res->end = res->start + SPIBASE_LPT_SZ - 1; + + info->set_writeable = lpc_ich_lpt_set_writeable; + info->data = dev; + } + break; + + case INTEL_SPI_BXT: + /* + * The P2SB is hidden by BIOS and we need to unhide it in + * order to read BAR of the SPI flash device. Once that is + * done we hide it again. + */ + ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res); + if (ret) + return ret; + + info->set_writeable = lpc_ich_bxt_set_writeable; + info->data = dev; + break; + + default: + return -EINVAL; + } + + if (!res->start) + return -ENODEV; + + lpc_ich_spi_cell.platform_data = info; + lpc_ich_spi_cell.pdata_size = sizeof(*info); + + return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE, + &lpc_ich_spi_cell, 1, NULL, 0, NULL); +} + +static int lpc_ich_probe(struct pci_dev *dev, + const struct pci_device_id *id) +{ + struct lpc_ich_priv *priv; + int ret; + bool cell_added = false; + + priv = devm_kzalloc(&dev->dev, + sizeof(struct lpc_ich_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->chipset = id->driver_data; + + priv->actrl_pbase_save = -1; + priv->abase_save = -1; + + priv->abase = ACPIBASE; + priv->actrl_pbase = ACPICTRL_PMCBASE; + + priv->gctrl_save = -1; + if (priv->chipset <= LPC_ICH5) { + priv->gbase = GPIOBASE_ICH0; + priv->gctrl = GPIOCTRL_ICH0; + } else { + priv->gbase = GPIOBASE_ICH6; + priv->gctrl = GPIOCTRL_ICH6; + } + + pci_set_drvdata(dev, priv); + + if (lpc_chipset_info[priv->chipset].iTCO_version) { + ret = lpc_ich_init_wdt(dev); + if (!ret) + cell_added = true; + } + + if (lpc_chipset_info[priv->chipset].gpio_version) { + ret = lpc_ich_init_gpio(dev); + if (!ret) + cell_added = true; + } + + if (lpc_chipset_info[priv->chipset].gpio_info) { + ret = lpc_ich_init_pinctrl(dev); + if (!ret) + cell_added = true; + } + + if (lpc_chipset_info[priv->chipset].spi_type) { + ret = lpc_ich_init_spi(dev); + if (!ret) + cell_added = true; + } + + /* + * We only care if at least one or none of the cells registered + * successfully. + */ + if (!cell_added) { + dev_warn(&dev->dev, "No MFD cells added\n"); + lpc_ich_restore_config_space(dev); + return -ENODEV; + } + + return 0; +} + +static void lpc_ich_remove(struct pci_dev *dev) +{ + mfd_remove_devices(&dev->dev); + lpc_ich_restore_config_space(dev); +} + +static struct pci_driver lpc_ich_driver = { + .name = "lpc_ich", + .id_table = lpc_ich_ids, + .probe = lpc_ich_probe, + .remove = lpc_ich_remove, +}; + +module_pci_driver(lpc_ich_driver); + +MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); +MODULE_DESCRIPTION("LPC interface for Intel ICH"); +MODULE_LICENSE("GPL"); |