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Diffstat (limited to 'Documentation/devicetree/bindings/pinctrl')
263 files changed, 41541 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt b/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt new file mode 100644 index 000000000..c591b9cb5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/abilis,tb10x-iomux.txt @@ -0,0 +1,80 @@ +Abilis Systems TB10x pin controller +=================================== + +Required properties +------------------- + +- compatible: should be "abilis,tb10x-iomux"; +- reg: should contain the physical address and size of the pin controller's + register range. + + +Function definitions +-------------------- + +Functions are defined (and referenced) by sub-nodes of the pin controller. +Every sub-node defines exactly one function (implying a set of pins). +Every function is associated to one named pin group inside the pin controller +driver and these names are used to associate pin group predefinitions to pin +controller sub-nodes. + +Required function definition subnode properties: + - abilis,function: should be set to the name of the function's pin group. + +The following pin groups are available: + - GPIO ports: gpioa, gpiob, gpioc, gpiod, gpioe, gpiof, gpiog, + gpioh, gpioi, gpioj, gpiok, gpiol, gpiom, gpion + - Serial TS input ports: mis0, mis1, mis2, mis3, mis4, mis5, mis6, mis7 + - Parallel TS input ports: mip1, mip3, mip5, mip7 + - Serial TS output ports: mos0, mos1, mos2, mos3 + - Parallel TS output port: mop + - CI+ port: ciplus + - CableCard (Mcard) port: mcard + - Smart card ports: stc0, stc1 + - UART ports: uart0, uart1 + - SPI ports: spi1, spi3 + - JTAG: jtag + +All other ports of the chip are not multiplexed and thus not managed by this +driver. + + +GPIO ranges definition +---------------------- + +The named pin groups of GPIO ports can be used to define GPIO ranges as +explained in Documentation/devicetree/bindings/gpio/gpio.txt. + + +Example +------- + +iomux: iomux@ff10601c { + compatible = "abilis,tb10x-iomux"; + reg = <0xFF10601c 0x4>; + pctl_gpio_a: pctl-gpio-a { + abilis,function = "gpioa"; + }; + pctl_uart0: pctl-uart0 { + abilis,function = "uart0"; + }; +}; +uart@ff100000 { + compatible = "snps,dw-apb-uart"; + reg = <0xFF100000 0x100>; + clock-frequency = <166666666>; + interrupts = <25 1>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pctl_uart0>; +}; +gpioa: gpio@ff140000 { + compatible = "abilis,tb10x-gpio"; + reg = <0xFF140000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + ngpio = <3>; + gpio-ranges = <&iomux 0 0>; + gpio-ranges-group-names = "gpioa"; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml new file mode 100644 index 000000000..7cb8a747f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S500 SoC pinmux & GPIO controller + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + - Cristian Ciocaltea <cristian.ciocaltea@gmail.com> + +description: | + Pinmux & GPIO controller manages pin multiplexing & configuration including + GPIO function selection & GPIO attributes configuration. Please refer to + pinctrl-bindings.txt in this directory for common binding part and usage. + +properties: + compatible: + const: actions,s500-pinctrl + + reg: + items: + - description: GPIO Output + GPIO Input + GPIO Data + - description: Multiplexing Control + - description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control + - description: PAD Drive Capacity Select + minItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + '#gpio-cells': + description: + Specifies the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the pin number and flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + interrupts: + description: + One interrupt per each of the 5 GPIO ports supported by the controller, + sorted by port number ascending order. + minItems: 5 + maxItems: 5 + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: + Pinctrl node's client devices specify pin muxes using subnodes, + which in turn use the standard properties below. + $ref: pinmux-node.yaml# + + properties: + groups: + description: + List of gpio pin groups affected by the functions specified in + this subnode. + items: + oneOf: + - enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp, + rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp, + rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp, + i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp, + ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp, + ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, + dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp, + dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp, + spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp, + dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, + uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, + uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, + pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, + dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp, + nand_ceb3_mfp] + minItems: 1 + maxItems: 32 + + function: + description: + Specify the alternative function to be configured for the + given gpio pin groups. + enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, + i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m, + mipi_csi, nand, spdif, ts, lcd0] + + required: + - groups + - function + + additionalProperties: false + + '^(.*-)?pinconf$': + type: object + description: + Pinctrl node's client devices specify pin configurations using + subnodes, which in turn use the standard properties below. + $ref: pincfg-node.yaml# + + properties: + groups: + description: + List of gpio pin groups affected by the drive-strength property + specified in this subnode. + items: + oneOf: + - enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv, + rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv, + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, + i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, + lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv, + sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv, + spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv, + i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, + sens0_ckout_drv, uart3_all_drv] + minItems: 1 + maxItems: 32 + + pins: + description: + List of gpio pins affected by the bias-pull-* and + input-schmitt-* properties specified in this subnode. + items: + oneOf: + - enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen, + eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, + i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1, + ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, + lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, + lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, + lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3, + dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0, + dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, + sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, + uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk, + sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, + dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb, + uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk, + i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, + csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3, + csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3, + dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb, + dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1, + pkg2, pkg3] + minItems: 1 + maxItems: 64 + + bias-pull-up: true + bias-pull-down: true + + drive-strength: + description: + Selects the drive strength for the specified pins, in mA. + enum: [2, 4, 8, 12] + + input-schmitt-enable: true + input-schmitt-disable: true + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - gpio-controller + - gpio-ranges + - '#gpio-cells' + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl: pinctrl@b01b0000 { + compatible = "actions,s500-pinctrl"; + reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>, + <0xb01b0060 0x18>, <0xb01b0080 0xc>; + clocks = <&cmu 55>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 132>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + + mmc0_pins: mmc0-pins { + pinmux { + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", + "sd0_cmd_mfp", "sd0_clk_mfp"; + function = "sd0"; + }; + + drv-pinconf { + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; + drive-strength = <8>; + }; + + bias-pinconf { + pins = "sd0_d0", "sd0_d1", "sd0_d2", + "sd0_d3", "sd0_cmd"; + bias-pull-up; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.yaml new file mode 100644 index 000000000..9597b983c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s700-pinctrl.yaml @@ -0,0 +1,204 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s700-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S700 Pin Controller + +maintainers: + - Manivannan Sadhasivam <mani@kernel.org> + +properties: + compatible: + const: actions,s700-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-line-names: + maxItems: 136 + + gpio-ranges: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 5 + description: + The interrupt outputs from the controller. There is one GPIO interrupt per + GPIO bank. The interrupts must be ordered by bank, starting with + bank 0. + +additionalProperties: + type: object + description: Pin configuration subnode + additionalProperties: false + + properties: + pinmux: + description: Configure pin multiplexing. + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp, + rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp, + rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp, + i2c1_dummy, i2c2_dummy, i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp, + i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, + ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, + dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp, + lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, + dsi_dnp1_cp_d2_mfp, dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, + dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, + uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, + uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, + pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, + dnand_acle_ce0_mfp, nand_ceb2_mfp, nand_ceb3_mfp + ] + + function: + items: + enum: [ + nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, pcm1, + pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0, sd0, sd1, + sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30, clko_25m, mipi_csi, + nand, spdif, sirq0, sirq1, sirq2, bt, lcd0 + ] + + required: + - groups + - function + + pinconf: + description: Configure pin-specific parameters. + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv, + rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv, + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv, + pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv, + dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, + spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv, + i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, sens0_ckout_drv, + uart3_all_drv + ] + + pins: + items: + enum: [ + eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer, + eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2, + ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp, + lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap, + lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp, + lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, + lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, + dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, + sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, + sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx, uart2_rx, + uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, + uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk, i2c1_sdata, + i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1, csi_cn, csi_cp, + csi_dn2, csi_dp2, csi_dn3, csi_dp3, sensor0_pclk, sensor0_ckout, + dnand_d0, dnand_d1, dnand_d2, dnand_d3, dnand_d4, dnand_d5, + dnand_d6, dnand_d7, dnand_wrb, dnand_rdb, dnand_rdbn, dnand_dqs, + dnand_dqsn, dnand_rb0, dnand_ale, dnand_cle, dnand_ceb0, + dnand_ceb1, dnand_ceb2, dnand_ceb3, porb, clko_25m, bsel, pkg0, + pkg1, pkg2, pkg3 + ] + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + description: Selects the drive strength for the specified pins in mA. + enum: [2, 4, 8, 12] + + input-schmitt-enable: true + input-schmitt-disable: true + + oneOf: + - required: + - groups + - required: + - pins + + anyOf: + - required: [ pinmux ] + - required: [ pinconf ] + +required: + - compatible + - reg + - clocks + - gpio-controller + - gpio-ranges + - '#gpio-cells' + - interrupt-controller + - '#interrupt-cells' + - interrupts + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s700-pinctrl"; + reg = <0xe01b0000 0x1000>; + clocks = <&cmu 1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 136>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + + uart3-default { + pinmux { + groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp"; + function = "uart3"; + }; + pinconf { + groups = "uart3_all_drv"; + drive-strength = <2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.yaml new file mode 100644 index 000000000..5c7b9f132 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s900-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S900 Pin Controller + +maintainers: + - Manivannan Sadhasivam <mani@kernel.org> + +properties: + compatible: + const: actions,s900-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 6 + description: The interrupt outputs from the controller. There is one GPIO + interrupt per GPIO bank. The number of interrupts listed depends on the + number of GPIO banks on the SoC. The interrupts must be ordered by bank, + starting with bank 0. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-line-names: + maxItems: 146 + + gpio-ranges: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + - clocks + - gpio-controller + - gpio-ranges + - "#gpio-cells" + +additionalProperties: + type: object + description: Pin configuration subnode + additionalProperties: false + + properties: + pinmux: + type: object + description: Pin mux configuration + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ + lvds_oxx_uart4_mfp, rmii_mdc_mfp, rmii_mdio_mfp, sirq0_mfp, + sirq1_mfp, rmii_txd0_mfp, rmii_txd1_mfp, rmii_txen_mfp, + rmii_rxer_mfp, rmii_crs_dv_mfp, rmii_rxd1_mfp, rmii_rxd0_mfp, + rmii_ref_clk_mfp, i2s_d0_mfp, i2s_d1_mfp, i2s_lr_m_clk0_mfp, + i2s_bclk0_mfp, i2s_bclk1_mclk1_mfp, pcm1_in_out_mfp, pcm1_clk_mfp, + pcm1_sync_mfp, eram_a5_mfp, eram_a6_mfp, eram_a7_mfp, eram_a8_mfp, + eram_a9_mfp, eram_a10_mfp, eram_a11_mfp, lvds_oep_odn_mfp, + lvds_ocp_obn_mfp, lvds_oap_oan_mfp, lvds_e_mfp, + spi0_sclk_mosi_mfp, spi0_ss_mfp, spi0_miso_mfp, uart2_rtsb_mfp, + uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, + sd0_d1_mfp, sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, + sd0_clk_mfp, sd1_cmd_clk_mfp, uart0_rx_mfp, nand0_d0_ceb3_mfp, + uart0_tx_mfp, i2c0_mfp, csi0_cn_cp_mfp, csi0_dn0_dp3_mfp, + csi1_dn0_cp_mfp, dsi_dp3_dn1_mfp, dsi_cp_dn0_mfp, dsi_dp2_dn2_mfp, + nand1_d0_ceb1_mfp, nand1_ceb3_mfp, nand1_ceb0_mfp, + csi1_dn0_dp0_mfp, uart4_rx_tx_mfp + ] + + function: + items: + enum: [ + eram, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1, + pcm0, pcm1, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, sd0, + sd1, sd2, sd3, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, lvds, + usb30, usb20, gpu, mipi_csi0, mipi_csi1, mipi_dsi, nand0, + nand1, spdif, sirq0, sirq1, sirq2 + ] + + required: + - groups + - function + + pinconf: + type: object + description: Pin configuration parameters + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + additionalProperties: false + + properties: + groups: + items: + enum: [ + # pin groups for drive strength + sgpio3_drv, sgpio2_drv, sgpio1_drv, sgpio0_drv, rmii_tx_d0_d1_drv, + rmii_txen_rxer_drv, rmii_crs_dv_drv, rmii_rx_d1_d0_drv, + rmii_ref_clk_drv, rmii_mdc_mdio_drv, sirq_0_1_drv, sirq2_drv, + i2s_d0_d1_drv, i2s_lr_m_clk0_drv, i2s_blk1_mclk1_drv, + pcm1_in_out_drv, lvds_oap_oan_drv, lvds_oep_odn_drv, + lvds_ocp_obn_drv, lvds_e_drv, sd0_d3_d0_drv, sd1_d3_d0_drv, + sd0_sd1_cmd_clk_drv, spi0_sclk_mosi_drv, spi0_ss_miso_drv, + uart0_rx_tx_drv, uart4_rx_tx_drv, uart2_drv, uart3_drv, i2c0_drv, + i2c1_drv, i2c2_drv, sensor0_drv, + # pin groups for slew rate + sgpio3_sr, sgpio2_sr, sgpio1_sr, sgpio0_sr, rmii_tx_d0_d1_sr, + rmii_txen_rxer_sr, rmii_crs_dv_sr, rmii_rx_d1_d0_sr, + rmii_ref_clk_sr, rmii_mdc_mdio_sr, sirq_0_1_sr, sirq2_sr, + i2s_do_d1_sr, i2s_lr_m_clk0_sr, i2s_bclk0_mclk1_sr, + pcm1_in_out_sr, sd1_d3_d0_sr, sd0_sd1_clk_cmd_sr, + spi0_sclk_mosi_sr, spi0_ss_miso_sr, uart0_rx_tx_sr, + uart4_rx_tx_sr, uart2_sr, uart3_sr, i2c0_sr, i2c1_sr, i2c2_sr, + sensor0_sr + ] + + pins: + items: + enum: [ + eth_txd0, eth_txd1, eth_txen, eth_rxer, eth_crs_dv, eth_rxd1, + eth_rxd0, eth_ref_clk, eth_mdc, eth_mdio, sirq0, sirq1, sirq2, + i2s_d0, i2s_bclk0, i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, + i2s_lrclk1, i2s_mclk1, pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, + eram_a5, eram_a6, eram_a7, eram_a8, eram_a9, eram_a10, eram_a11, + lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, lvds_ocn, + lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, lvds_een, + lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, lvds_ebn, + lvds_eap, lvds_ean, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, + sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, uart0_tx, + uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx, + uart3_rtsb, uart3_ctsb, uart4_rx, uart4_tx, i2c0_sclk, i2c0_sdata, + i2c1_sclk, i2c1_sdata, i2c2_sclk, i2c2_sdata, csi0_dn0, csi0_dp0, + csi0_dn1, csi0_dp1, csi0_cn, csi0_cp, csi0_dn2, csi0_dp2, + csi0_dn3, csi0_dp3, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, + dsi_cn, dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sensor0_pclk, + csi1_dn0, csi1_dp0, csi1_dn1, csi1_dp1, csi1_cn, csi1_cp, + sensor0_ckout, nand0_d0, nand0_d1, nand0_d2, nand0_d3, nand0_d4, + nand0_d5, nand0_d6, nand0_d7, nand0_dqs, nand0_dqsn, nand0_ale, + nand0_cle, nand0_ceb0, nand0_ceb1, nand0_ceb2, nand0_ceb3, + nand1_d0, nand1_d1, nand1_d2, nand1_d3, nand1_d4, nand1_d5, + nand1_d6, nand1_d7, nand1_dqs, nand1_dqsn, nand1_ale, nand1_cle, + nand1_ceb0, nand1_ceb1, nand1_ceb2, nand1_ceb3, sgpio0, sgpio1, + sgpio2, sgpio3 + ] + + bias-bus-hold: true + bias-high-impedance: true + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + input-schmitt-enable: true + input-schmitt-disable: true + slew-rate: true + drive-strength: true + + oneOf: + - required: + - groups + - required: + - pins + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl: pinctrl@e01b0000 { + compatible = "actions,s900-pinctrl"; + reg = <0xe01b0000 0x1000>; + clocks = <&cmu 1>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + + uart2-default { + pinmux { + groups = "lvds_oep_odn_mfp"; + function = "uart2"; + }; + + pinconf { + groups = "lvds_oep_odn_drv"; + drive-strength = <12>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml new file mode 100644 index 000000000..79910214d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,an7583-pinctrl.yaml @@ -0,0 +1,402 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,an7583-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN7583 Pin Controller + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The Airoha's AN7583 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,an7583-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, + phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: tod_1pps + then: + properties: + groups: + enum: [pon_tod_1pps, gsw_tod_1pps] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, + uart4, uart5] + maxItems: 2 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c1] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pcm_spi + then: + properties: + groups: + items: + enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, + pcm_spi_cs2, pcm_spi_cs3, pcm_spi_cs4] + maxItems: 7 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2s] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + enum: [emmc] + - if: + properties: + function: + const: pnand + then: + properties: + groups: + enum: [pnand] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio1, gpio2, gpio3, gpio4] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio8, gpio9, gpio10, gpio11] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk, + spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, + gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, + gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40, + gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, + pcie_reset0, pcie_reset1, pcie_reset2] + minItems: 1 + maxItems: 58 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl { + compatible = "airoha,an7583-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2", "uart2_cts_rts"; + }; + }; + + uar5-pins { + mux { + function = "uart"; + groups = "uart5"; + }; + }; + + mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml new file mode 100644 index 000000000..21fd4f1ba --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/airoha,en7581-pinctrl.yaml @@ -0,0 +1,403 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/airoha,en7581-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha EN7581 Pin Controller + +maintainers: + - Lorenzo Bianconi <lorenzo@kernel.org> + +description: + The Airoha's EN7581 Pin controller is used to control SoC pins. + +properties: + compatible: + const: airoha,en7581-pinctrl + + interrupts: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - interrupts + - gpio-controller + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-pins$': + type: object + + patternProperties: + '^mux(-|$)': + type: object + + description: + pinmux configuration nodes. + + $ref: /schemas/pinctrl/pinmux-node.yaml + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [pon, tod_1pps, sipo, mdio, uart, i2c, jtag, pcm, spi, + pcm_spi, i2s, emmc, pnand, pcie_reset, pwm, phy1_led0, + phy2_led0, phy3_led0, phy4_led0, phy1_led1, phy2_led1, + phy3_led1, phy4_led1] + + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: pon + then: + properties: + groups: + enum: [pon] + - if: + properties: + function: + const: tod_1pps + then: + properties: + groups: + enum: [pon_tod_1pps, gsw_tod_1pps] + - if: + properties: + function: + const: sipo + then: + properties: + groups: + enum: [sipo, sipo_rclk] + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart2, uart2_cts_rts, hsuart, hsuart_cts_rts, + uart4, uart5] + maxItems: 2 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c1] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag_udi, jtag_dfd] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm1, pcm2] + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi_quad, spi_cs1] + maxItems: 2 + - if: + properties: + function: + const: pcm_spi + then: + properties: + groups: + items: + enum: [pcm_spi, pcm_spi_int, pcm_spi_rst, pcm_spi_cs1, + pcm_spi_cs2_p156, pcm_spi_cs2_p128, pcm_spi_cs3, + pcm_spi_cs4] + maxItems: 7 + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2s] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + enum: [emmc] + - if: + properties: + function: + const: pnand + then: + properties: + groups: + enum: [pnand] + - if: + properties: + function: + const: pcie_reset + then: + properties: + groups: + enum: [pcie_reset0, pcie_reset1, pcie_reset2] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, + gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, + gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio29, gpio30, gpio31, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, + gpio42, gpio43, gpio44, gpio45, gpio46, gpio47] + - if: + properties: + function: + const: phy1_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy2_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy3_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy4_led0 + then: + properties: + groups: + enum: [gpio33, gpio34, gpio35, gpio42] + - if: + properties: + function: + const: phy1_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy2_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy3_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + - if: + properties: + function: + const: phy4_led1 + then: + properties: + groups: + enum: [gpio43, gpio44, gpio45, gpio46] + + additionalProperties: false + + '^conf(-|$)': + type: object + + description: + pinconf configuration nodes. + + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [uart1_txd, uart1_rxd, i2c_scl, i2c_sda, spi_cs0, spi_clk, + spi_mosi, spi_miso, gpio0, gpio1, gpio2, gpio3, gpio4, + gpio5, gpio6, gpio7, gpio8, gpio9, gpio10, gpio11, gpio12, + gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, gpio26, + gpio27, gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, + gpio34, gpio35, gpio36, gpio37, gpio38, gpio39, gpio40, + gpio41, gpio42, gpio43, gpio44, gpio45, gpio46, + pcie_reset0, pcie_reset1, pcie_reset2] + minItems: 1 + maxItems: 58 + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-enable: true + + output-low: true + + output-high: true + + drive-open-drain: true + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 6, 8] + + required: + - pins + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl { + compatible = "airoha,en7581-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + pcie1-rst-pins { + conf { + pins = "pcie_reset1"; + drive-open-drain = <1>; + }; + }; + + pwm-pins { + mux { + function = "pwm"; + groups = "gpio18"; + }; + }; + + spi-pins { + mux { + function = "spi"; + groups = "spi_quad", "spi_cs1"; + }; + }; + + uart2-pins { + mux { + function = "uart"; + groups = "uart2", "uart2_cts_rts"; + }; + }; + + uar5-pins { + mux { + function = "uart"; + groups = "uart5"; + }; + }; + + mmc-pins { + mux { + function = "emmc"; + groups = "emmc"; + }; + }; + + mdio-pins { + mux { + function = "mdio"; + groups = "mdio"; + }; + + conf { + pins = "gpio2"; + output-enable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml new file mode 100644 index 000000000..45b7a0b6c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -0,0 +1,315 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A10 Pin Controller + +maintainers: + - Chen-Yu Tsai <wens@csie.org> + - Maxime Ripard <mripard@kernel.org> + +properties: + "#gpio-cells": + const: 3 + description: + GPIO consumers must use three arguments, first the number of the + bank, then the pin number inside that bank, and finally the GPIO + flags. + + "#interrupt-cells": + const: 3 + description: + Interrupts consumers must use three arguments, first the number + of the bank, then the pin number inside that bank, and finally + the interrupts flags. + + compatible: + enum: + - allwinner,sun4i-a10-pinctrl + - allwinner,sun5i-a10s-pinctrl + - allwinner,sun5i-a13-pinctrl + - allwinner,sun6i-a31-pinctrl + - allwinner,sun6i-a31-r-pinctrl + - allwinner,sun6i-a31s-pinctrl + - allwinner,sun7i-a20-pinctrl + - allwinner,sun8i-a23-pinctrl + - allwinner,sun8i-a23-r-pinctrl + - allwinner,sun8i-a33-pinctrl + - allwinner,sun8i-a83t-pinctrl + - allwinner,sun8i-a83t-r-pinctrl + - allwinner,sun8i-h3-pinctrl + - allwinner,sun8i-h3-r-pinctrl + - allwinner,sun8i-r40-pinctrl + - allwinner,sun8i-v3-pinctrl + - allwinner,sun8i-v3s-pinctrl + - allwinner,sun8i-v853-pinctrl + - allwinner,sun9i-a80-pinctrl + - allwinner,sun9i-a80-r-pinctrl + - allwinner,sun20i-d1-pinctrl + - allwinner,sun50i-a64-pinctrl + - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-pinctrl + - allwinner,sun50i-a100-r-pinctrl + - allwinner,sun50i-h5-pinctrl + - allwinner,sun50i-h6-pinctrl + - allwinner,sun50i-h6-r-pinctrl + - allwinner,sun50i-h616-pinctrl + - allwinner,sun50i-h616-r-pinctrl + - allwinner,suniv-f1c100s-pinctrl + - nextthing,gr8-pinctrl + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 8 + description: + One interrupt per external interrupt bank supported on the + controller, sorted by bank number ascending order. + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: apb + - const: hosc + - const: losc + + gpio-controller: true + interrupt-controller: true + gpio-line-names: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 8 + +patternProperties: + # It's pretty scary, but the basic idea is that: + # - One node name can start with either s- or r- for PRCM nodes, + # - Then, the name itself can be any repetition of <string>- (to + # accommodate with nodes like uart4-rts-cts-pins), where each + # string can be either starting with 'p' but in a string longer + # than 3, or something that doesn't start with 'p', + # - Then, the bank name is optional and will be between pa and pg, + # pl or pm. Some pins groups that have several options will have + # the pin numbers then, + # - Finally, the name will end with either -pin or pins. + + "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z0-9][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$": + type: object + + properties: + pins: true + function: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 30, 40] + + required: + - pins + - function + + additionalProperties: false + + "^vcc-p[a-ilm]-supply$": + description: + Power supplies for pin banks. + +required: + - "#gpio-cells" + - compatible + - reg + - clocks + - clock-names + - gpio-controller + +allOf: + # FIXME: We should have the pin bank supplies here, but not a lot of + # boards are defining it at the moment so it would generate a lot of + # warnings. + + - $ref: pinctrl.yaml# + - if: + not: + properties: + compatible: + enum: + - allwinner,sun50i-h616-r-pinctrl + + then: + required: + - "#interrupt-cells" + - interrupts + - interrupt-controller + + - if: + properties: + compatible: + enum: + - allwinner,sun50i-h616-pinctrl + + then: + properties: + interrupts: + minItems: 8 + + - if: + properties: + compatible: + enum: + - allwinner,sun50i-a100-pinctrl + + then: + properties: + interrupts: + minItems: 7 + maxItems: 7 + + - if: + properties: + compatible: + enum: + - allwinner,sun8i-v853-pinctrl + + then: + properties: + interrupts: + minItems: 8 + maxItems: 8 + + - if: + properties: + compatible: + enum: + - allwinner,sun20i-d1-pinctrl + + then: + properties: + interrupts: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + enum: + - allwinner,sun9i-a80-pinctrl + + then: + properties: + interrupts: + minItems: 5 + maxItems: 5 + + - if: + properties: + compatible: + enum: + - allwinner,sun6i-a31-pinctrl + - allwinner,sun6i-a31s-pinctrl + - allwinner,sun50i-h6-pinctrl + + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + + - if: + properties: + compatible: + enum: + - allwinner,sun8i-a23-pinctrl + - allwinner,sun8i-a83t-pinctrl + - allwinner,sun50i-a64-pinctrl + - allwinner,sun50i-h5-pinctrl + - allwinner,suniv-f1c100s-pinctrl + + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 + + - if: + properties: + compatible: + enum: + - allwinner,sun6i-a31-r-pinctrl + - allwinner,sun8i-a33-pinctrl + - allwinner,sun8i-h3-pinctrl + - allwinner,sun8i-v3-pinctrl + - allwinner,sun8i-v3s-pinctrl + - allwinner,sun9i-a80-r-pinctrl + - allwinner,sun50i-h6-r-pinctrl + + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + enum: + - allwinner,sun4i-a10-pinctrl + - allwinner,sun5i-a10s-pinctrl + - allwinner,sun5i-a13-pinctrl + - allwinner,sun7i-a20-pinctrl + - allwinner,sun8i-a23-r-pinctrl + - allwinner,sun8i-a83t-r-pinctrl + - allwinner,sun8i-h3-r-pinctrl + - allwinner,sun8i-r40-pinctrl + - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-r-pinctrl + - nextthing,gr8-pinctrl + + then: + properties: + interrupts: + minItems: 1 + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/sun5i-ccu.h> + + pio: pinctrl@1c20800 { + compatible = "allwinner,sun5i-a13-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <28>; + clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart1_pe_pins: uart1-pe-pins { + pins = "PE10", "PE11"; + function = "uart1"; + }; + + uart1_pg_pins: uart1-pg-pins { + pins = "PG3", "PG4"; + function = "uart1"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml new file mode 100644 index 000000000..154e03da8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun55i-a523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 Pin Controller + +maintainers: + - Andre Przywara <andre.przywara@arm.com> + +properties: + "#gpio-cells": + const: 3 + description: + GPIO consumers must use three arguments, first the number of the + bank, then the pin number inside that bank, and finally the GPIO + flags. + + "#interrupt-cells": + const: 3 + description: + Interrupts consumers must use three arguments, first the number + of the bank, then the pin number inside that bank, and finally + the interrupts flags. + + compatible: + enum: + - allwinner,sun55i-a523-pinctrl + - allwinner,sun55i-a523-r-pinctrl + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 10 + description: + One interrupt per external interrupt bank supported on the + controller, sorted by bank number ascending order. + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: apb + - const: hosc + - const: losc + + gpio-controller: true + interrupt-controller: true + gpio-line-names: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 10 + +patternProperties: + # It's pretty scary, but the basic idea is that: + # - One node name can start with either s- or r- for PRCM nodes, + # - Then, the name itself can be any repetition of <string>- (to + # accommodate with nodes like uart4-rts-cts-pins), where each + # string can be either starting with 'p' but in a string longer + # than 3, or something that doesn't start with 'p', + # - Then, the bank name is optional and will be between pa and pm. + # Some pins groups that have several options will have the pin + # numbers then, + # - Finally, the name will end with either -pin or pins. + + "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-m][0-9]*?-)??pins?$": + type: object + + properties: + pins: true + function: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 30, 40] + + allwinner,pinmux: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Pinmux selector value, for each pin. Almost every time this value + is the same for all pins, so any array shorter than the number of + pins will repeat the last value, to allow just specifying a single + cell, for all cells. + + required: + - pins + - allwinner,pinmux + - function + + additionalProperties: false + + "^vcc-p[a-m]-supply$": + description: + Power supplies for pin banks. + +required: + - "#gpio-cells" + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#interrupt-cells" + - interrupts + - interrupt-controller + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-pinctrl + + then: + properties: + interrupts: + minItems: 10 + maxItems: 10 + + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-r-pinctrl + + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + +additionalProperties: false + +examples: + - | + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun55i-a523-r-pinctrl"; + reg = <0x7022000 0x800>; + interrupts = <0 159 4>, <0 161 4>; + clocks = <&r_ccu 1>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + allwinner,pinmux = <2>; + function = "r_i2c0"; + bias-pull-up; + }; + + r_spi_pins: r-spi-pins { + pins = "PL11" ,"PL12", "PL13"; + allwinner,pinmux = <6>; + function = "r_spi"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml new file mode 100644 index 000000000..d9e0b2c48 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-a1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson A1 pinmux controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: amlogic,meson-pinctrl-common.yaml# + +properties: + compatible: + enum: + - amlogic,c3-periphs-pinctrl + - amlogic,t7-periphs-pinctrl + - amlogic,meson-a1-periphs-pinctrl + - amlogic,meson-s4-periphs-pinctrl + +required: + - compatible + +patternProperties: + "^bank@[0-9a-f]+$": + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio + + unevaluatedProperties: false + + properties: + reg: + maxItems: 2 + + reg-names: + items: + - const: mux + - const: gpio + + gpio-line-names: + minItems: 62 # A1 + maxItems: 82 # S4 + +unevaluatedProperties: + type: object + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins + +examples: + - | + periphs_pinctrl: pinctrl { + compatible = "amlogic,meson-a1-periphs-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + bank@400 { + reg = <0x0400 0x003c>, + <0x0480 0x0118>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 62>; + }; + + cec_ao_a_h_pins: cec_ao_a_h { + mux { + groups = "cec_ao_a_h"; + function = "cec_ao_a_h"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml new file mode 100644 index 000000000..e707c222a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-common.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson pinmux controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: pinctrl.yaml# + +properties: + ranges: true + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] + +required: + - ranges + - "#address-cells" + - "#size-cells" + +additionalProperties: true + +$defs: + meson-gpio: + type: object + + properties: + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 1 + + patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + + required: + - gpio-hog + + required: + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + + meson-pins: + type: object + additionalProperties: + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml new file mode 100644 index 000000000..108719bde --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-g12a-aobus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson G12 AOBUS pinmux controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: amlogic,meson-pinctrl-common.yaml# + +properties: + compatible: + enum: + - amlogic,meson-g12a-aobus-pinctrl + +required: + - compatible + +patternProperties: + "^bank@[0-9a-f]+$": + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio + + unevaluatedProperties: false + + properties: + reg: + maxItems: 3 + + reg-names: + items: + - const: mux + - const: ds + - const: gpio + + gpio-line-names: + maxItems: 15 + +unevaluatedProperties: + type: object + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins + +examples: + - | + ao_pinctrl: pinctrl { + compatible = "amlogic,meson-g12a-aobus-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + bank@14 { + reg = <0x14 0x8>, + <0x1c 0x8>, + <0x24 0x14>; + reg-names = "mux", "ds", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&ao_pinctrl 0 0 15>; + }; + + cec_ao_a_h_pins: cec_ao_a_h { + mux { + groups = "cec_ao_a_h"; + function = "cec_ao_a_h"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml new file mode 100644 index 000000000..dc277f2e2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,meson-pinctrl-g12a-periphs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson G12 PERIPHS pinmux controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: amlogic,meson-pinctrl-common.yaml# + +properties: + compatible: + enum: + - amlogic,meson-g12a-periphs-pinctrl + +required: + - compatible + +patternProperties: + "^bank@[0-9a-f]+$": + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio + + unevaluatedProperties: false + + properties: + reg: + maxItems: 5 + + reg-names: + items: + - const: gpio + - const: pull + - const: pull-enable + - const: mux + - const: ds + + gpio-line-names: + maxItems: 85 + +unevaluatedProperties: + type: object + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins + +examples: + - | + periphs_pinctrl: pinctrl { + compatible = "amlogic,meson-g12a-periphs-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + bank@40 { + reg = <0x40 0x4c>, + <0xe8 0x18>, + <0x120 0x18>, + <0x2c0 0x40>, + <0x340 0x1c>; + reg-names = "gpio", "pull", "pull-enable", "mux", "ds"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 86>; + }; + + cec_ao_a_h_pins: cec_ao_a_h { + mux { + groups = "cec_ao_a_h"; + function = "cec_ao_a_h"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml new file mode 100644 index 000000000..add83c676 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-aobus.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,meson8-pinctrl-aobus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson8 AOBUS pinmux controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: amlogic,meson-pinctrl-common.yaml# + +properties: + compatible: + oneOf: + - enum: + - amlogic,meson8-aobus-pinctrl + - amlogic,meson8b-aobus-pinctrl + - amlogic,meson-gxbb-aobus-pinctrl + - amlogic,meson-gxl-aobus-pinctrl + - amlogic,meson-axg-aobus-pinctrl + - items: + - const: amlogic,meson8m2-aobus-pinctrl + - const: amlogic,meson8-aobus-pinctrl + +required: + - compatible + +patternProperties: + "^bank@[0-9a-f]+$": + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio + + unevaluatedProperties: false + + properties: + reg: + maxItems: 3 + + reg-names: + items: + - const: mux + - const: pull + - const: gpio + + gpio-line-names: + minItems: 11 # GXL + maxItems: 16 # Meson8 + +unevaluatedProperties: + type: object + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins + +examples: + - | + pinctrl_aobus: pinctrl { + compatible = "amlogic,meson8-aobus-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + bank@14 { + reg = <0x14 0x4>, + <0x2c 0x4>, + <0x24 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 0 16>; + }; + + cec_ao_a_h_pins: cec_ao_a_h { + mux { + groups = "cec_ao_a_h"; + function = "cec_ao_a_h"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml new file mode 100644 index 000000000..c954761e0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,meson8-pinctrl-cbus.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,meson8-pinctrl-cbus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Meson8 CBUS pinmux controller + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +allOf: + - $ref: amlogic,meson-pinctrl-common.yaml# + +properties: + compatible: + oneOf: + - enum: + - amlogic,meson8-cbus-pinctrl + - amlogic,meson8b-cbus-pinctrl + - amlogic,meson-gxbb-periphs-pinctrl + - amlogic,meson-gxl-periphs-pinctrl + - amlogic,meson-axg-periphs-pinctrl + - items: + - const: amlogic,meson8m2-cbus-pinctrl + - const: amlogic,meson8-cbus-pinctrl + +required: + - compatible + +patternProperties: + "^bank@[0-9a-f]+$": + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-gpio + + unevaluatedProperties: false + + properties: + reg: + maxItems: 4 + + reg-names: + items: + - const: mux + - const: pull + - const: pull-enable + - const: gpio + + gpio-line-names: + minItems: 83 # Meson8b + maxItems: 120 # Meson8 + +unevaluatedProperties: + type: object + $ref: amlogic,meson-pinctrl-common.yaml#/$defs/meson-pins + +examples: + - | + pinctrl_cbus: pinctrl { + compatible = "amlogic,meson8-cbus-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + bank@80b0 { + reg = <0x80b0 0x28>, + <0x80e8 0x18>, + <0x8120 0x18>, + <0x8030 0x30>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_cbus 0 0 120>; + }; + + cec_ao_a_h_pins: cec_ao_a_h { + mux { + groups = "cec_ao_a_h"; + function = "cec_ao_a_h"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml new file mode 100644 index 000000000..6ba66c203 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,pinctrl-a4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic pinmux controller + +maintainers: + - Xianwei Zhao <xianwei.zhao@amlogic.com> + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + oneOf: + - enum: + - amlogic,pinctrl-a4 + - amlogic,pinctrl-s6 + - amlogic,pinctrl-s7 + - items: + - enum: + - amlogic,pinctrl-a5 + - const: amlogic,pinctrl-a4 + - items: + - enum: + - amlogic,pinctrl-s7d + - const: amlogic,pinctrl-s7 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + + additionalProperties: false + properties: + reg: + minItems: 1 + items: + - description: pin config register + - description: pin mux setting register (some special pin fixed function) + - description: pin drive strength register (optional) + + reg-names: + minItems: 1 + items: + - const: gpio + - const: mux + - const: ds + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 1 + + required: + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + + "^func-[0-9a-z-]+$": + type: object + additionalProperties: false + patternProperties: + "^group-[0-9a-z-]+$": + type: object + unevaluatedProperties: false + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + + required: + - pinmux + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/amlogic,pinctrl.h> + apb { + #address-cells = <2>; + #size-cells = <2>; + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-a4"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio@4240 { + reg = <0 0x4240 0 0x40>, <0 0x4000 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 8 10>; + }; + + func-uart-b { + group-default { + pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 1, 4)>; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + group-pins1 { + pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 5, 2)>; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + func-uart-c { + group-default { + pinmux = <AML_PINMUX(AMLOGIC_GPIO_B, 3, 1)>, + <AML_PINMUX(AMLOGIC_GPIO_B, 2, 1)>; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml new file mode 100644 index 000000000..41073176b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple GPIO controller + +maintainers: + - Mark Kettenis <kettenis@openbsd.org> + +description: | + The Apple GPIO controller is a simple combined pin and GPIO + controller present on Apple ARM SoC platforms, including various + iPhone and iPad devices and the "Apple Silicon" Macs. + +properties: + compatible: + oneOf: + - items: + - enum: + - apple,t6020-pinctrl + - apple,t8122-pinctrl + - const: apple,t8103-pinctrl + - items: + # Do not add additional SoC to this list. + - enum: + - apple,s5l8960x-pinctrl + - apple,t7000-pinctrl + - apple,s8000-pinctrl + - apple,t8010-pinctrl + - apple,t8015-pinctrl + - apple,t8103-pinctrl + - apple,t8112-pinctrl + - apple,t6000-pinctrl + - const: apple,pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + apple,npins: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of pins in this GPIO controller. + + interrupts: + description: One interrupt for each of the (up to 7) interrupt + groups supported by the controller sorted by interrupt group + number in ascending order. + minItems: 1 + maxItems: 7 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + power-domains: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + Values are constructed from pin number and alternate function + configuration number using the APPLE_PINMUX() helper macro + defined in include/dt-bindings/pinctrl/apple.h. + + required: + - pinmux + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - apple,npins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/apple-aic.h> + #include <dt-bindings/pinctrl/apple.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@23c100000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3c100000 0x0 0x100000>; + clocks = <&gpio_clk>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 212>; + apple,npins = <212>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = <AIC_IRQ 16 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 17 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 18 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 19 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 20 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 21 IRQ_TYPE_LEVEL_HIGH>, + <AIC_IRQ 22 IRQ_TYPE_LEVEL_HIGH>; + + pcie_pins: pcie-pins { + pinmux = <APPLE_PINMUX(150, 1)>, + <APPLE_PINMUX(151, 1)>, + <APPLE_PINMUX(32, 1)>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml new file mode 100644 index 000000000..23ed9a8b6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml @@ -0,0 +1,223 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2400 Pin Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + + - compatible: Should be one of the following: + "aspeed,ast2400-scu", "syscon", "simple-mfd" + + Refer to the bindings described in + Documentation/devicetree/bindings/mfd/syscon.yaml + +properties: + compatible: + const: aspeed,ast2400-pinctrl + reg: + maxItems: 2 + +additionalProperties: + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + pins: true + bias-disable: true + + patternProperties: + "^function|groups$": + enum: + - ACPI + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - BMCINT + - DDCCLK + - DDCDAT + - EXTRST + - FLACK + - FLBUSY + - FLWP + - GPID + - GPID0 + - GPID2 + - GPID4 + - GPID6 + - GPIE0 + - GPIE2 + - GPIE4 + - GPIE6 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - LPCPD + - LPCPME + - LPCRST + - LPCSMI + - MAC1LINK + - MAC2LINK + - MDIO1 + - MDIO2 + - NCTS1 + - NCTS2 + - NCTS3 + - NCTS4 + - NDCD1 + - NDCD2 + - NDCD3 + - NDCD4 + - NDSR1 + - NDSR2 + - NDSR3 + - NDSR4 + - NDTR1 + - NDTR2 + - NDTR3 + - NDTR4 + - NDTS4 + - NRI1 + - NRI2 + - NRI3 + - NRI4 + - NRTS1 + - NRTS2 + - NRTS3 + - OSCCLK + - PWM0 + - PWM1 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - RGMII1 + - RGMII2 + - RMII1 + - RMII2 + - ROM16 + - ROM8 + - ROMCS1 + - ROMCS2 + - ROMCS3 + - ROMCS4 + - RXD1 + - RXD2 + - RXD3 + - RXD4 + - SALT1 + - SALT2 + - SALT3 + - SALT4 + - SD1 + - SD2 + - SGPMCK + - SGPMI + - SGPMLD + - SGPMO + - SGPSCK + - SGPSI0 + - SGPSI1 + - SGPSLD + - SIOONCTRL + - SIOPBI + - SIOPBO + - SIOPWREQ + - SIOPWRGD + - SIOS3 + - SIOS5 + - SIOSCI + - SPI1 + - SPI1DEBUG + - SPI1PASSTHRU + - SPICS1 + - TIMER3 + - TIMER4 + - TIMER5 + - TIMER6 + - TIMER7 + - TIMER8 + - TXD1 + - TXD2 + - TXD3 + - TXD4 + - UART6 + - USB11D1 + - USB11H2 + - USB2D1 + - USB2H1 + - USBCKI + - VGABIOS_ROM + - VGAHS + - VGAVS + - VPI18 + - VPI24 + - VPI30 + - VPO12 + - VPO24 + - WDTRST1 + - WDTRST2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +examples: + - | + syscon: scu@1e6e2000 { + compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6e2000 0x1000>; + + pinctrl: pinctrl { + compatible = "aspeed,ast2400-pinctrl"; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_gpioh0_unbiased_default: gpioh0 { + pins = "A8"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml new file mode 100644 index 000000000..35bd0e1ea --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -0,0 +1,253 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2500 Pin Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + + - compatible: Should be one of the following: + "aspeed,ast2500-scu", "syscon", "simple-mfd" + "aspeed,g5-scu", "syscon", "simple-mfd" + + Refer to the bindings described in + Documentation/devicetree/bindings/mfd/syscon.yaml + +properties: + compatible: + const: aspeed,ast2500-pinctrl + reg: + maxItems: 2 + + aspeed,external-nodes: + minItems: 2 + maxItems: 2 + items: + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + A cell of phandles to external controller nodes: + 0: compatible with "aspeed,ast2500-gfx", "syscon" + 1: compatible with "aspeed,ast2500-lpc", "syscon" + +additionalProperties: + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + pins: true + bias-disable: true + + patternProperties: + "^function|groups$": + enum: + - ACPI + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - BMCINT + - DDCCLK + - DDCDAT + - ESPI + - FWSPICS1 + - FWSPICS2 + - GPID0 + - GPID2 + - GPID4 + - GPID6 + - GPIE0 + - GPIE2 + - GPIE4 + - GPIE6 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - LAD0 + - LAD1 + - LAD2 + - LAD3 + - LCLK + - LFRAME + - LPCHC + - LPCPD + - LPCPLUS + - LPCPME + - LPCRST + - LPCSMI + - LSIRQ + - MAC1LINK + - MAC2LINK + - MDIO1 + - MDIO2 + - NCTS1 + - NCTS2 + - NCTS3 + - NCTS4 + - NDCD1 + - NDCD2 + - NDCD3 + - NDCD4 + - NDSR1 + - NDSR2 + - NDSR3 + - NDSR4 + - NDTR1 + - NDTR2 + - NDTR3 + - NDTR4 + - NRI1 + - NRI2 + - NRI3 + - NRI4 + - NRTS1 + - NRTS2 + - NRTS3 + - NRTS4 + - OSCCLK + - PEWAKE + - PNOR + - PWM0 + - PWM1 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - RGMII1 + - RGMII2 + - RMII1 + - RMII2 + - RXD1 + - RXD2 + - RXD3 + - RXD4 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SCL1 + - SCL2 + - SD1 + - SD2 + - SDA1 + - SDA2 + - SGPM + - SGPS1 + - SGPS2 + - SIOONCTRL + - SIOPBI + - SIOPBO + - SIOPWREQ + - SIOPWRGD + - SIOS3 + - SIOS5 + - SIOSCI + - SPI1 + - SPI1CS1 + - SPI1DEBUG + - SPI1PASSTHRU + - SPI2CK + - SPI2CS0 + - SPI2CS1 + - SPI2MISO + - SPI2MOSI + - TIMER3 + - TIMER4 + - TIMER5 + - TIMER6 + - TIMER7 + - TIMER8 + - TXD1 + - TXD2 + - TXD3 + - TXD4 + - UART6 + - USB11BHID + - USB2AD + - USB2AH + - USB2BD + - USB2BH + - USBCKI + - VGABIOSROM + - VGAHS + - VGAVS + - VPI24 + - VPO + - WDTRST1 + - WDTRST2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - aspeed,external-nodes + +examples: + - | + #include <dt-bindings/clock/aspeed-clock.h> + scu@1e6e2000 { + compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1a8>; + #clock-cells = <1>; + #reset-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6e2000 0x1000>; + + pinctrl: pinctrl { + compatible = "aspeed,ast2500-pinctrl"; + aspeed,external-nodes = <&gfx>, <&lhc>; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_gpioh0_unbiased_default: gpioh0 { + pins = "A18"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml new file mode 100644 index 000000000..af8979af9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -0,0 +1,537 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2600-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2600 Pin Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + + - compatible: Should be one of the following: + "aspeed,ast2600-scu", "syscon", "simple-mfd" + + Refer to the bindings described in + Documentation/devicetree/bindings/mfd/syscon.yaml + + Note: According to the NCSI specification, the reference clock output pin + (RMIIXRCLKO) is not required on the management controller side. To optimize + pin usage, add "NCSI" pin groups that are equivalent to the RMII pin groups, + but without the RMIIXRCLKO pin. + +properties: + compatible: + const: aspeed,ast2600-pinctrl + +additionalProperties: + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - BMCINT + - EMMC + - ESPI + - ESPIALT + - FSI1 + - FSI2 + - FWQSPI + - FWSPIABR + - FWSPID + - FWSPIWP + - GPIT0 + - GPIT1 + - GPIT2 + - GPIT3 + - GPIT4 + - GPIT5 + - GPIT6 + - GPIT7 + - GPIU0 + - GPIU1 + - GPIU2 + - GPIU3 + - GPIU4 + - GPIU5 + - GPIU6 + - GPIU7 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C16 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I3C1 + - I3C2 + - I3C3 + - I3C4 + - I3C5 + - I3C6 + - JTAGM + - LHPD + - LHSIRQ + - LPC + - LPCHC + - LPCPD + - LPCPME + - LPCSMI + - LSIRQ + - MACLINK1 + - MACLINK2 + - MACLINK3 + - MACLINK4 + - MDIO1 + - MDIO2 + - MDIO3 + - MDIO4 + - NCTS1 + - NCTS2 + - NCTS3 + - NCTS4 + - NDCD1 + - NDCD2 + - NDCD3 + - NDCD4 + - NDSR1 + - NDSR2 + - NDSR3 + - NDSR4 + - NDTR1 + - NDTR2 + - NDTR3 + - NDTR4 + - NRI1 + - NRI2 + - NRI3 + - NRI4 + - NRTS1 + - NRTS2 + - NRTS3 + - NRTS4 + - OSCCLK + - PCIERC1 + - PEWAKE + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - RGMII1 + - RGMII2 + - RGMII3 + - RGMII4 + - RMII1 + - RMII2 + - RMII3 + - RMII4 + - RXD1 + - RXD2 + - RXD3 + - RXD4 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT16 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD1 + - SD2 + - SGPM1 + - SGPM2 + - SGPS1 + - SGPS2 + - SIOONCTRL + - SIOPBI + - SIOPBO + - SIOPWREQ + - SIOPWRGD + - SIOS3 + - SIOS5 + - SIOSCI + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WP + - SPI2 + - SPI2CS1 + - SPI2CS2 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - TXD1 + - TXD2 + - TXD3 + - TXD4 + - UART10 + - UART11 + - UART12 + - UART13 + - UART6 + - UART7 + - UART8 + - UART9 + - USB11BHID + - USB2AD + - USB2AH + - USB2AHP + - USB2BD + - USB2BH + - USBAD + - USBADP + - VB + - VGAHS + - VGAVS + - WDTRST1 + - WDTRST2 + - WDTRST3 + - WDTRST4 + + groups: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - BMCINT + - EMMCG1 + - EMMCG4 + - EMMCG8 + - ESPI + - ESPIALT + - FSI1 + - FSI2 + - FWQSPI + - FWSPIABR + - FWSPID + - FWSPIWP + - GPIT0 + - GPIT1 + - GPIT2 + - GPIT3 + - GPIT4 + - GPIT5 + - GPIT6 + - GPIT7 + - GPIU0 + - GPIU1 + - GPIU2 + - GPIU3 + - GPIU4 + - GPIU5 + - GPIU6 + - GPIU7 + - HVI3C3 + - HVI3C4 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C16 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I3C1 + - I3C2 + - I3C3 + - I3C4 + - I3C5 + - I3C6 + - JTAGM + - LHPD + - LHSIRQ + - LPC + - LPCHC + - LPCPD + - LPCPME + - LPCSMI + - LSIRQ + - MACLINK1 + - MACLINK2 + - MACLINK3 + - MACLINK4 + - MDIO1 + - MDIO2 + - MDIO3 + - MDIO4 + - NCSI3 + - NCSI4 + - NCTS1 + - NCTS2 + - NCTS3 + - NCTS4 + - NDCD1 + - NDCD2 + - NDCD3 + - NDCD4 + - NDSR1 + - NDSR2 + - NDSR3 + - NDSR4 + - NDTR1 + - NDTR2 + - NDTR3 + - NDTR4 + - NRI1 + - NRI2 + - NRI3 + - NRI4 + - NRTS1 + - NRTS2 + - NRTS3 + - NRTS4 + - OSCCLK + - PCIERC1 + - PEWAKE + - PWM0 + - PWM1 + - PWM10G0 + - PWM10G1 + - PWM11G0 + - PWM11G1 + - PWM12G0 + - PWM12G1 + - PWM13G0 + - PWM13G1 + - PWM14G0 + - PWM14G1 + - PWM15G0 + - PWM15G1 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8G0 + - PWM8G1 + - PWM9G0 + - PWM9G1 + - QSPI1 + - QSPI2 + - RGMII1 + - RGMII2 + - RGMII3 + - RGMII4 + - RMII1 + - RMII2 + - RMII3 + - RMII4 + - RXD1 + - RXD2 + - RXD3 + - RXD4 + - SALT1 + - SALT10G0 + - SALT10G1 + - SALT11G0 + - SALT11G1 + - SALT12G0 + - SALT12G1 + - SALT13G0 + - SALT13G1 + - SALT14G0 + - SALT14G1 + - SALT15G0 + - SALT15G1 + - SALT16G0 + - SALT16G1 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9G0 + - SALT9G1 + - SD1 + - SD2 + - SD3 + - SGPM1 + - SGPM2 + - SGPS1 + - SGPS2 + - SIOONCTRL + - SIOPBI + - SIOPBO + - SIOPWREQ + - SIOPWRGD + - SIOS3 + - SIOS5 + - SIOSCI + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WP + - SPI2 + - SPI2CS1 + - SPI2CS2 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - TXD1 + - TXD2 + - TXD3 + - TXD4 + - UART10 + - UART11 + - UART12G0 + - UART12G1 + - UART13G0 + - UART13G1 + - UART6 + - UART7 + - UART8 + - UART9 + - USBA + - USBB + - VB + - VGAHS + - VGAVS + - WDTRST1 + - WDTRST2 + - WDTRST3 + - WDTRST4 + + pins: true + bias-disable: true + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +examples: + - | + syscon: scu@1e6e2000 { + compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0xf6c>; + #clock-cells = <1>; + #reset-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e6e2000 0x1000>; + + pinctrl: pinctrl { + compatible = "aspeed,ast2600-pinctrl"; + + pinctrl_pwm10g1_default: pwm10g1_default { + function = "PWM10"; + groups = "PWM10G1"; + }; + + pinctrl_gpioh0_unbiased_default: gpioh0 { + pins = "A18"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt new file mode 100644 index 000000000..81a05a09f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -0,0 +1,99 @@ +* Atmel PIO4 Controller + +The Atmel PIO4 controller is used to select the function of a pin and to +configure it. + +Required properties: +- compatible: + "atmel,sama5d2-pinctrl" + "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl" + "microchip,sama7g5-pinctrl" +- reg: base address and length of the PIO controller. +- interrupts: interrupt outputs from the controller, one for each bank. +- interrupt-controller: mark the device node as an interrupt controller. +- #interrupt-cells: should be two. +- gpio-controller: mark the device node as a gpio controller. +- #gpio-cells: should be two. + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices. + +Subnode format +Each node (or subnode) will list the pins it needs and how to configured these +pins. + + node { + pinmux = <PIN_NUMBER_PINMUX>; + GENERIC_PINCONFIG; + }; + +Required properties: +- pinmux: integer array. Each integer represents a pin number plus mux and +ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the +right representation of the pin. + +Optional properties: +- GENERIC_PINCONFIG: generic pinconfig options to use: + - bias-disable, bias-pull-down, bias-pull-up, drive-open-drain, + drive-push-pull input-schmitt-enable, input-debounce, output-low, + output-high. + - for microchip,sama7g5-pinctrl only: + - slew-rate: 0 - disabled, 1 - enabled (default) +- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for +high drive. The default value is low drive. + +Example: + +#include <sama5d2-pinfunc.h> + +... +{ + pioA: pinctrl@fc038000 { + compatible = "atmel,sama5d2-pinctrl"; + reg = <0xfc038000 0x600>; + interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>, + <68 IRQ_TYPE_LEVEL_HIGH 7>, + <69 IRQ_TYPE_LEVEL_HIGH 7>, + <70 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&pioA_clk>; + + pinctrl_i2c0_default: i2c0_default { + pinmux = <PIN_PD21__TWD0>, + <PIN_PD22__TWCK0>; + bias-disable; + }; + + pinctrl_led_gpio_default: led_gpio_default { + pinmux = <PIN_PB0>, + <PIN_PB5>; + bias-pull-up; + atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>; + }; + + pinctrl_sdmmc1_default: sdmmc1_default { + cmd_data { + pinmux = <PIN_PA28__SDMMC1_CMD>, + <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-pull-up; + }; + + ck_cd { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + }; + }; + ... + }; +}; +... diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml new file mode 100644 index 000000000..a7ede29c1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91rm9200-pinctrl.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIO3 Pinmux Controller + +maintainers: + - Manikandan Muralidharan <manikandan.m@microchip.com> + +description: + The AT91 Pinmux Controller, enables the IC to share one PAD to several + functional blocks. The sharing is done by multiplexing the PAD input/output + signals. For each PAD there are up to 8 muxing options (called periph modes). + Since different modules require different PAD settings (like pull up, keeper, + etc) the controller controls also the PAD settings parameters. + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at91rm9200-pinctrl + - atmel,at91sam9x5-pinctrl + - atmel,sama5d3-pinctrl + - microchip,sam9x60-pinctrl + - const: simple-mfd + - items: + - enum: + - microchip,sam9x7-pinctrl + - const: microchip,sam9x60-pinctrl + - const: simple-mfd + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + + atmel,mux-mask: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + Array of mask (periph per bank) to describe if a pin can be + configured in this periph mode. All the periph and bank need to + be described. + + #How to create such array: + + Each column will represent the possible peripheral of the pinctrl + Each line will represent a pio bank + + #Example: + + In at91sam9260.dtsi, + Peripheral: 2 ( A and B) + Bank: 3 (A, B and C) + + # A B + 0xffffffff 0xffc00c3b # pioA + 0xffffffff 0x7fff3ccf # pioB + 0xffffffff 0x007fffff # pioC + + For each peripheral/bank we will describe in a u32 if a pin can be + configured in it by putting 1 to the pin bit (1 << pin) + + Let's take the pioA on peripheral B whose value is 0xffc00c3b + From the datasheet Table 10-2. + Peripheral B + PA0 MCDB0 + PA1 MCCDB + PA2 + PA3 MCDB3 + PA4 MCDB2 + PA5 MCDB1 + PA6 + PA7 + PA8 + PA9 + PA10 ETX2 + PA11 ETX3 + PA12 + PA13 + PA14 + PA15 + PA16 + PA17 + PA18 + PA19 + PA20 + PA21 + PA22 ETXER + PA23 ETX2 + PA24 ETX3 + PA25 ERX2 + PA26 ERX3 + PA27 ERXCK + PA28 ECRS + PA29 ECOL + PA30 RXD4 + PA31 TXD4 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - ranges + - "#address-cells" + - "#size-cells" + - atmel,mux-mask + +patternProperties: + 'gpio@[0-9a-f]+$': + $ref: /schemas/gpio/atmel,at91rm9200-gpio.yaml + unevaluatedProperties: false + +additionalProperties: + type: object + additionalProperties: + type: object + additionalProperties: false + + properties: + atmel,pins: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + Each entry consists of 4 integers and represents the pins + mux and config setting.The format is + atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>. + Supported pin number and mux varies for different SoCs, and + are defined in <include/dt-bindings/pinctrl/at91.h>. + items: + items: + - description: + Pin bank + - description: + Pin bank index + - description: + Peripheral function + - description: + Pad configuration + +examples: + - | + #include <dt-bindings/clock/at91.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/pinctrl/at91.h> + + pinctrl@fffff400 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91rm9200-pinctrl", "simple-mfd"; + ranges = <0xfffff400 0xfffff400 0x600>; + + atmel,mux-mask = < + /* A B */ + 0xffffffff 0xffc00c3b /* pioA */ + 0xffffffff 0x7fff3ccf /* pioB */ + 0xffffffff 0x007fffff /* pioC */ + >; + + dbgu { + dbgu-0 { + atmel,pins = + <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP + AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml new file mode 100644 index 000000000..98c310a3c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/awinic,aw9523-pinctrl.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/awinic,aw9523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Awinic AW9523/AW9523B I2C GPIO Expander + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> + +description: | + The Awinic AW9523/AW9523B I2C GPIO Expander featuring 16 multi-function + I/O, 256 steps PWM mode and interrupt support. + +properties: + compatible: + const: awinic,aw9523-pinctrl + + reg: + maxItems: 1 + + '#gpio-cells': + description: | + Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: Specifies the INTN pin IRQ. + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + reset-gpios: + maxItems: 1 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. + items: + pattern: "^gpio([0-9]|1[0-5])$" + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the + specified pins. + + enum: [ gpio, pwm ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-open-drain: true + drive-push-pull: true + input-enable: true + input-disable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + # Example configuration to drive pins for a keyboard matrix + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + aw9523: gpio-expander@58 { + compatible = "awinic,aw9523-pinctrl"; + reg = <0x58>; + interrupt-parent = <&tlmm>; + interrupts = <50 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 16>; + interrupt-controller; + #interrupt-cells = <2>; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_HIGH>; + + keyboard-matrix-col-pins { + pins = "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + function = "gpio"; + input-disable; + output-low; + }; + + keyboard-matrix-row-pins { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7"; + function = "gpio"; + bias-pull-up; + drive-open-drain; + input-enable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt new file mode 100644 index 000000000..678f50970 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/axis,artpec6-pinctrl.txt @@ -0,0 +1,87 @@ +Axis ARTPEC-6 Pin Controller + +Required properties: +- compatible: "axis,artpec6-pinctrl". +- reg: Should contain the register physical address and length for the pin + controller. + +A pinctrl node should contain at least one subnode representing the pinctrl +groups available on the machine. Each subnode will list the mux function +required and what pin group it will use. Each subnode will also configure the +drive strength and bias pullup of the pin group. If either of these options is +not set, its actual value will be unspecified. + + +Required subnode-properties: +- function: Function to mux. +- groups: Name of the pin group to use for the function above. + + Available functions and groups (function: group0, group1...): + gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0, + i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0, + spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2, + uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2, + uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1, + uart5nocts + cpuclkout: cpuclkoutgrp0 + udlclkout: udlclkoutgrp0 + i2c1: i2c1grp0 + i2c2: i2c2grp0 + i2c3: i2c3grp0 + i2s0: i2s0grp0 + i2s1: i2s1grp0 + i2srefclk: i2srefclkgrp0 + spi0: spi0grp0 + spi1: spi1grp0 + pciedebug: pciedebuggrp0 + uart0: uart0grp0, uart0grp1, uart0grp2 + uart1: uart1grp0, uart1grp1 + uart2: uart2grp0, uart2grp1, uart2grp2 + uart3: uart3grp0 + uart4: uart4grp0, uart4grp1 + uart5: uart5grp0, uart5grp1, uart5nocts + nand: nandgrp0 + sdio0: sdio0grp0 + sdio1: sdio1grp0 + ethernet: ethernetgrp0 + + +Optional subnode-properties (see pinctrl-bindings.txt): +- drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3. +- bias-pull-up +- bias-disable + +Examples: +pinctrl@f801d000 { + compatible = "axis,artpec6-pinctrl"; + reg = <0xf801d000 0x400>; + + pinctrl_uart0: uart0grp { + function = "uart0"; + groups = "uart0grp0"; + drive-strength = <4>; + bias-pull-up; + }; + pinctrl_uart3: uart3grp { + function = "uart3"; + groups = "uart3grp0"; + }; +}; +uart0: uart@f8036000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8036000 0x1000>; + interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pll2div24>, <&apb_pclk>; + clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; +}; +uart3: uart@f8039000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8039000 0x1000>; + interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pll2div24>, <&apb_pclk>; + clock-names = "uart_clk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml new file mode 100644 index 000000000..542be9870 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/bitmain,bm1880-pinctrl.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/bitmain,bm1880-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Bitmain BM1880 Pin Controller + +maintainers: + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> + +properties: + compatible: + const: bitmain,bm1880-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + description: A pin configuration node. + type: object + additionalProperties: false + + properties: + pinmux: + type: object + description: Pin multiplexing parameters. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + pins: + items: + pattern: '^MIO[0-9]+$' + + groups: + items: + enum: [ + nand_grp, spi_grp, emmc_grp, sdio_grp, eth0_grp, pwm0_grp, + pwm1_grp, pwm2_grp, pwm3_grp, pwm4_grp, pwm5_grp, pwm6_grp, + pwm7_grp, pwm8_grp, pwm9_grp, pwm10_grp, pwm11_grp, pwm12_grp, + pwm13_grp, pwm14_grp, pwm15_grp, pwm16_grp, pwm17_grp, + pwm18_grp, pwm19_grp, pwm20_grp, pwm21_grp, pwm22_grp, + pwm23_grp, pwm24_grp, pwm25_grp, pwm26_grp, pwm27_grp, + pwm28_grp, pwm29_grp, pwm30_grp, pwm31_grp, pwm32_grp, + pwm33_grp, pwm34_grp, pwm35_grp, pwm36_grp, i2c0_grp, + i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, uart0_grp, uart1_grp, + uart2_grp, uart3_grp, uart4_grp, uart5_grp, uart6_grp, + uart7_grp, uart8_grp, uart9_grp, uart10_grp, uart11_grp, + uart12_grp, uart13_grp, uart14_grp, uart15_grp, gpio0_grp, + gpio1_grp, gpio2_grp, gpio3_grp, gpio4_grp, gpio5_grp, + gpio6_grp, gpio7_grp, gpio8_grp, gpio9_grp, gpio10_grp, + gpio11_grp, gpio12_grp, gpio13_grp, gpio14_grp, gpio15_grp, + gpio16_grp, gpio17_grp, gpio18_grp, gpio19_grp, gpio20_grp, + gpio21_grp, gpio22_grp, gpio23_grp, gpio24_grp, gpio25_grp, + gpio26_grp, gpio27_grp, gpio28_grp, gpio29_grp, gpio30_grp, + gpio31_grp, gpio32_grp, gpio33_grp, gpio34_grp, gpio35_grp, + gpio36_grp, gpio37_grp, gpio38_grp, gpio39_grp, gpio40_grp, + gpio41_grp, gpio42_grp, gpio43_grp, gpio44_grp, gpio45_grp, + gpio46_grp, gpio47_grp, gpio48_grp, gpio49_grp, gpio50_grp, + gpio51_grp, gpio52_grp, gpio53_grp, gpio54_grp, gpio55_grp, + gpio56_grp, gpio57_grp, gpio58_grp, gpio59_grp, gpio60_grp, + gpio61_grp, gpio62_grp, gpio63_grp, gpio64_grp, gpio65_grp, + gpio66_grp, gpio67_grp, eth1_grp, i2s0_grp, i2s0_mclkin_grp, + i2s1_grp, i2s1_mclkin_grp, spi0_grp + ] + + function: + items: + enum: [ + nand, spi, emmc, sdio, eth0, pwm0, pwm1, pwm2, pwm3, pwm4, + pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, pwm12, pwm13, + pwm14, pwm15, pwm16, pwm17, pwm18, pwm19, pwm20, pwm21, pwm22, + pwm23, pwm24, pwm25, pwm26, pwm27, pwm28, pwm29, pwm30, pwm31, + pwm32, pwm33, pwm34, pwm35, pwm36, i2c0, i2c1, i2c2, i2c3, + i2c4, uart0, uart1, uart2, uart3, uart4, uart5, uart6, uart7, + uart8, uart9, uart10, uart11, uart12, uart13, uart14, uart15, + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, + gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, gpio16, + gpio17, gpio18, gpio19, gpio20, gpio21, gpio22, gpio23, + gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, + gpio31, gpio32, gpio33, gpio34, gpio35, gpio36, gpio37, + gpio38, gpio39, gpio40, gpio41, gpio42, gpio43, gpio44, + gpio45, gpio46, gpio47, gpio48, gpio49, gpio50, gpio51, + gpio52, gpio53, gpio54, gpio55, gpio56, gpio57, gpio58, + gpio59, gpio60, gpio61, gpio62, gpio63, gpio64, gpio65, + gpio66, gpio67, eth1, i2s0, i2s0_mclkin, i2s1, i2s1_mclkin, + spi0 + ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + + slew-rate: + description: > + Sets slew rate. Valid values: 0 = Slow, 1 = Fast. + enum: [0, 1] + + drive-strength: + enum: [4, 8, 12, 16, 20, 24, 28, 32] + + oneOf: + - required: + - pins + - required: + - groups + + required: + - function + +required: + - compatible + - reg + +examples: + - | + pinctrl@400 { + compatible = "bitmain,bm1880-pinctrl"; + reg = <0x400 0x120>; + + uart0-default { + pinmux { + groups = "uart0_grp"; + function = "uart0"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml new file mode 100644 index 000000000..90c275295 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm11351-pinctrl.yaml @@ -0,0 +1,259 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM281xx pin controller + +maintainers: + - Florian Fainelli <florian.fainelli@broadcom.com> + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: brcm,bcm11351-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '-grp[0-9]$': + type: object + unevaluatedProperties: false + + properties: + pins: + description: + Specifies the name(s) of one or more pins to be configured by + this node. + items: + enum: [ adcsync, bat_rm, bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, + classgpwr, clk_cx8, clkout_0, clkout_1, clkout_2, + clkout_3, clkreq_in_0, clkreq_in_1, cws_sys_req1, + cws_sys_req2, cws_sys_req3, digmic1_clk, digmic1_dq, + digmic2_clk, digmic2_dq, gpen13, gpen14, gpen15, gpio00, + gpio01, gpio02, gpio03, gpio04, gpio05, gpio06, gpio07, + gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, gpio14, + gps_pablank, gps_tmark, hdmi_scl, hdmi_sda, ic_dm, ic_dp, + kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3, + kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3, + lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5, + lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3, + lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, lcd_oe, + lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, lcd_r_3, lcd_r_4, + lcd_r_5, lcd_r_6, lcd_r_7, lcd_vsync, mdmgpio0, mdmgpio1, + mdmgpio2, mdmgpio3, mdmgpio4, mdmgpio5, mdmgpio6, + mdmgpio7, mdmgpio8, mphi_data_0, mphi_data_1, mphi_data_2, + mphi_data_3, mphi_data_4, mphi_data_5, mphi_data_6, + mphi_data_7, mphi_data_8, mphi_data_9, mphi_data_10, + mphi_data_11, mphi_data_12, mphi_data_13, mphi_data_14, + mphi_data_15, mphi_ha0, mphi_hat0, mphi_hat1, mphi_hce0_n, + mphi_hce1_n, mphi_hrd_n, mphi_hwr_n, mphi_run0, mphi_run1, + mtx_scan_clk, mtx_scan_data, nand_ad_0, nand_ad_1, + nand_ad_2, nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6, + nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, nand_cle, + nand_oen, nand_rdy_0, nand_rdy_1, nand_wen, nand_wp, pc1, + pc2, pmu_int, pmu_scl, pmu_sda, rfst2g_mtsloten3g, + rgmii_0_rx_ctl, rgmii_0_rxc, rgmii_0_rxd_0, rgmii_0_rxd_1, + rgmii_0_rxd_2, rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc, + rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2, + rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, rgmii_1_rxd_0, + rgmii_1_rxd_1, rgmii_1_rxd_2, rgmii_1_rxd_3, + rgmii_1_tx_ctl, rgmii_1_txc, rgmii_1_txd_0, rgmii_1_txd_1, + rgmii_1_txd_2, rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1, + rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1, + rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2, + sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1, + sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd, + sdio4_data_0, sdio4_data_1, sdio4_data_2, sdio4_data_3, + sim_clk, sim_data, sim_det, sim_resetn, sim2_clk, + sim2_data, sim2_det, sim2_resetn, sri_c, sri_d, sri_e, + ssp_extclk, ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, + ssp2_clk, ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3, + ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, ssp3_clk, + ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, ssp4_fs, ssp4_rxd, + ssp4_txd, ssp5_clk, ssp5_fs, ssp5_rxd, ssp5_txd, ssp6_clk, + ssp6_fs, ssp6_rxd, ssp6_txd, stat_1, stat_2, sysclken, + traceclk, tracedt00, tracedt01, tracedt02, tracedt03, + tracedt04, tracedt05, tracedt06, tracedt07, tracedt08 + tracedt09, tracedt10, tracedt11, tracedt12, tracedt13 + tracedt14, tracedt15, txdata3g0, txpwrind, uartb1_ucts, + uartb1_urts, uartb1_urxd, uartb1_utxd, uartb2_urxd, + uartb2_utxd, uartb3_ucts, uartb3_urts, uartb3_urxd, + uartb3_utxd, uartb4_ucts, uartb4_urts, uartb4_urxd, + uartb4_utxd, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl, + vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ] + + function: + description: + Specifies the pin mux selection. + enum: [ alt1, alt2, alt3, alt4 ] + + slew-rate: + description: | + Meaning depends on configured pin mux: + *_scl or *_sda: + 0: Standard (100 kbps) & Fast (400 kbps) mode + 1: Highspeed (3.4 Mbps) mode + ic_dm or ic_dp: + 0: normal slew rate + 1: fast slew rate + Otherwise: + 0: fast slew rate + 1: normal slew rate + + bias-disable: true + input-disable: true + input-enable: true + + required: + - pins + + allOf: + - $ref: pincfg-node.yaml# + + # Optional properties for standard pins + - if: + properties: + pins: + contains: + enum: [ adcsync, bat_rm, classgpwr, clk_cx8, clkout_0, + clkout_1, clkout_2, clkout_3, clkreq_in_0, + clkreq_in_1, cws_sys_req1, cws_sys_req2, + cws_sys_req3, digmic1_clk, digmic1_dq, digmic2_clk, + digmic2_dq, gpen13, gpen14, gpen15, gpio00, gpio01, + gpio02, gpio03, gpio04, gpio05, gpio06, gpio07, + gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, + gpio14, gps_pablank, gps_tmark, ic_dm, ic_dp, + kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3, + kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3, + lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5, + lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3, + lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, + lcd_oe, lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, + lcd_r_3, lcd_r_4, lcd_r_5, lcd_r_6, lcd_r_7, + lcd_vsync, mdmgpio0, mdmgpio1, mdmgpio2, mdmgpio3, + mdmgpio4, mdmgpio5, mdmgpio6, mdmgpio7, mdmgpio8, + mphi_data_0, mphi_data_1, mphi_data_2, mphi_data_3, + mphi_data_4, mphi_data_5, mphi_data_6, mphi_data_7, + mphi_data_8, mphi_data_9, mphi_data_10, + mphi_data_11, mphi_data_12, mphi_data_13, + mphi_data_14, mphi_data_15, mphi_ha0, mphi_hat0, + mphi_hat1, mphi_hce0_n, mphi_hce1_n, mphi_hrd_n, + mphi_hwr_n, mphi_run0, mphi_run1, mtx_scan_clk, + mtx_scan_data, nand_ad_0, nand_ad_1, nand_ad_2, + nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6, + nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, + nand_cle, nand_oen, nand_rdy_0, nand_rdy_1, + nand_wen, nand_wp, pc1, pc2, pmu_int, + rfst2g_mtsloten3g, rgmii_0_rx_ctl, rgmii_0_rxc, + rgmii_0_rxd_0, rgmii_0_rxd_1, rgmii_0_rxd_2, + rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc, + rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2, + rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, + rgmii_1_rxd_0, rgmii_1_rxd_1, rgmii_1_rxd_2, + rgmii_1_rxd_3, rgmii_1_tx_ctl, rgmii_1_txc, + rgmii_1_txd_0, rgmii_1_txd_1, rgmii_1_txd_2, + rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1, + rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1, + rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2, + sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1, + sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd, + sdio4_data_0, sdio4_data_1, sdio4_data_2, + sdio4_data_3, sim_clk, sim_data, sim_det, + sim_resetn, sim2_clk, sim2_data, sim2_det, + sim2_resetn, sri_c, sri_d, sri_e, ssp_extclk, + ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, ssp2_clk, + ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3, + ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, + ssp3_clk, ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, + ssp4_fs, ssp4_rxd, ssp4_txd, ssp5_clk, ssp5_fs, + ssp5_rxd, ssp5_txd, ssp6_clk, ssp6_fs, ssp6_rxd, + ssp6_txd, stat_1, stat_2, sysclken, traceclk, + tracedt00, tracedt01, tracedt02, tracedt03, + tracedt04, tracedt05, tracedt06, tracedt07, + tracedt08, tracedt09, tracedt10, tracedt11, + tracedt12, tracedt13, tracedt14, tracedt15, + txdata3g0, txpwrind, uartb1_ucts, uartb1_urts, + uartb1_urxd, uartb1_utxd, uartb2_urxd, uartb2_utxd, + uartb3_ucts, uartb3_urts, uartb3_urxd, uartb3_utxd, + uartb4_ucts, uartb4_urts, uartb4_urxd, uartb4_utxd ] + then: + properties: + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + input-schmitt-enable: true + input-schmitt-disable: true + + # Optional properties for I2C pins + - if: + properties: + pins: + contains: + enum: [ bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, pmu_scl, + pmu_sda, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl, + vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ] + then: + properties: + bias-pull-up: + description: + There are 3 pull-up resistors (1.2k, 1.8k, 2.7k) available + in parallel for I2C pins. + enum: [ 568, 720, 831, 1080, 1200, 1800, 2700 ] + + bias-disable: true + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@35004800 { + compatible = "brcm,bcm11351-pinctrl"; + reg = <0x35004800 0x430>; + + dev-a-active-pins { + /* group node defining 1 standard pin */ + std-grp0 { + pins = "gpio00"; + function = "alt1"; + input-schmitt-enable; + bias-disable; + slew-rate = <1>; + drive-strength = <4>; + }; + + /* group node defining 2 I2C pins */ + i2c-grp0 { + pins = "bsc1_scl", "bsc1_sda"; + function = "alt2"; + bias-pull-up = <720>; + input-enable; + }; + + /* group node defining 2 HDMI pins */ + hdmi-grp0 { + pins = "hdmi_scl", "hdmi_sda"; + function = "alt3"; + slew-rate = <1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml new file mode 100644 index 000000000..a2e609b06 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm21664-pinctrl.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm21664-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM21664 pin controller + +maintainers: + - Florian Fainelli <florian.fainelli@broadcom.com> + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: brcm,bcm21664-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '-grp[0-9]$': + type: object + + properties: + pins: + description: + Specifies the name(s) of one or more pins to be configured by + this node. + items: + enum: [ adcsyn, batrm, bsc1clk, bsc1dat, camcs0, camcs1, clk32k, + clk_cx8, dclk1, dclk4, dclkreq1, dclkreq4, dmic0clk, + dmic0dq, dsi0te, gpio00, gpio01, gpio02, gpio03, gpio04, + gpio05, gpio06, gpio07, gpio08, gpio09, gpio10, gpio11, + gpio12, gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, + gpio19, gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio32, gpio33, gpio34, gpio93, + gpio94, gps_calreq, gps_hostreq, gps_pablank, gps_tmark, + icusbdm, icusbdp, lcdcs0, lcdres, lcdscl, lcdsda, lcdte, + mdmgpio00, mdmgpio01, mdmgpio02, mdmgpio03, mdmgpio04, + mdmgpio05, mdmgpio06, mdmgpio07, mdmgpio08, mmc0ck, + mmc0cmd, mmc0dat0, mmc0dat1, mmc0dat2, mmc0dat3, mmc0dat4, + mmc0dat5, mmc0dat6, mmc0dat7, mmc0rst, mmc1ck, mmc1cmd, + mmc1dat0, mmc1dat1, mmc1dat2, mmc1dat3, mmc1dat4, + mmc1dat5, mmc1dat6, mmc1dat7, mmc1rst, pc1, pc2, pmbscclk, + pmbscdat, pmuint, resetn, rfst2g_mtsloten3g, + rtxdata2g_txdata3g1, rtxen2g_txdata3g2, rxdata3g0, + rxdata3g1, rxdata3g2, sdck, sdcmd, sddat0, sddat1, sddat2, + sddat3, simclk, simdat, simdet, simrst, spi0clk, spi0fss, + spi0rxd, spi0txd, sri_c, sri_d, sri_e, sspck, sspdi, + sspdo, sspsyn, stat1, stat2, swclktck, swdiotms, sysclken, + tdi, tdo, testmode, traceclk, tracedt00, tracedt01, + tracedt02, tracedt03, tracedt04, tracedt05, tracedt06, + tracedt07, tracedt08, tracedt09, tracedt10, tracedt11, + tracedt12, tracedt13, tracedt14, tracedt15, trstb, + txdata3g0, ubctsn, ubrtsn, ubrx, ubtx ] + + function: + description: + Specifies the pin mux selection. + enum: [ alt1, alt2, alt3, alt4, alt5, alt6 ] + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + slew-rate: + description: | + Meaning depends on configured pin mux: + bsc*clk/pmbscclk or bsc*dat/pmbscdat or gpio16/gpio17: + 0: Standard (100 kbps) & Fast (400 kbps) mode + 1: Highspeed (3.4 Mbps) mode + Otherwise: + 0: fast slew rate + 1: normal slew rate + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + input-enable: true + input-disable: true + + input-schmitt-enable: true + input-schmitt-disable: true + + required: + - pins + + additionalProperties: false + + allOf: + - $ref: pincfg-node.yaml# + # Limitations for I2C pins + - if: + properties: + pins: + contains: + enum: [ bsc1clk, bsc1dat, gpio16, gpio17, pmbscclk, + pmbscdat ] + then: + properties: + drive-strength: false + bias-pull-down: false + input-schmitt-enable: false + input-schmitt-disable: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@35004800 { + compatible = "brcm,bcm21664-pinctrl"; + reg = <0x35004800 0x7f0>; + + dev-a-active-pins { + /* group node defining 1 standard pin */ + std-grp0 { + pins = "gpio00"; + function = "alt1"; + input-schmitt-enable; + bias-disable; + slew-rate = <1>; + drive-strength = <4>; + }; + + /* group node defining 2 I2C pins */ + i2c-grp0 { + pins = "bsc1clk", "bsc1dat"; + function = "alt2"; + bias-pull-up; + input-enable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml new file mode 100644 index 000000000..ae6c13a74 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2712c0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB family pin controller + +maintainers: + - Ivan T. Ivanov <iivanov@suse.de> + - A. della Porta <andrea.porta@suse.com> + +description: > + Broadcom's STB family of memory-mapped pin controllers. + + This includes the pin controllers inside the BCM2712 SoC which + are instances of the STB family and has two silicon variants, + C0 and D0, which differs slightly in terms of registers layout. + + The -aon- (Always On) variant is the same IP block but differs + in the number of pins that are associated and the pinmux functions + for each of those pins. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - brcm,bcm2712c0-pinctrl + - brcm,bcm2712c0-aon-pinctrl + - brcm,bcm2712d0-pinctrl + - brcm,bcm2712d0-aon-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-state$': + oneOf: + - $ref: '#/$defs/brcmstb-pinctrl-state' + - patternProperties: + '-pins$': + $ref: '#/$defs/brcmstb-pinctrl-state' + additionalProperties: false + +$defs: + brcmstb-pinctrl-state: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: > + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode (either this or "groups" must be specified). + items: + pattern: '^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$' + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8, + aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm, + arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2, + bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii, + ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c, + hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out, + ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0, + sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e, + sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0, + te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0, + vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1, + vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3, + vc_uart4 ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + required: + - pins + + if: + properties: + pins: + not: + contains: + pattern: "^emmc_(clk|cmd|dat[0-7]|ds)$" + then: + required: + - function + else: + properties: + function: false + + additionalProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@7d504100 { + compatible = "brcm,bcm2712c0-pinctrl"; + reg = <0x7d504100 0x30>; + + bt-shutdown-default-state { + function = "gpio"; + pins = "gpio29"; + }; + + uarta-default-state { + rts-tx-pins { + function = "uart0"; + pins = "gpio24", "gpio26"; + bias-disable; + }; + + cts-rx-pins { + function = "uart0"; + pins = "gpio25", "gpio27"; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml new file mode 100644 index 000000000..6514f347f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2835-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 GPIO (and pinmux) controller + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +description: > + The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt + controller, and pinmux/control device. + +properties: + compatible: + enum: + - brcm,bcm2835-gpio + - brcm,bcm2711-gpio + - brcm,bcm7211-gpio + + reg: + maxItems: 1 + + '#gpio-cells': + const: 2 + + gpio-controller: true + gpio-ranges: true + gpio-line-names: true + + interrupts: + description: > + Interrupt outputs: one per bank, then the combined “all banks” line. + BCM7211 may specify up to four per-bank wake-up lines and one combined + wake-up interrupt. + minItems: 4 + maxItems: 10 + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + +additionalProperties: + oneOf: + - type: object + additionalProperties: false + + patternProperties: + '^pins?-': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + pins: true + function: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + output-high: true + output-low: true + + required: + - pins + - function + + - type: object + additionalProperties: false + deprecated: true + + properties: + brcm,pins: + description: + GPIO pin numbers for legacy configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + brcm,function: + description: + Legacy mux function for the pins (0=input, 1=output, 2–7=alt functions). + $ref: /schemas/types.yaml#/definitions/uint32-array + maximum: 7 + + brcm,pull: + description: > + Legacy pull setting for the pins (0=none, 1=pull-down, 2=pull-up). + $ref: /schemas/types.yaml#/definitions/uint32-array + maximum: 2 + + required: + - brcm,pins + +allOf: + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm2835-gpio + - brcm,bcm2711-gpio + then: + properties: + interrupts: + maxItems: 5 + +examples: + - | + gpio@2200000 { + compatible = "brcm,bcm2835-gpio"; + reg = <0x2200000 0xb4>; + interrupts = <2 17>, <2 19>, <2 18>, <2 20>, <2 21>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml new file mode 100644 index 000000000..8a9fb9b43 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM4908 pin controller + +maintainers: + - Rafał Miłecki <rafal@milecki.pl> + +description: + Binding for pin controller present on BCM4908 family SoCs. + +properties: + compatible: + const: brcm,bcm4908-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8, + led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16, + led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24, + led_25, led_26, led_27, led_28, led_29, led_30, led_31, + hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr, + usb1_pwr ] + + groups: + minItems: 1 + maxItems: 2 + items: + enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a, + led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a, + led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b, + led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b, + led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a, + led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a, + led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a, + led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a, + led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a, + led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp, + nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp, + usb1_pwr_grp ] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@ff800560 { + compatible = "brcm,bcm4908-pinctrl"; + reg = <0xff800560 0x10>; + + led_0-a-pins { + function = "led_0"; + groups = "led_0_grp_a"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml new file mode 100644 index 000000000..62890a0ae --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6318-pinctrl.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6318-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6318 pin controller + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: + Bindings for Broadcom's BCM6318 memory-mapped pin controller. + +properties: + compatible: + const: brcm,bcm6318-pinctrl + + reg: + maxItems: 2 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + enum: [ ephy0_spd_led, ephy1_spd_led, ephy2_spd_led, ephy3_spd_led, + ephy0_act_led, ephy1_act_led, ephy2_act_led, ephy3_act_led, + serial_led_data, serial_led_clk, inet_act_led, inet_fail_led, + dsl_led, post_fail_led, wlan_wps_led, usb_pwron, + usb_device_led, usb_active ] + + pins: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio40 ] + + patternProperties: + '-pins$': + $ref: '#/patternProperties/-pins$' + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@18 { + compatible = "brcm,bcm6318-pinctrl"; + reg = <0x18 0x10>, <0x54 0x18>; + + pinctrl_ephy0_spd_led: ephy0_spd_led-pins { + function = "ephy0_spd_led"; + pins = "gpio0"; + }; + + pinctrl_ephy1_spd_led: ephy1_spd_led-pins { + function = "ephy1_spd_led"; + pins = "gpio1"; + }; + + pinctrl_ephy2_spd_led: ephy2_spd_led-pins { + function = "ephy2_spd_led"; + pins = "gpio2"; + }; + + pinctrl_ephy3_spd_led: ephy3_spd_led-pins { + function = "ephy3_spd_led"; + pins = "gpio3"; + }; + + pinctrl_ephy0_act_led: ephy0_act_led-pins { + function = "ephy0_act_led"; + pins = "gpio4"; + }; + + pinctrl_ephy1_act_led: ephy1_act_led-pins { + function = "ephy1_act_led"; + pins = "gpio5"; + }; + + pinctrl_ephy2_act_led: ephy2_act_led-pins { + function = "ephy2_act_led"; + pins = "gpio6"; + }; + + pinctrl_ephy3_act_led: ephy3_act_led-pins { + function = "ephy3_act_led"; + pins = "gpio7"; + }; + + pinctrl_serial_led: serial_led-pins { + pinctrl_serial_led_data: serial_led_data-pins { + function = "serial_led_data"; + pins = "gpio6"; + }; + + pinctrl_serial_led_clk: serial_led_clk-pins { + function = "serial_led_clk"; + pins = "gpio7"; + }; + }; + + pinctrl_inet_act_led: inet_act_led-pins { + function = "inet_act_led"; + pins = "gpio8"; + }; + + pinctrl_inet_fail_led: inet_fail_led-pins { + function = "inet_fail_led"; + pins = "gpio9"; + }; + + pinctrl_dsl_led: dsl_led-pins { + function = "dsl_led"; + pins = "gpio10"; + }; + + pinctrl_post_fail_led: post_fail_led-pins { + function = "post_fail_led"; + pins = "gpio11"; + }; + + pinctrl_wlan_wps_led: wlan_wps_led-pins { + function = "wlan_wps_led"; + pins = "gpio12"; + }; + + pinctrl_usb_pwron: usb_pwron-pins { + function = "usb_pwron"; + pins = "gpio13"; + }; + + pinctrl_usb_device_led: usb_device_led-pins { + function = "usb_device_led"; + pins = "gpio13"; + }; + + pinctrl_usb_active: usb_active-pins { + function = "usb_active"; + pins = "gpio40"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml new file mode 100644 index 000000000..7cc0e1650 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM63268 pin controller + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: + Bindings for Broadcom's BCM63268 memory-mapped pin controller. + +properties: + compatible: + const: brcm,bcm63268-pinctrl + + reg: + maxItems: 3 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + unevaluatedProperties: false + + properties: + function: + enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5, + hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi, + vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data, + nand, gpio35_alt, dectpd, vdsl_phy_override_0, + vdsl_phy_override_1, vdsl_phy_override_2, + vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ] + + pins: + enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19, + gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35, + dectpd_grp, vdsl_phy_override_0_grp, + vdsl_phy_override_1_grp, vdsl_phy_override_2_grp, + vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ] + + patternProperties: + '-pins$': + $ref: '#/patternProperties/-pins$' + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@10 { + compatible = "brcm,bcm63268-pinctrl"; + reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>; + + pinctrl_serial_led: serial_led-pins { + pinctrl_serial_led_clk: serial_led_clk-pins { + function = "serial_led_clk"; + pins = "gpio0"; + }; + + pinctrl_serial_led_data: serial_led_data-pins { + function = "serial_led_data"; + pins = "gpio1"; + }; + }; + + pinctrl_hsspi_cs4: hsspi_cs4-pins { + function = "hsspi_cs4"; + pins = "gpio16"; + }; + + pinctrl_hsspi_cs5: hsspi_cs5-pins { + function = "hsspi_cs5"; + pins = "gpio17"; + }; + + pinctrl_hsspi_cs6: hsspi_cs6-pins { + function = "hsspi_cs6"; + pins = "gpio8"; + }; + + pinctrl_hsspi_cs7: hsspi_cs7-pins { + function = "hsspi_cs7"; + pins = "gpio9"; + }; + + pinctrl_adsl_spi: adsl_spi-pins { + pinctrl_adsl_spi_miso: adsl_spi_miso-pins { + function = "adsl_spi_miso"; + pins = "gpio18"; + }; + + pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins { + function = "adsl_spi_mosi"; + pins = "gpio19"; + }; + }; + + pinctrl_vreq_clk: vreq_clk-pins { + function = "vreq_clk"; + pins = "gpio22"; + }; + + pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins { + function = "pcie_clkreq_b"; + pins = "gpio23"; + }; + + pinctrl_robosw_led_clk: robosw_led_clk-pins { + function = "robosw_led_clk"; + pins = "gpio30"; + }; + + pinctrl_robosw_led_data: robosw_led_data-pins { + function = "robosw_led_data"; + pins = "gpio31"; + }; + + pinctrl_nand: nand-pins { + function = "nand"; + pins = "nand_grp"; + }; + + pinctrl_gpio35_alt: gpio35_alt-pins { + function = "gpio35_alt"; + pins = "gpio35"; + }; + + pinctrl_dectpd: dectpd-pins { + function = "dectpd"; + pins = "dectpd_grp"; + }; + + pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins { + function = "vdsl_phy_override_0"; + pins = "vdsl_phy_override_0_grp"; + }; + + pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins { + function = "vdsl_phy_override_1"; + pins = "vdsl_phy_override_1_grp"; + }; + + pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins { + function = "vdsl_phy_override_2"; + pins = "vdsl_phy_override_2_grp"; + }; + + pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins { + function = "vdsl_phy_override_3"; + pins = "vdsl_phy_override_3_grp"; + }; + + pinctrl_dsl_gpio8: dsl_gpio8-pins { + function = "dsl_gpio8"; + pins = "dsl_gpio8"; + }; + + pinctrl_dsl_gpio9: dsl_gpio9-pins { + function = "dsl_gpio9"; + pins = "dsl_gpio9"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml new file mode 100644 index 000000000..f57bb34c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6328-pinctrl.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6328-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6328 pin controller + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: + Bindings for Broadcom's BCM6328 memory-mapped pin controller. + +properties: + compatible: + const: brcm,bcm6328-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + unevaluatedProperties: false + + properties: + function: + enum: [ serial_led_data, serial_led_clk, inet_act_led, pcie_clkreq, + led, ephy0_act_led, ephy1_act_led, ephy2_act_led, + ephy3_act_led, hsspi_cs1, usb_device_port, usb_host_port ] + + pins: + enum: [ gpio6, gpio7, gpio11, gpio16, gpio17, gpio18, gpio19, + gpio20, gpio25, gpio26, gpio27, gpio28, hsspi_cs1, + usb_port1 ] + + patternProperties: + '-pins$': + $ref: '#/patternProperties/-pins$' + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@18 { + compatible = "brcm,bcm6328-pinctrl"; + reg = <0x18 0x10>; + + pinctrl_serial_led: serial_led-pins { + pinctrl_serial_led_data: serial_led_data-pins { + function = "serial_led_data"; + pins = "gpio6"; + }; + + pinctrl_serial_led_clk: serial_led_clk-pins { + function = "serial_led_clk"; + pins = "gpio7"; + }; + }; + + pinctrl_inet_act_led: inet_act_led-pins { + function = "inet_act_led"; + pins = "gpio11"; + }; + + pinctrl_pcie_clkreq: pcie_clkreq-pins { + function = "pcie_clkreq"; + pins = "gpio16"; + }; + + pinctrl_ephy0_spd_led: ephy0_spd_led-pins { + function = "led"; + pins = "gpio17"; + }; + + pinctrl_ephy1_spd_led: ephy1_spd_led-pins { + function = "led"; + pins = "gpio18"; + }; + + pinctrl_ephy2_spd_led: ephy2_spd_led-pins { + function = "led"; + pins = "gpio19"; + }; + + pinctrl_ephy3_spd_led: ephy3_spd_led-pins { + function = "led"; + pins = "gpio20"; + }; + + pinctrl_ephy0_act_led: ephy0_act_led-pins { + function = "ephy0_act_led"; + pins = "gpio25"; + }; + + pinctrl_ephy1_act_led: ephy1_act_led-pins { + function = "ephy1_act_led"; + pins = "gpio26"; + }; + + pinctrl_ephy2_act_led: ephy2_act_led-pins { + function = "ephy2_act_led"; + pins = "gpio27"; + }; + + pinctrl_ephy3_act_led: ephy3_act_led-pins { + function = "ephy3_act_led"; + pins = "gpio28"; + }; + + pinctrl_hsspi_cs1: hsspi_cs1-pins { + function = "hsspi_cs1"; + pins = "hsspi_cs1"; + }; + + pinctrl_usb_port1_device: usb_port1_device-pins { + function = "usb_device_port"; + pins = "usb_port1"; + }; + + pinctrl_usb_port1_host: usb_port1_host-pins { + function = "usb_host_port"; + pins = "usb_port1"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml new file mode 100644 index 000000000..ce6fc5380 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6358-pinctrl.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6358-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6358 pin controller + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: + Bindings for Broadcom's BCM6358 memory-mapped pin controller. + +properties: + compatible: + const: brcm,bcm6358-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + unevaluatedProperties: false + + properties: + function: + enum: [ ebi_cs, uart1, serial_led, legacy_led, led, spi_cs, utopia, + pwm_syn_clk, sys_irq ] + + groups: + enum: [ ebi_cs_grp, uart1_grp, serial_led_grp, legacy_led_grp, + led_grp, spi_cs_grp, utopia_grp, pwm_syn_clk_grp, sys_irq_grp ] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@18 { + compatible = "brcm,bcm6358-pinctrl"; + reg = <0x18 0x4>; + + pinctrl_ebi_cs: ebi_cs-pins { + function = "ebi_cs"; + groups = "ebi_cs_grp"; + }; + + pinctrl_uart1: uart1-pins { + function = "uart1"; + groups = "uart1_grp"; + }; + + pinctrl_serial_led: serial_led-pins { + function = "serial_led"; + groups = "serial_led_grp"; + }; + + pinctrl_legacy_led: legacy_led-pins { + function = "legacy_led"; + groups = "legacy_led_grp"; + }; + + pinctrl_led: led-pins { + function = "led"; + groups = "led_grp"; + }; + + pinctrl_spi_cs_23: spi_cs-pins { + function = "spi_cs"; + groups = "spi_cs_grp"; + }; + + pinctrl_utopia: utopia-pins { + function = "utopia"; + groups = "utopia_grp"; + }; + + pinctrl_pwm_syn_clk: pwm_syn_clk-pins { + function = "pwm_syn_clk"; + groups = "pwm_syn_clk_grp"; + }; + + pinctrl_sys_irq: sys_irq-pins { + function = "sys_irq"; + groups = "sys_irq_grp"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml new file mode 100644 index 000000000..5f7ed7d3d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6362-pinctrl.yaml @@ -0,0 +1,214 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6362-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6362 pin controller + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: + Bindings for Broadcom's BCM6362 memory-mapped pin controller. + +properties: + compatible: + const: brcm,bcm6362-pinctrl + + reg: + maxItems: 2 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + unevaluatedProperties: false + + properties: + function: + enum: [ usb_device_led, sys_irq, serial_led_clk, serial_led_data, + robosw_led_data, robosw_led_clk, robosw_led0, robosw_led1, + inet_led, spi_cs2, spi_cs3, ntr_pulse, uart1_scts, + uart1_srts, uart1_sdin, uart1_sdout, adsl_spi_miso, + adsl_spi_mosi, adsl_spi_clk, adsl_spi_cs, ephy0_led, + ephy1_led, ephy2_led, ephy3_led, ext_irq0, ext_irq1, + ext_irq2, ext_irq3, nand ] + + pins: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, nand_grp ] + + patternProperties: + '-pins$': + $ref: '#/patternProperties/-pins$' + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@18 { + compatible = "brcm,bcm6362-pinctrl"; + reg = <0x18 0x10>, <0x38 0x4>; + + pinctrl_usb_device_led: usb_device_led-pins { + function = "usb_device_led"; + pins = "gpio0"; + }; + + pinctrl_sys_irq: sys_irq-pins { + function = "sys_irq"; + pins = "gpio1"; + }; + + pinctrl_serial_led: serial_led-pins { + pinctrl_serial_led_clk: serial_led_clk-pins { + function = "serial_led_clk"; + pins = "gpio2"; + }; + + pinctrl_serial_led_data: serial_led_data-pins { + function = "serial_led_data"; + pins = "gpio3"; + }; + }; + + pinctrl_robosw_led_data: robosw_led_data-pins { + function = "robosw_led_data"; + pins = "gpio4"; + }; + + pinctrl_robosw_led_clk: robosw_led_clk-pins { + function = "robosw_led_clk"; + pins = "gpio5"; + }; + + pinctrl_robosw_led0: robosw_led0-pins { + function = "robosw_led0"; + pins = "gpio6"; + }; + + pinctrl_robosw_led1: robosw_led1-pins { + function = "robosw_led1"; + pins = "gpio7"; + }; + + pinctrl_inet_led: inet_led-pins { + function = "inet_led"; + pins = "gpio8"; + }; + + pinctrl_spi_cs2: spi_cs2-pins { + function = "spi_cs2"; + pins = "gpio9"; + }; + + pinctrl_spi_cs3: spi_cs3-pins { + function = "spi_cs3"; + pins = "gpio10"; + }; + + pinctrl_ntr_pulse: ntr_pulse-pins { + function = "ntr_pulse"; + pins = "gpio11"; + }; + + pinctrl_uart1_scts: uart1_scts-pins { + function = "uart1_scts"; + pins = "gpio12"; + }; + + pinctrl_uart1_srts: uart1_srts-pins { + function = "uart1_srts"; + pins = "gpio13"; + }; + + pinctrl_uart1: uart1-pins { + pinctrl_uart1_sdin: uart1_sdin-pins { + function = "uart1_sdin"; + pins = "gpio14"; + }; + + pinctrl_uart1_sdout: uart1_sdout-pins { + function = "uart1_sdout"; + pins = "gpio15"; + }; + }; + + pinctrl_adsl_spi: adsl_spi-pins { + pinctrl_adsl_spi_miso: adsl_spi_miso-pins { + function = "adsl_spi_miso"; + pins = "gpio16"; + }; + + pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins { + function = "adsl_spi_mosi"; + pins = "gpio17"; + }; + + pinctrl_adsl_spi_clk: adsl_spi_clk-pins { + function = "adsl_spi_clk"; + pins = "gpio18"; + }; + + pinctrl_adsl_spi_cs: adsl_spi_cs-pins { + function = "adsl_spi_cs"; + pins = "gpio19"; + }; + }; + + pinctrl_ephy0_led: ephy0_led-pins { + function = "ephy0_led"; + pins = "gpio20"; + }; + + pinctrl_ephy1_led: ephy1_led-pins { + function = "ephy1_led"; + pins = "gpio21"; + }; + + pinctrl_ephy2_led: ephy2_led-pins { + function = "ephy2_led"; + pins = "gpio22"; + }; + + pinctrl_ephy3_led: ephy3_led-pins { + function = "ephy3_led"; + pins = "gpio23"; + }; + + pinctrl_ext_irq0: ext_irq0-pins { + function = "ext_irq0"; + pins = "gpio24"; + }; + + pinctrl_ext_irq1: ext_irq1-pins { + function = "ext_irq1"; + pins = "gpio25"; + }; + + pinctrl_ext_irq2: ext_irq2-pins { + function = "ext_irq2"; + pins = "gpio26"; + }; + + pinctrl_ext_irq3: ext_irq3-pins { + function = "ext_irq3"; + pins = "gpio27"; + }; + + pinctrl_nand: nand-pins { + function = "nand"; + pins = "nand_grp"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml new file mode 100644 index 000000000..d549e9455 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml @@ -0,0 +1,225 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm6368-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM6368 pin controller + +maintainers: + - Álvaro Fernández Rojas <noltari@gmail.com> + - Jonas Gorski <jonas.gorski@gmail.com> + +description: + Bindings for Broadcom's BCM6368 memory-mapped pin controller. + +properties: + compatible: + const: brcm,bcm6368-pinctrl + + reg: + maxItems: 2 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + unevaluatedProperties: false + + properties: + function: + enum: [ analog_afe_0, analog_afe_1, sys_irq, serial_led_data, + serial_led_clk, inet_led, ephy0_led, ephy1_led, ephy2_led, + ephy3_led, robosw_led_data, robosw_led_clk, robosw_led0, + robosw_led1, usb_device_led, pci_req1, pci_gnt1, pci_intb, + pci_req0, pci_gnt0, pcmcia_cd1, pcmcia_cd2, pcmcia_vs1, + pcmcia_vs2, ebi_cs2, ebi_cs3, spi_cs2, spi_cs3, spi_cs4, + spi_cs5, uart1 ] + + pins: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio16, gpio17, gpio18, gpio19, gpio20, gpio22, gpio23, + gpio24, gpio25, gpio26, gpio27, gpio28, gpio29, gpio30, + gpio31, uart1_grp ] + + patternProperties: + '-pins$': + $ref: '#/patternProperties/-pins$' + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@18 { + compatible = "brcm,bcm6368-pinctrl"; + reg = <0x18 0x4>, <0x38 0x4>; + + pinctrl_analog_afe_0: analog_afe_0-pins { + function = "analog_afe_0"; + pins = "gpio0"; + }; + + pinctrl_analog_afe_1: analog_afe_1-pins { + function = "analog_afe_1"; + pins = "gpio1"; + }; + + pinctrl_sys_irq: sys_irq-pins { + function = "sys_irq"; + pins = "gpio2"; + }; + + pinctrl_serial_led: serial_led-pins { + pinctrl_serial_led_data: serial_led_data-pins { + function = "serial_led_data"; + pins = "gpio3"; + }; + + pinctrl_serial_led_clk: serial_led_clk-pins { + function = "serial_led_clk"; + pins = "gpio4"; + }; + }; + + pinctrl_inet_led: inet_led-pins { + function = "inet_led"; + pins = "gpio5"; + }; + + pinctrl_ephy0_led: ephy0_led-pins { + function = "ephy0_led"; + pins = "gpio6"; + }; + + pinctrl_ephy1_led: ephy1_led-pins { + function = "ephy1_led"; + pins = "gpio7"; + }; + + pinctrl_ephy2_led: ephy2_led-pins { + function = "ephy2_led"; + pins = "gpio8"; + }; + + pinctrl_ephy3_led: ephy3_led-pins { + function = "ephy3_led"; + pins = "gpio9"; + }; + + pinctrl_robosw_led_data: robosw_led_data-pins { + function = "robosw_led_data"; + pins = "gpio10"; + }; + + pinctrl_robosw_led_clk: robosw_led_clk-pins { + function = "robosw_led_clk"; + pins = "gpio11"; + }; + + pinctrl_robosw_led0: robosw_led0-pins { + function = "robosw_led0"; + pins = "gpio12"; + }; + + pinctrl_robosw_led1: robosw_led1-pins { + function = "robosw_led1"; + pins = "gpio13"; + }; + + pinctrl_usb_device_led: usb_device_led-pins { + function = "usb_device_led"; + pins = "gpio14"; + }; + + pinctrl_pci: pci-pins { + pinctrl_pci_req1: pci_req1-pins { + function = "pci_req1"; + pins = "gpio16"; + }; + + pinctrl_pci_gnt1: pci_gnt1-pins { + function = "pci_gnt1"; + pins = "gpio17"; + }; + + pinctrl_pci_intb: pci_intb-pins { + function = "pci_intb"; + pins = "gpio18"; + }; + + pinctrl_pci_req0: pci_req0-pins { + function = "pci_req0"; + pins = "gpio19"; + }; + + pinctrl_pci_gnt0: pci_gnt0-pins { + function = "pci_gnt0"; + pins = "gpio20"; + }; + }; + + pinctrl_pcmcia: pcmcia-pins { + pinctrl_pcmcia_cd1: pcmcia_cd1-pins { + function = "pcmcia_cd1"; + pins = "gpio22"; + }; + + pinctrl_pcmcia_cd2: pcmcia_cd2-pins { + function = "pcmcia_cd2"; + pins = "gpio23"; + }; + + pinctrl_pcmcia_vs1: pcmcia_vs1-pins { + function = "pcmcia_vs1"; + pins = "gpio24"; + }; + + pinctrl_pcmcia_vs2: pcmcia_vs2-pins { + function = "pcmcia_vs2"; + pins = "gpio25"; + }; + }; + + pinctrl_ebi_cs2: ebi_cs2-pins { + function = "ebi_cs2"; + pins = "gpio26"; + }; + + pinctrl_ebi_cs3: ebi_cs3-pins { + function = "ebi_cs3"; + pins = "gpio27"; + }; + + pinctrl_spi_cs2: spi_cs2-pins { + function = "spi_cs2"; + pins = "gpio28"; + }; + + pinctrl_spi_cs3: spi_cs3-pins { + function = "spi_cs3"; + pins = "gpio29"; + }; + + pinctrl_spi_cs4: spi_cs4-pins { + function = "spi_cs4"; + pins = "gpio30"; + }; + + pinctrl_spi_cs5: spi_cs5-pins { + function = "spi_cs5"; + pins = "gpio31"; + }; + + pinctrl_uart1: uart1-pins { + function = "uart1"; + pins = "uart1_grp"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt new file mode 100644 index 000000000..3914529a3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,cygnus-pinmux.txt @@ -0,0 +1,132 @@ +Broadcom Cygnus IOMUX Controller + +The Cygnus IOMUX controller supports group based mux configuration. In +addition, certain pins can be muxed to GPIO function individually. + +Required properties: + +- compatible: + Must be "brcm,cygnus-pinmux" + +- reg: + Define the base and range of the I/O address space that contains the Cygnus +IOMUX registers + +Properties in subnodes: + +- function: + The mux function to select + +- groups: + The list of groups to select with a given function + +For more details, refer to +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +For example: + + pinmux: pinmux@0301d0c8 { + compatible = "brcm,cygnus-pinmux"; + reg = <0x0301d0c8 0x1b0>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_default>; + + i2s0_default: i2s0_default { + mux { + function = "i2s0"; + groups = "i2s0_0_grp", "i2s0_1_grp"; + }; + }; + }; + +List of supported functions and groups in Cygnus: + +"i2s0": "i2s0_0_grp", "i2s0_1_grp" + +"i2s1": "i2s1_0_grp", "i2s1_1_grp" + +"i2s2": "i2s2_0_grp", "i2s2_1_grp", "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" + +"spdif": "spdif_grp" + +"pwm0": "pwm0_grp" + +"pwm1": "pwm1_grp" + +"pwm2": "pwm2_grp" + +"pwm3": "pwm3_grp" + +"pwm4": "pwm4_grp" + +"pwm5": "pwm5_grp" + +"key": "key0_grp", "key1_grp", "key2_grp", "key3_grp", "key4_grp", "key5_grp", +"key6_grp", "key7_grp", "key8_grp", "key9_grp", "key10_grp", "key11_grp", +"key12_grp", "key13_grp", "key14_grp", "key15_grp" + +"audio_dte": "audio_dte0_grp", "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" + +"smart_card0": "smart_card0_grp", "smart_card0_fcb_grp" + +"smart_card1": "smart_card1_grp", "smart_card1_fcb_grp" + +"spi0": "spi0_grp" + +"spi1": "spi1_grp" + +"spi2": "spi2_grp" + +"spi3": "spi3_grp" + +"spi4": "spi4_0_grp", "spi4_1_grp" + +"spi5": "spi5_grp" + +"sw_led0": "sw_led0_0_grp", "sw_led0_1_grp" + +"sw_led1": "sw_led1_grp" + +"sw_led2": "sw_led2_0_grp", "sw_led2_1_grp" + +"d1w": "d1w_grp" + +"lcd": "lcd_grp" + +"sram": "sram_0_grp", "sram_1_grp" + +"uart0": "uart0_grp" + +"uart1": "uart1_grp", "uart1_dte_grp" + +"uart2": "uart2_grp" + +"uart3": "uart3_grp" + +"uart4": "uart4_grp" + +"qspi": "qspi_0_grp", "qspi_1_grp" + +"nand": "nand_grp" + +"sdio0": "sdio0_grp", "sdio0_cd_grp", "sdio0_mmc_grp" + +"sdio1": "sdio1_data_0_grp", "sdio1_data_1_grp", "sdio1_cd_grp", +"sdio1_led_grp", "sdio1_mmc_grp" + +"can0": "can0_grp" + +"can1": "can1_grp" + +"cam": "cam_led_grp", "cam_0_grp", "cam_1_grp" + +"bsc1": "bsc1_grp" + +"pcie_clkreq": "pcie_clkreq_grp" + +"usb0_oc": "usb0_oc_grp" + +"usb1_oc": "usb1_oc_grp" + +"usb2_oc": "usb2_oc_grp" diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml new file mode 100644 index 000000000..a0ed308b7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,iproc-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc GPIO/PINCONF Controller + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + compatible: + oneOf: + - enum: + - brcm,cygnus-asiu-gpio + - brcm,cygnus-ccm-gpio + - brcm,cygnus-crmu-gpio + - brcm,iproc-gpio + - brcm,iproc-stingray-gpio + - items: + - enum: + - brcm,iproc-hr2-gpio + - brcm,iproc-nsp-gpio + - const: brcm,iproc-gpio + + reg: + minItems: 1 + items: + - description: GPIO Bank registers + - description: IO Ctrl registers + + "#gpio-cells": + const: 2 + + gpio-controller: true + + gpio-ranges: true + + ngpios: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + - ngpios + +patternProperties: + '-pins$': + type: object + additionalProperties: + description: Pin configuration child nodes. + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + pins: + items: + pattern: '^gpio-' + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpio@1800a000 { + compatible = "brcm,cygnus-ccm-gpio"; + reg = <0x1800a000 0x50>, + <0x0301d164 0x20>; + ngpios = <24>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + + touch-pins { + pwr { + pins = "gpio-0"; + drive-strength = <16>; + }; + + event { + pins = "gpio-1"; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml new file mode 100644 index 000000000..0a39dd26e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar pins mux controller + +maintainers: + - Rafał Miłecki <rafal@milecki.pl> + +description: + Some of Northstar SoCs's pins can be used for various purposes thanks to the + mux controller. This binding allows describing mux controller and listing + available functions. They can be referenced later by other bindings to let + system configure controller correctly. + + A list of pins varies across chipsets so few bindings are available. + +properties: + compatible: + enum: + - brcm,bcm4708-pinmux + - brcm,bcm4709-pinmux + - brcm,bcm53012-pinmux + + reg: + maxItems: 1 + + reg-names: + const: cru_gpio_control + +patternProperties: + '-pins$': + type: object + description: pin node + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ spi, i2c, pwm, uart1, mdio, uart2, sdio ] + groups: + minItems: 1 + maxItems: 4 + items: + enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp, + uart1_grp, mdio_grp, uart2_grp, sdio_pwr_grp, sdio_1p8v_grp ] + + required: + - function + - groups + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + const: brcm,bcm4708-pinmux + then: + patternProperties: + '-pins$': + properties: + function: + enum: [ spi, i2c, pwm, uart1 ] + groups: + items: + enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp, + uart1_grp ] + +required: + - reg + - reg-names + +additionalProperties: false + +examples: + - | + pinctrl@1800c1c0 { + compatible = "brcm,bcm4708-pinmux"; + reg = <0x1800c1c0 0x24>; + reg-names = "cru_gpio_control"; + + spi-pins { + function = "spi"; + groups = "spi_grp"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.yaml new file mode 100644 index 000000000..1de23c06f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns2-pinmux.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,ns2-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar2 IOMUX Controller + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + compatible: + const: brcm,ns2-pinmux + + reg: + maxItems: 3 + +additionalProperties: + description: Pin group node properties + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: The mux function to select + $ref: /schemas/types.yaml#/definitions/string + + groups: + items: + enum: [ + nand_grp, nor_data_grp, nor_adv_grp, nor_addr_0_3_grp, + nor_addr_4_5_grp, nor_addr_6_7_grp, nor_addr_8_9_grp, + nor_addr_10_11_grp, nor_addr_12_15_grp, gpio_0_1_grp, gpio_2_5_grp, + gpio_6_7_grp, gpio_8_9_grp, gpio_10_11_grp, gpio_12_13_grp, + gpio_14_17_grp, gpio_18_19_grp, gpio_20_21_grp, gpio_22_23_grp, + gpio_24_25_grp, gpio_26_27_grp, gpio_28_29_grp, gpio_30_31_grp, + pcie_ab1_clk_wak_grp, pcie_a3_clk_wak_grp, pcie_b3_clk_wak_grp, + pcie_b2_clk_wak_grp, pcie_a2_clk_wak_grp, uart0_modem_grp, + uart0_rts_cts_grp, uart0_in_out_grp, uart1_ext_clk_grp, + uart1_dcd_dsr_grp, uart1_ri_dtr_grp, uart1_rts_cts_grp, + uart1_in_out_grp, uart2_rts_cts_grp, pwm_0_grp, pwm_1_grp, pwm_2_grp, + pwm_3_grp + ] + + pins: + items: + enum: [ + qspi_wp, qspi_hold, qspi_cs, qspi_sck, uart3_sin, uart3_sout, + qspi_mosi, qspi_miso, spi0_fss, spi0_rxd, spi0_txd, spi0_sck, + spi1_fss, spi1_rxd, spi1_txd, spi1_sck, sdio0_data7, sdio0_emmc_rst, + sdio0_led_on, sdio0_wp, sdio0_data3, sdio0_data4, sdio0_data5, + sdio0_data6, sdio0_cmd, sdio0_data0, sdio0_data1, sdio0_data2, + sdio1_led_on, sdio1_wp, sdio0_cd_l, sdio0_clk, sdio1_data5, + sdio1_data6, sdio1_data7, sdio1_emmc_rst, sdio1_data1, sdio1_data2, + sdio1_data3, sdio1_data4, sdio1_cd_l, sdio1_clk, sdio1_cmd, + sdio1_data0, ext_mdio_0, ext_mdc_0, usb3_p1_vbus_ppc, + usb3_p1_overcurrent, usb3_p0_vbus_ppc, usb3_p0_overcurrent, + usb2_presence_indication, usb2_vbus_present, usb2_vbus_ppc, + usb2_overcurrent, sata_led1, sata_led0 + ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + slew-rate: true + input-enable: true + input-disable: true + + oneOf: + - required: + - groups + - function + - required: + - pins + +required: + - compatible + - reg + +examples: + - | + pinctrl@6501d130 { + compatible = "brcm,ns2-pinmux"; + reg = <0x6501d130 0x08>, + <0x660a0028 0x04>, + <0x660009b0 0x40>; + + /* Select nand function */ + nand-sel { + function = "nand"; + groups = "nand_grp"; + }; + + /* Pull up the uart3 rx pin */ + uart3-rx { + pins = "uart3_sin"; + bias-pull-up; + }; + + /* Set the drive strength of sdio d4 pin */ + sdio0-d4 { + pins = "sdio0_data4"; + drive-strength = <8>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt new file mode 100644 index 000000000..0844168a6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-gpio.txt @@ -0,0 +1,80 @@ +Broadcom Northstar plus (NSP) GPIO/PINCONF Controller + +Required properties: +- compatible: + Must be "brcm,nsp-gpio-a" + +- reg: + Should contain the register physical address and length for each of + GPIO base, IO control registers + +- #gpio-cells: + Must be two. The first cell is the GPIO pin number (within the + controller's pin space) and the second cell is used for the following: + bit[0]: polarity (0 for active high and 1 for active low) + +- gpio-controller: + Specifies that the node is a GPIO controller + +- ngpios: + Number of gpios supported (58x25 supports 32 and 58x23 supports 24) + +Optional properties: +- interrupts: + Interrupt ID + +- interrupt-controller: + Specifies that the node is an interrupt controller + +- gpio-ranges: + Specifies the mapping between gpio controller and pin-controllers pins. + This requires 4 fields in cells defined as - + 1. Phandle of pin-controller. + 2. GPIO base pin offset. + 3 Pin-control base pin offset. + 4. number of gpio pins which are linearly mapped from pin base. + +Supported generic PINCONF properties in child nodes: +- pins: + The list of pins (within the controller's own pin space) that properties + in the node apply to. Pin names are "gpio-<pin>" + +- bias-disable: + Disable pin bias + +- bias-pull-up: + Enable internal pull up resistor + +- bias-pull-down: + Enable internal pull down resistor + +- drive-strength: + Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) + +Example: + + gpioa: gpio@18000020 { + compatible = "brcm,nsp-gpio-a"; + reg = <0x18000020 0x100>, + <0x1803f1c4 0x1c>; + #gpio-cells = <2>; + gpio-controller; + ngpios = <32>; + gpio-ranges = <&pinctrl 0 0 31>; + interrupt-controller; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + + /* Hog a few default settings */ + pinctrl-names = "default"; + pinctrl-0 = <&led>; + led: led { + pins = "gpio-1"; + bias-pull-up; + }; + + pwr: pwr { + gpio-hog; + gpios = <3 1>; + output-high; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt new file mode 100644 index 000000000..dede11e4e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt @@ -0,0 +1,79 @@ +Broadcom NSP (Northstar plus) IOMUX Controller + +The NSP IOMUX controller supports group based mux configuration. In +addition, certain pins can be muxed to GPIO function individually. + +Required properties: +- compatible: + Must be "brcm,nsp-pinmux" + +- reg: + Should contain the register physical address and length for each of + GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers + +Properties in subnodes: +- function: + The mux function to select + +- groups: + The list of groups to select with a given function + +For more details, refer to +Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +For example: + + pinmux: pinmux@1803f1c0 { + compatible = "brcm,nsp-pinmux"; + reg = <0x1803f1c0 0x04>, + <0x18030028 0x04>, + <0x1803f408 0x04>; + + pinctrl-names = "default"; + pinctrl-0 = <&pwm>, <&gpio_b>, <&nand_sel>; + + pwm: pwm { + function = "pwm"; + groups = "pwm0_grp", "pwm1_grp"; + }; + + gpio_b: gpio_b { + function = "gpio_b"; + groups = "gpio_b_0_grp", "gpio_b_1_grp"; + }; + + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; + }; + +List of supported functions and groups in Northstar Plus: + +"spi": "spi_grp" + +"i2c": "i2c_grp" + +"mdio": "mdio_grp" + +"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" + +"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp" + +"uart1": "uart1_grp" + +"uart2": "uart2_grp" + +"synce": "synce_grp" + +"sata_led_grps": "sata0_led_grp", "sata1_led_grp" + +"xtal_out": "xtal_out_grp" + +"sdio": "sdio_pwr_grp", "sdio_1p8v_grp" + +"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp" + +"nand": "nand_grp" + +"emmc": "emmc_grp" diff --git a/Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml b/Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml new file mode 100644 index 000000000..beb769e88 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/canaan,k210-fpioa.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K210 FPIOA + +maintainers: + - Damien Le Moal <dlemoal@kernel.org> + +description: + The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA) + controller allows assigning any of 256 possible functions to any of + 48 IO pins of the SoC. Pin function configuration is performed on + a per-pin basis. + +properties: + compatible: + const: canaan,k210-fpioa + + reg: + maxItems: 1 + description: + Address and length of the register set for the FPIOA controller. + + clocks: + items: + - description: Controller reference clock source + - description: APB interface clock source + + clock-names: + items: + - const: ref + - const: pclk + + resets: + maxItems: 1 + + canaan,k210-sysctl-power: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of the K210 system controller node + - description: offset of its power domain control register + description: | + phandle of the K210 system controller node and offset of its + power domain control register. + +patternProperties: + '-pinmux$': + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml + description: + FPIOA client devices use sub-nodes to define the desired pin + configuration. Client device sub-nodes use the pinux property + below. + + properties: + pinmux: + description: + List of IO pins alternate functions. The values for each IO + pin is a combination of an IO pin number (0 to 47) with the + desired function for the IO pin. Functions are defined as + macros in include/dt-bindings/pinctrl/k210-fpioa.h. + The K210_FPIOA(IO pin, function) macro is provided to + facilitate the combination of IO pin numbers and functions. + + required: + - pinmux + + additionalProperties: false + + '-pins$': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + description: + FPIOA client devices use sub-nodes to define the desired + configuration of pins. Client device sub-nodes use the + properties below. + + properties: + pins: + description: + List of IO pins affected by the properties specified in this + subnode. IO pins are identified using the pin names "IO_xx". + Pin configuration nodes can also define the power domain to + be used for the SoC pin groups A0 (IO pins 0-5), + A1 (IO pins 6-11), A2 (IO pins 12-17), B0 (IO pins 18-23), + B1 (IO pins 24-29), B2 (IO pins 30-35), B3 (IO pins 30-35), + C0 (IO pins 36-41) and C1 (IO pins 42-47) using the + power-source property. + items: + anyOf: + - pattern: "^(IO_([0-9]*))|(A[0-2])|(B[3-5])|(C[6-7])$" + - enum: [ IO_0, IO_1, IO_2, IO_3, IO_4, IO_5, IO_6, IO_7, + IO_8, IO_9, IO_10, IO_11, IO_12, IO_13, IO_14, + IO_15, IO_16, IO_17, IO_18, IO_19, IO_20, IO_21, + IO_22, IO_23, IO_24, IO_25, IO_26, IO_27, IO_28, + IO_29, IO_30, IO_31, IO_32, IO_33, IO_34, IO_35, + IO_36, IO_37, IO_38, IO_39, IO_40, IO_41, IO_42, + IO_43, IO_44, IO_45, IO_46, IO_47, + A0, A1, A2, B3, B4, B5, C6, C7 ] + bias-disable: true + + bias-pull-down: true + + bias-pull-up: true + + drive-strength: true + + drive-strength-microamp: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + input-polarity-invert: + type: boolean + description: + Enable or disable pin input polarity inversion. + + output-enable: true + + output-disable: true + + output-high: true + + output-low: true + + output-polarity-invert: + type: boolean + description: + Enable or disable pin output polarity inversion. + + slew-rate: true + + power-source: true + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - canaan,k210-sysctl-power + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/k210-fpioa.h> + #include <dt-bindings/clock/k210-clk.h> + #include <dt-bindings/reset/k210-rst.h> + + fpioa: pinmux@502b0000 { + compatible = "canaan,k210-fpioa"; + reg = <0x502b0000 0x100>; + clocks = <&sysclk K210_CLK_FPIOA>, + <&sysclk K210_CLK_APB0>; + clock-names = "ref", "pclk"; + resets = <&sysrst K210_RST_FPIOA>; + canaan,k210-sysctl-power = <&sysctl 108>; + pinctrl-0 = <&jtag_pinctrl>; + pinctrl-names = "default"; + + jtag_pinctrl: jtag-pinmux { + pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>, + <K210_FPIOA(1, K210_PCF_JTAG_TDI)>, + <K210_FPIOA(2, K210_PCF_JTAG_TMS)>, + <K210_FPIOA(3, K210_PCF_JTAG_TDO)>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml new file mode 100644 index 000000000..0b462eb6d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/canaan,k230-pinctrl.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/canaan,k230-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Pin Controller + +maintainers: + - Ze Huang <18771902331@163.com> + +description: + The Canaan Kendryte K230 platform includes 64 IO pins, each capable of + multiplexing up to 5 different functions. Pin function configuration is + performed on a per-pin basis. + +properties: + compatible: + const: canaan,k230-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + '-cfg$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias, input + enable/disable, input schmitt trigger, slew-rate enable/disable, + slew-rate, drive strength. + + properties: + pinmux: + description: + The list of GPIOs and their mux settings that properties in + the node apply to. This should be set with the macro + 'K230_PINMUX(pin, mode)' + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + minimum: 0 + maximum: 15 + + input-enable: true + + output-enable: true + + input-schmitt-enable: true + + slew-rate: + description: | + slew rate control enable + 0: disable + 1: enable + + enum: [0, 1] + + power-source: + description: | + Specifies the power source voltage for the IO bank that the + pin belongs to. Each bank of IO pins operate at a specific, + fixed voltage levels. Incorrect voltage configuration can + damage the chip. The defined constants represent the + possible voltage configurations: + + - K230_MSC_3V3 (value 0): 3.3V power supply + - K230_MSC_1V8 (value 1): 1.8V power supply + + The following banks have the corresponding voltage + configurations: + + - bank IO0 to IO1: Fixed at 1.8V + - bank IO2 to IO13: Fixed at 1.8V + - bank IO14 to IO25: Fixed at 1.8V + - bank IO26 to IO37: Fixed at 1.8V + - bank IO38 to IO49: Fixed at 1.8V + - bank IO50 to IO61: Fixed at 3.3V + - bank IO62 to IO63: Fixed at 1.8V + + enum: [0, 1] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@91105000 { + compatible = "canaan,k230-pinctrl"; + reg = <0x91105000 0x100>; + + uart2-pins { + uart2-pins-cfg { + pinmux = <0x503>, /* uart2 txd */ + <0x603>; /* uart2 rxd */ + slew-rate = <0>; + drive-strength = <4>; + power-source = <1>; + input-enable; + output-enable; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.yaml new file mode 100644 index 000000000..5e000b3fa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,lochnagar.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cirrus,lochnagar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Lochnagar Audio Development Board + +maintainers: + - patches@opensource.cirrus.com + +description: | + Lochnagar is an evaluation and development board for Cirrus Logic + Smart CODEC and Amp devices. It allows the connection of most Cirrus + Logic devices on mini-cards, as well as allowing connection of various + application processor systems to provide a full evaluation platform. + Audio system topology, clocking and power can all be controlled through + the Lochnagar, allowing the device under test to be used in a variety of + possible use cases. + + This binding document describes the binding for the pinctrl portion of + the driver. + + Also see these documents for generic binding information: + [1] GPIO : ../gpio/gpio.txt + [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt + + And these for relevant defines: + [3] include/dt-bindings/pinctrl/lochnagar.h + + This binding must be part of the Lochnagar MFD binding: + [4] ../mfd/cirrus,lochnagar.yaml + +properties: + compatible: + enum: + - cirrus,lochnagar-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + The first cell is the pin number and the second cell is used + to specify optional parameters. + const: 2 + + gpio-ranges: + description: + Range of pins managed by the GPIO controller, see [1]. Both the + GPIO and Pinctrl base should be set to zero and the count to the + appropriate of the LOCHNAGARx_PIN_NUM_GPIOS define, see [3]. + maxItems: 1 + + pin-settings: + type: object + patternProperties: + '-pins$': + description: + The pin configurations are defined as a child of the pinctrl + states node, see [2]. Each sub-node can have the following + properties. + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + groups: + description: + A list of groups to select (either this or "pins" must be + specified), available groups. + enum: [ codec-aif1, codec-aif2, codec-aif3, dsp-aif1, + dsp-aif2, psia1, psia2, gf-aif1, gf-aif2, gf-aif3, + gf-aif4, spdif-aif, usb-aif1, usb-aif2, adat-aif, + soundcard-aif ] + + pins: + description: + A list of pin names to select (either this or "groups" must + be specified), available pins. + enum: [ fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, + fpga-gpio5, fpga-gpio6, codec-gpio1, codec-gpio2, + codec-gpio3, codec-gpio4, codec-gpio5, codec-gpio6, + codec-gpio7, codec-gpio8, dsp-gpio1, dsp-gpio2, + dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, + gf-gpio2, gf-gpio3, gf-gpio7, codec-aif1-bclk, + codec-aif1-rxdat, codec-aif1-lrclk, codec-aif1-txdat, + codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk, + codec-aif2-txdat, codec-aif3-bclk, codec-aif3-rxdat, + codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk, + dsp-aif1-rxdat, dsp-aif1-lrclk, dsp-aif1-txdat, + dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk, + dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk, + psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk, + psia2-txdat, gf-aif3-bclk, gf-aif3-rxdat, + gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk, + gf-aif4-rxdat, gf-aif4-lrclk, gf-aif4-txdat, + gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk, + gf-aif1-txdat, gf-aif2-bclk, gf-aif2-rxdat, + gf-aif2-lrclk, gf-aif2-txdat, dsp-uart1-rx, + dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx, + gf-uart2-rx, gf-uart2-tx, usb-uart-rx, codec-pdmclk1, + codec-pdmdat1, codec-pdmclk2, codec-pdmdat2, + codec-dmicclk1, codec-dmicdat1, codec-dmicclk2, + codec-dmicdat2, codec-dmicclk3, codec-dmicdat3, + codec-dmicclk4, codec-dmicdat4, dsp-dmicclk1, + dsp-dmicdat1, dsp-dmicclk2, dsp-dmicdat2, i2c2-scl, + i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, i2c4-sda, + dsp-standby, codec-mclk1, codec-mclk2, dsp-clkin, + psia1-mclk, psia2-mclk, gf-gpio1, gf-gpio5, + dsp-gpio20, led1, led2 ] + + function: + description: + The mux function to select, available functions. + enum: [ aif, fpga-gpio1, fpga-gpio2, fpga-gpio3, fpga-gpio4, + fpga-gpio5, fpga-gpio6, codec-gpio1, codec-gpio2, + codec-gpio3, codec-gpio4, codec-gpio5, codec-gpio6, + codec-gpio7, codec-gpio8, dsp-gpio1, dsp-gpio2, + dsp-gpio3, dsp-gpio4, dsp-gpio5, dsp-gpio6, + gf-gpio2, gf-gpio3, gf-gpio7, gf-gpio1, gf-gpio5, + dsp-gpio20, codec-clkout, dsp-clkout, pmic-32k, + spdif-clkout, clk-12m288, clk-11m2986, clk-24m576, + clk-22m5792, xmos-mclk, gf-clkout1, gf-mclk1, + gf-mclk3, gf-mclk2, gf-clkout2, codec-mclk1, + codec-mclk2, dsp-clkin, psia1-mclk, psia2-mclk, + spdif-mclk, codec-irq, codec-reset, dsp-reset, + dsp-irq, dsp-standby, codec-pdmclk1, codec-pdmdat1, + codec-pdmclk2, codec-pdmdat2, codec-dmicclk1, + codec-dmicdat1, codec-dmicclk2, codec-dmicdat2, + codec-dmicclk3, codec-dmicdat3, codec-dmicclk4, + codec-dmicdat4, dsp-dmicclk1, dsp-dmicdat1, + dsp-dmicclk2, dsp-dmicdat2, dsp-uart1-rx, + dsp-uart1-tx, dsp-uart2-rx, dsp-uart2-tx, + gf-uart2-rx, gf-uart2-tx, usb-uart-rx, usb-uart-tx, + i2c2-scl, i2c2-sda, i2c3-scl, i2c3-sda, i2c4-scl, + i2c4-sda, spdif-aif, psia1, psia1-bclk, psia1-lrclk, + psia1-rxdat, psia1-txdat, psia2, psia2-bclk, + psia2-lrclk, psia2-rxdat, psia2-txdat, codec-aif1, + codec-aif1-bclk, codec-aif1-lrclk, codec-aif1-rxdat, + codec-aif1-txdat, codec-aif2, codec-aif2-bclk, + codec-aif2-lrclk, codec-aif2-rxdat, codec-aif2-txdat, + codec-aif3, codec-aif3-bclk, codec-aif3-lrclk, + codec-aif3-rxdat, codec-aif3-txdat, dsp-aif1, + dsp-aif1-bclk, dsp-aif1-lrclk, dsp-aif1-rxdat, + dsp-aif1-txdat, dsp-aif2, dsp-aif2-bclk, + dsp-aif2-lrclk, dsp-aif2-rxdat, dsp-aif2-txdat, + gf-aif3, gf-aif3-bclk, gf-aif3-lrclk, gf-aif3-rxdat, + gf-aif3-txdat, gf-aif4, gf-aif4-bclk, gf-aif4-lrclk, + gf-aif4-rxdat, gf-aif4-txdat, gf-aif1, gf-aif1-bclk, + gf-aif1-lrclk, gf-aif1-rxdat, gf-aif1-txdat, gf-aif2, + gf-aif2-bclk, gf-aif2-lrclk, gf-aif2-rxdat, + gf-aif2-txdat, usb-aif1, usb-aif2, adat-aif, + soundcard-aif ] + + output-enable: + description: + Specifies that an AIF group will be used as a master + interface (either this or input-enable is required if a + group is being muxed to an AIF) + + input-enable: + description: + Specifies that an AIF group will be used as a slave + interface (either this or output-enable is required if a + group is being muxed to an AIF) + + additionalProperties: false + + required: + - function + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - pinctrl-0 + - pinctrl-names + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml b/Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml new file mode 100644 index 000000000..482acda88 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cirrus,madera.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cirrus,madera.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic Madera class audio CODECs pinctrl driver + +maintainers: + - patches@opensource.cirrus.com + +description: | + The Cirrus Logic Madera codecs provide a number of GPIO functions for + interfacing to external hardware and to provide logic outputs to other devices. + Certain groups of GPIO pins also have an alternate function, normally as an + audio interface. + + The set of available GPIOs, functions and alternate function groups differs + between CODECs so refer to the datasheet for the CODEC for further information + on what is supported on that device. + + The properties for this driver exist within the parent MFD driver node. + + See also the core bindings for the parent MFD driver: + + Documentation/devicetree/bindings/mfd/cirrus,madera.yaml + + And the generic pinmix bindings: + + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +properties: + pin-settings: + description: + One subnode is required to contain the default settings. It + contains an arbitrary number of configuration subnodes, one for + each group or pin configuration you want to apply as a default. + type: object + patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + properties: + groups: + description: + Name of one pin group to configure. + enum: [ aif1, aif2, aif3, aif4, mif1, mif2, mif3, pdmspk1, + pdmspk2, dmic4, dmic5, dmic6, gpio1, gpio2, gpio3, + gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, + gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, + gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, + gpio28, gpio29, gpio30, gpio31, gpio32, gpio33, + gpio34, gpio35, gpio36, gpio37, gpio38, gpio39 ] + + function: + description: + Name of function to assign to this group. + enum: [ aif1, aif2, aif3, aif4, mif1, mif2, mif3, + pdmspk1, pdmspk2, dmic3, dmic4, dmic5, + dmic6, io, dsp-gpio, irq1, irq2, fll1-clk, + fll1-lock, fll2-clk, fll2-lock, fll3-clk, + fll3-lock, fllao-clk, fllao-lock, opclk, + opclk-async, pwm1, pwm2, spdif, asrc1-in1-lock, + asrc1-in2-lock, asrc2-in1-lock, asrc2-in2-lock, + spkl-short-circuit, spkr-short-circuit, + spk-shutdown, spk-overheat-shutdown, + spk-overheat-warn, timer1-sts, timer2-sts, + timer3-sts, timer4-sts, timer5-sts, timer6-sts, + timer7-sts, timer8-sts, log1-fifo-ne, + log2-fifo-ne, log3-fifo-ne, log4-fifo-ne, + log5-fifo-ne, log6-fifo-ne, log7-fifo-ne, + log8-fifo-ne ] + + bias-disable: true + + bias-bus-hold: true + + bias-pull-up: true + + bias-pull-down: true + + drive-push-pull: true + + drive-open-drain: true + + drive-strength: + enum: [ 4, 8 ] + + input-schmitt-enable: true + + input-schmitt-disable: true + + input-debounce: + maxItems: 1 + + output-low: true + + output-high: true + + additionalProperties: false + + required: + - groups + + additionalProperties: false + +required: + - pinctrl-0 + - pinctrl-names + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml new file mode 100644 index 000000000..8ed53496c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cix,sky1-pinctrl.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cix,sky1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 Soc Pin Controller + +maintainers: + - Gary Yang <gary.yang@cixtech.com> + +description: + The pin-controller is used to control Soc pins. There are two pin-controllers + on Cix Sky1 platform. one is used under S0 state, the other one is used under + S0 and S5 state. + +properties: + compatible: + enum: + - cix,sky1-pinctrl + - cix,sky1-pinctrl-s5 + + reg: + items: + - description: gpio base + +patternProperties: + '-cfg$': + type: object + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + 'pins$': + type: object + additionalProperties: false + + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias pull, + and drive strength. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + Values are constructed from pin number and mux setting, pin + number is left shifted by 8 bits, then ORed with mux setting + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + drive-strength: + description: + typical current when output high level. + enum: [ 2, 3, 5, 6, 8, 9, 11, 12, 13, 14, 17, 18, 20, 21, 23, + 24 ] + + required: + - pinmux + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #define CIX_PAD_GPIO012_FUNC_GPIO012 (11 << 8 | 0x0) + pinctrl@4170000 { + compatible = "cix,sky1-pinctrl"; + reg = <0x4170000 0x1000>; + + wifi_vbat_gpio: wifi-vbat-gpio-cfg { + pins { + pinmux = <CIX_PAD_GPIO012_FUNC_GPIO012>; + bias-pull-up; + drive-strength = <8>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt new file mode 100644 index 000000000..23ce8dc26 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt @@ -0,0 +1,86 @@ +Conexant Digicolor CX92755 General Purpose Pin Mapping + +This document describes the device tree binding of the pin mapping hardware +modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the +Digicolor series of SoCs. + +=== Pin Controller Node === + +Required Properties: + +- compatible: Must be "cnxt,cx92755-pinctrl" +- reg: Base address of the General Purpose Pin Mapping register block and the + size of the block. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Must be <2>. The first cell is the pin number and the + second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h + for possible values. + +For example, the following is the bare minimum node: + + pinctrl: pinctrl@f0000e20 { + compatible = "cnxt,cx92755-pinctrl"; + reg = <0xf0000e20 0x100>; + gpio-controller; + #gpio-cells = <2>; + }; + +As a pin controller device, in addition to the required properties, this node +should also contain the pin configuration nodes that client devices reference, +if any. + +For a general description of GPIO bindings, please refer to ../gpio/gpio.txt. + +=== Pin Configuration Node === + +Each pin configuration node is a sub-node of the pin controller node and is a +container of an arbitrary number of subnodes, called pin group nodes in this +document. + +Please refer to the pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the definition of a +"pin configuration node". + +=== Pin Group Node === + +A pin group node specifies the desired pin mux for an arbitrary number of +pins. The name of the pin group node is optional and not used. + +A pin group node only affects the properties specified in the node, and has no +effect on any properties that are omitted. + +The pin group node accepts a subset of the generic pin config properties. For +details generic pin config properties, please refer to pinctrl-bindings.txt +and <include/linux/pinctrl/pinconfig-generic.h>. + +Required Pin Group Node Properties: + +- pins: Multiple strings. Specifies the name(s) of one or more pins to be + configured by this node. The format of a pin name string is "GP_xy", where x + is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7. +- function: String. Specifies the pin mux selection. Values must be one of: + "gpio", "client_a", "client_b", "client_c" + +Example: + pinctrl: pinctrl@f0000e20 { + compatible = "cnxt,cx92755-pinctrl"; + reg = <0xf0000e20 0x100>; + + uart0_default: uart0_active { + data_signals { + pins = "GP_O0", "GP_O1"; + function = "client_b"; + }; + }; + }; + + uart0: uart@f0000740 { + compatible = "cnxt,cx92755-usart"; + ... + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + }; + +In the example above, a single pin group configuration node defines the +"client select" for the Rx and Tx signals of uart0. The uart0 node references +that pin configuration node using the &uart0_default phandle. diff --git a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt new file mode 100644 index 000000000..4346ff2dd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt @@ -0,0 +1,68 @@ +Cortina Systems Gemini pin controller + +This pin controller is found in the Cortina Systems Gemini SoC family, +see further arm/gemini.txt. It is a purely group-based multiplexing pin +controller. + +The pin controller node must be a subnode of the system controller node. + +Required properties: +- compatible: "cortina,gemini-pinctrl" + +Subnodes of the pin controller contain pin control multiplexing set-up +and pin configuration of individual pins. + +Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes +and generic pin config nodes. + +Supported configurations: +- skew-delay is supported on the Ethernet pins +- drive-strength with 4, 8, 12 or 16 mA as argument is supported for + entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp" + and "pcigrp". + +Example: + + +syscon { + compatible = "cortina,gemini-syscon"; + ... + pinctrl { + compatible = "cortina,gemini-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, + <&vcontrol_default_pins>; + + dram_default_pins: pinctrl-dram { + mux { + function = "dram"; + groups = "dramgrp"; + }; + }; + rtc_default_pins: pinctrl-rtc { + mux { + function = "rtc"; + groups = "rtcgrp"; + }; + }; + power_default_pins: pinctrl-power { + mux { + function = "power"; + groups = "powergrp"; + }; + }; + system_default_pins: pinctrl-system { + mux { + function = "system"; + groups = "systemgrp"; + }; + }; + (...) + uart_default_pins: pinctrl-uart { + mux { + function = "uart"; + groups = "uartrxtxgrp"; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml b/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml new file mode 100644 index 000000000..700ac86c2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/cypress,cy8c95x0.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/cypress,cy8c95x0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress CY8C95X0 I2C GPIO expander + +maintainers: + - Patrick Rudolph <patrick.rudolph@9elements.com> + +description: | + This supports the 20/40/60 pin Cypress CYC95x0 GPIO I2C expanders. + Pin function configuration is performed on a per-pin basis. + +properties: + compatible: + enum: + - cypress,cy8c9520 + - cypress,cy8c9540 + - cypress,cy8c9560 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: + The first cell is the GPIO number and the second cell specifies GPIO + flags, as defined in <dt-bindings/gpio/gpio.h>. + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-line-names: true + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 60 + + vdd-supply: + description: + Optional power supply. + + reset-gpios: + description: GPIO connected to the XRES pin + maxItems: 1 + +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: pincfg-node.yaml# + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: '^gp([0-7][0-7])$' + minItems: 1 + maxItems: 60 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, pwm ] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-enable: true + + output-high: true + + output-low: true + + drive-push-pull: true + + drive-open-drain: true + + drive-open-source: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pinctrl@20 { + compatible = "cypress,cy8c9520"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + vdd-supply = <&p3v3>; + gpio-reserved-ranges = <1 2>, <6 1>, <10 1>, <15 1>; + + pinctrl-0 = <&U62160_pins>, <&U62160_ipins>; + pinctrl-names = "default"; + + U62160_pins: cfg-pins { + pins = "gp03", "gp16", "gp20", "gp50", "gp51"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + U62160_ipins: icfg-pins { + pins = "gp04", "gp17", "gp21", "gp52", "gp53"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctrl.yaml new file mode 100644 index 000000000..d46e7ee63 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/eswin,eic7700-pinctrl.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/eswin,eic7700-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin Eic7700 Pinctrl + +maintainers: + - Yulin Lu <luyulin@eswincomputing.com> + +allOf: + - $ref: pinctrl.yaml# + +description: | + eic7700 pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for one or + more pins. This configuration can include the mux function to select on those pin(s), + and various pin configuration parameters, such as input-enable, pull-up, etc. + +properties: + compatible: + const: eswin,eic7700-pinctrl + + reg: + maxItems: 1 + + vrgmii-supply: + description: + Regulator supply for the RGMII interface IO power domain. + This property should reference a regulator that provides either 1.8V or 3.3V, + depending on the board-level voltage configuration required by the RGMII interface. + +patternProperties: + '-grp$': + type: object + additionalProperties: false + + patternProperties: + '-pins$': + type: object + + properties: + pins: + description: + For eic7700, specifies the name(s) of one or more pins to be configured by + this node. + items: + enum: [ chip_mode, mode_set0, mode_set1, mode_set2, mode_set3, xin, + rst_out_n, key_reset_n, gpio0, por_sel, jtag0_tck, jtag0_tms, + jtag0_tdi, jtag0_tdo, gpio5, spi2_cs0_n, jtag1_tck, jtag1_tms, + jtag1_tdi, jtag1_tdo, gpio11, spi2_cs1_n, pcie_clkreq_n, + pcie_wake_n, pcie_perst_n, hdmi_scl, hdmi_sda, hdmi_cec, + jtag2_trst, rgmii0_clk_125, rgmii0_txen, rgmii0_txclk, + rgmii0_txd0, rgmii0_txd1, rgmii0_txd2, rgmii0_txd3, i2s0_bclk, + i2s0_wclk, i2s0_sdi, i2s0_sdo, i2s_mclk, rgmii0_rxclk, + rgmii0_rxdv, rgmii0_rxd0, rgmii0_rxd1, rgmii0_rxd2, rgmii0_rxd3, + i2s2_bclk, i2s2_wclk, i2s2_sdi, i2s2_sdo, gpio27, gpio28, gpio29, + rgmii0_mdc, rgmii0_mdio, rgmii0_intb, rgmii1_clk_125, rgmii1_txen, + rgmii1_txclk, rgmii1_txd0, rgmii1_txd1, rgmii1_txd2, rgmii1_txd3, + i2s1_bclk, i2s1_wclk, i2s1_sdi, i2s1_sdo, gpio34, rgmii1_rxclk, + rgmii1_rxdv, rgmii1_rxd0, rgmii1_rxd1, rgmii1_rxd2, rgmii1_rxd3, + spi1_cs0_n, spi1_clk, spi1_d0, spi1_d1, spi1_d2, spi1_d3, spi1_cs1_n, + rgmii1_mdc, rgmii1_mdio, rgmii1_intb, usb0_pwren, usb1_pwren, + i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c2_scl, i2c2_sda, + i2c3_scl, i2c3_sda, i2c4_scl, i2c4_sda, i2c5_scl, i2c5_sda, + uart0_tx, uart0_rx, uart1_tx, uart1_rx, uart1_cts, uart1_rts, + uart2_tx, uart2_rx, jtag2_tck, jtag2_tms, jtag2_tdi, jtag2_tdo, + fan_pwm, fan_tach, mipi_csi0_xvs, mipi_csi0_xhs, mipi_csi0_mclk, + mipi_csi1_xvs, mipi_csi1_xhs, mipi_csi1_mclk, mipi_csi2_xvs, + mipi_csi2_xhs, mipi_csi2_mclk, mipi_csi3_xvs, mipi_csi3_xhs, + mipi_csi3_mclk, mipi_csi4_xvs, mipi_csi4_xhs, mipi_csi4_mclk, + mipi_csi5_xvs, mipi_csi5_xhs, mipi_csi5_mclk, spi3_cs_n, spi3_clk, + spi3_di, spi3_do, gpio92, gpio93, s_mode, gpio95, spi0_cs_n, + spi0_clk, spi0_d0, spi0_d1, spi0_d2, spi0_d3, i2c10_scl, + i2c10_sda, i2c11_scl, i2c11_sda, gpio106, boot_sel0, boot_sel1, + boot_sel2, boot_sel3, gpio111, lpddr_ref_clk ] + + function: + description: + Specify the alternative function to be configured for the + given pins. + enum: [ disabled, boot_sel, chip_mode, emmc, fan_tach, + gpio, hdmi, i2c, i2s, jtag, ddr_ref_clk_sel, + lpddr_ref_clk, mipi_csi, osc, pcie, pwm, + rgmii, reset, sata, sdio, spi, s_mode, uart, usb ] + + input-schmitt-enable: true + + input-schmitt-disable: true + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: true + + input-enable: true + + input-disable: true + + drive-strength-microamp: true + + required: + - pins + + additionalProperties: false + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + - if: + properties: + pins: + anyOf: + - pattern: '^rgmii' + - const: lpddr_ref_clk + then: + properties: + drive-strength-microamp: + enum: [3000, 6000, 9000, 12000, 15000, 18000, 21000, 24000] + else: + properties: + drive-strength-microamp: + enum: [6000, 9000, 12000, 15000, 18000, 21000, 24000, 27000] + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@51600080 { + compatible = "eswin,eic7700-pinctrl"; + reg = <0x51600080 0x1fff80>; + vrgmii-supply = <&vcc_1v8>; + + dev-active-grp { + /* group node defining 1 standard pin */ + gpio10-pins { + pins = "jtag1_tdo"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + + /* group node defining 2 I2C pins */ + i2c6-pins { + pins = "uart1_cts", "uart1_rts"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt new file mode 100644 index 000000000..a1050b598 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt @@ -0,0 +1,93 @@ +* Freescale IOMUX Controller (IOMUXC) for i.MX + +The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC +to share one PAD to several functional blocks. The sharing is done by +multiplexing the PAD input/output signals. For each PAD there are up to +8 muxing options (called ALT modes). Since different modules require +different PAD settings (like pull up, keeper, etc) the IOMUXC controls +also the PAD settings parameters. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Freescale IMX pin configuration node is a node of a group of pins which can be +used for a specific device or function. This node represents both mux and config +of the pins in that group. The 'mux' selects the function mode(also named mux +mode) this pin can work on and the 'config' configures various pad settings +such as pull-up, open drain, drive strength, etc. + +Required properties for iomux controller: +- compatible: "fsl,<soc>-iomuxc" + Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs. + +Required properties for pin configuration node: +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val + input_val> are specified using a PIN_FUNC_ID macro, which can be found in + imx*-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. And that's why fsl,pins entry + looks like <PIN_FUNC_ID CONFIG> in the example below. + +Bits used for CONFIG: +NO_PAD_CTL(1 << 31): indicate this pin does not need config. + +SION(1 << 30): Software Input On Field. +Force the selected mux mode input path no matter of MUX_MODE functionality. +By default the input path is determined by functionality of the selected +mux mode (regular). + +Other bits are used for PAD setting. +Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part +of bits definitions. + +NOTE: +Some requirements for using fsl,imx-pinctrl binding: +1. We have pin function node defined under iomux controller node to represent + what pinmux functions this SoC supports. +2. The pin configuration node intends to work on a specific function should + to be defined under that specific function node. + The function node's name should represent well about what function + this group of pins in this pin configuration node are working on. +3. The driver can use the function node's name and pin configuration node's + name describe the pin function and group hierarchy. + For example, Linux IMX pinctrl driver takes the function node's name + as the function name and pin configuration node's name as group name to + create the map table. +4. Each pin configuration node should have a phandle, devices can set pins + configurations by referring to the phandle of that pin configuration node. + +Examples: +usdhc@219c000 { /* uSDHC4 */ + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; +}; + +iomuxc@20e0000 { + compatible = "fsl,imx6q-iomuxc"; + reg = <0x020e0000 0x4000>; + + /* shared pinctrl settings */ + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + .... +}; +Refer to the IOMUXC controller chapter in imx6q datasheet, +0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed, +80Ohm driver strength and Fast Slew Rate. +User should refer to each SoC spec to set the correct value. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx25-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx25-pinctrl.txt new file mode 100644 index 000000000..fd653bde1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx25-pinctrl.txt @@ -0,0 +1,23 @@ +* Freescale IMX25 IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +CONFIG bits definition: +PAD_CTL_HYS (1 << 8) +PAD_CTL_PKE (1 << 7) +PAD_CTL_PUE (1 << 6) +PAD_CTL_PUS_100K_DOWN (0 << 4) +PAD_CTL_PUS_47K_UP (1 << 4) +PAD_CTL_PUS_100K_UP (2 << 4) +PAD_CTL_PUS_22K_UP (3 << 4) +PAD_CTL_ODE_CMOS (0 << 3) +PAD_CTL_ODE_OPENDRAIN (1 << 3) +PAD_CTL_DSE_NOMINAL (0 << 1) +PAD_CTL_DSE_HIGH (1 << 1) +PAD_CTL_DSE_MAX (2 << 1) +PAD_CTL_SRE_FAST (1 << 0) +PAD_CTL_SRE_SLOW (0 << 0) + +Refer to imx25-pinfunc.h in device tree source folder for all available +imx25 PIN_FUNC_ID. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml new file mode 100644 index 000000000..1254bfcaa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX1/i.MX25/i.MX27 IOMUX Controller + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + enum: + - fsl,imx1-iomuxc + - fsl,imx27-iomuxc + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + '^gpio@[0-9a-f]+$': + type: object + $ref: /schemas/gpio/fsl-imx-gpio.yaml + unevaluatedProperties: false + + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + three integers array, represents a group of pins mux and config + setting. The format is fsl,pins = <PIN MUX_ID CONFIG>. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: + PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 + configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN + is the pin number on the specific port (between 0 and 31) + - description: | + MUX_ID is function + (direction << 2) + (gpio_oconf << 4) + + (gpio_iconfa << 8) + (gpio_iconfb << 10) + + function value is used to select the pin function. + Possible values: + 0 - Primary function + 1 - Alternate function + 2 - GPIO + Registers: GIUS (GPIO In Use), GPR (General Purpose Register) + + direction defines the data direction of the pin. + Possible values: + 0 - Input + 1 - Output + Register: DDIR + + gpio_oconf configures the gpio submodule output signal. + This does not have any effect unless GPIO function is + selected. A/B/C_IN are output signals of function blocks + A,B and C. Specific function blocks are described in the + reference manual. + Possible values: + 0 - A_IN + 1 - B_IN + 2 - C_IN + 3 - Data Register + Registers: OCR1, OCR2 + + gpio_iconfa/b configures the gpio submodule input to + functionblocks A and B. GPIO function should be selected if + this is configured. + Possible values: + 0 - GPIO_IN + 1 - Interrupt Status Register + 2 - Pulldown + 3 - Pullup + Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2 + + - description: + CONFIG can be 0 or 1, meaning Pullup disable/enable. + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + pinmux@10015000 { + compatible = "fsl,imx27-iomuxc"; + reg = <0x10015000 0x600>; + + uartgrp { + fsl,pins = < + 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */ + 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */ + 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */ + 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */ + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml new file mode 100644 index 000000000..846e11006 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml @@ -0,0 +1,185 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx35-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX35/IMX5x/IMX6 IOMUX Controller + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + oneOf: + - enum: + - fsl,imx25-iomuxc + - fsl,imx35-iomuxc + - fsl,imx51-iomuxc + - fsl,imx53-iomuxc + - fsl,imx6dl-iomuxc + - fsl,imx6q-iomuxc + - fsl,imx6sl-iomuxc + - fsl,imx6sll-iomuxc + - fsl,imx6sx-iomuxc + - fsl,imx6ul-iomuxc + - fsl,imx6ull-iomuxc-snvs + - items: + - const: fsl,imx50-iomuxc + - const: fsl,imx53-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm/boot/dts/nxp/imx/imx*-pinfunc.h>. The last integer + CONFIG is the pad setting value like pull-up on this pin. Please + refer to matching i.MX Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + Common i.MX35 + PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13) + PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13) + PAD_CTL_HYS (1 << 8) + PAD_CTL_PKE (1 << 7) + PAD_CTL_PUE (1 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_ODE_CMOS (0 << 3) + PAD_CTL_ODE_OPENDRAIN (1 << 3) + PAD_CTL_DSE_NOMINAL (0 << 1) + PAD_CTL_DSE_HIGH (1 << 1) + PAD_CTL_DSE_MAX (2 << 1) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + Common i.MX50/i.MX51/i.MX53 bits + PAD_CTL_HVE (1 << 13) + PAD_CTL_HYS (1 << 8) + PAD_CTL_PKE (1 << 7) + PAD_CTL_PUE (1 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_ODE (1 << 3) + PAD_CTL_DSE_LOW (0 << 1) + PAD_CTL_DSE_MED (1 << 1) + PAD_CTL_DSE_HIGH (2 << 1) + PAD_CTL_DSE_MAX (3 << 1) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + Common i.MX6 bits + PAD_CTL_HYS (1 << 16) + PAD_CTL_PUS_100K_DOWN (0 << 14) + PAD_CTL_PUS_47K_UP (1 << 14) + PAD_CTL_PUS_100K_UP (2 << 14) + PAD_CTL_PUS_22K_UP (3 << 14) + PAD_CTL_PUE (1 << 13) + PAD_CTL_PKE (1 << 12) + PAD_CTL_ODE (1 << 11) + PAD_CTL_SPEED_LOW (0 << 6) + PAD_CTL_SPEED_MED (1 << 6) + PAD_CTL_SPEED_HIGH (3 << 6) + PAD_CTL_DSE_DISABLE (0 << 3) + PAD_CTL_SRE_FAST (1 << 0) + PAD_CTL_SRE_SLOW (0 << 0) + i.MX6SL/MX6SLL specific bits + PAD_CTL_LVE (1 << 22) (MX6SL/SLL only) + i.MX6SLL/i.MX6SX/i.MX6UL/i.MX6ULL specific bits + PAD_CTL_DSE_260ohm (1 << 3) + PAD_CTL_DSE_130ohm (2 << 3) + PAD_CTL_DSE_87ohm (3 << 3) + PAD_CTL_DSE_65ohm (4 << 3) + PAD_CTL_DSE_52ohm (5 << 3) + PAD_CTL_DSE_43ohm (6 << 3) + PAD_CTL_DSE_37ohm (7 << 3) + i.MX6DL/i.MX6Q/i.MX6SL specific bits + PAD_CTL_DSE_240ohm (1 << 3) + PAD_CTL_DSE_120ohm (2 << 3) + PAD_CTL_DSE_80ohm (3 << 3) + PAD_CTL_DSE_60ohm (4 << 3) + PAD_CTL_DSE_48ohm (5 << 3) + PAD_CTL_DSE_40ohm (6 << 3) + PAD_CTL_DSE_34ohm (7 << 3) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: pinctrl@20e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + + mux_uart: uartgrp { + fsl,pins = < + 0x0084 0x0310 0x0000 0 0 0x1b0b1 + 0x0088 0x0314 0x0624 0 3 0x1b0b1 + >; + }; + }; + - | + iomuxc_snvs: pinctrl@2290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x4000>; + + pinctrl_snvs_usbc_det: snvsusbcdetgrp { + fsl,pins = < + 0x0010 0x0054 0x0000 0x5 0x0 0x130b0 + >; + }; + }; + - | + iomuxc_mx6q: pinctrl@20e0000 { + compatible = "fsl,imx6q-iomuxc"; + reg = <0x20e0000 0x4000>; + + pinctrl_uart4: uart4grp { + fsl,pins = + <0x288 0x658 0x000 0x3 0x0 0x140>, + <0x28c 0x65c 0x938 0x3 0x3 0x140>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml new file mode 100644 index 000000000..7bd723ab1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX7D IOMUX Controller + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + oneOf: + - enum: + - fsl,imx7d-iomuxc + - fsl,imx7d-iomuxc-lpsr + + reg: + maxItems: 1 + + fsl,input-sel: + description: + phandle for main iomuxc controller which shares the input select + register for daisy chain settings. + $ref: /schemas/types.yaml#/definitions/phandle + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm/boot/dts/imx7d-pinfunc.h>. The last integer + CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX7D Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +if: + properties: + compatible: + contains: + enum: + - fsl,imx7d-iomuxc-lpsr + +then: + required: + - fsl,input-sel + +additionalProperties: false + +examples: + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart5: uart5grp { + fsl,pins = + <0x0160 0x03D0 0x0714 0x1 0x0 0x7e>, + <0x0164 0x03D4 0x0000 0x1 0x0 0x76>; + }; + }; + - | + iomuxc_lpsr: pinctrl@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + + pinctrl_gpio_lpsr: gpio1-grp { + fsl,pins = + <0x0008 0x0038 0x0000 0x0 0x0 0x59>, + <0x000C 0x003C 0x0000 0x0 0x0 0x59>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml new file mode 100644 index 000000000..957918b73 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx7ulp-iomuxc1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX7ULP IOMUX Controller + +description: | + i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 + ports and IOMUXC DDR for DDR interface. + + Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it + only supports generic pin config. + + Please refer to fsl,imx-pinctrl.txt in this directory for common binding + part and usage. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,imx7ulp-iomuxc1 + + reg: + maxItems: 1 + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + Each entry consists of 5 integers which represents the mux + and config setting for one pin. The first 4 integers + <mux_conf_reg input_reg mux_mode input_val> are specified + using a PIN_FUNC_ID macro, which can be found in + imx7ulp-pinfunc.h in the device tree source folder. + The last integer CONFIG is the pad setting value like + pull-up on this pin. + + Please refer to i.MX7ULP Reference Manual for detailed + CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_conf_reg" indicates the offset of mux register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_mode" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + CONFIG bits definition: + PAD_CTL_OBE (1 << 17) + PAD_CTL_IBE (1 << 16) + PAD_CTL_LK (1 << 16) + PAD_CTL_DSE_HI (1 << 6) + PAD_CTL_DSE_STD (0 << 6) + PAD_CTL_ODE (1 << 5) + PAD_CTL_PUSH_PULL (0 << 5) + PAD_CTL_SRE_SLOW (1 << 2) + PAD_CTL_SRE_STD (0 << 2) + PAD_CTL_PE (1 << 0) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + pinctrl@40ac0000 { + compatible = "fsl,imx7ulp-iomuxc1"; + reg = <0x40ac0000 0x1000>; + + lpuart4grp { + fsl,pins = < + 0x000c 0x0248 0x4 0x1 0x1 + 0x0008 0x024c 0x4 0x1 0x1 + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml new file mode 100644 index 000000000..6068be11d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8M IOMUX Controller + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + enum: + - fsl,imx8mm-iomuxc + - fsl,imx8mn-iomuxc + - fsl,imx8mp-iomuxc + - fsl,imx8mq-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8m[m,n,p,q]-pinfunc.h>. + The last integer CONFIG is the pad setting value like pull-up on this + pin. Please refer to i.MX8M Mini/Nano/Plus/Quad Reference Manual for + detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be + applied. + + required: + - fsl,pins + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mm-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart2: uart2grp { + fsl,pins = + <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, + <0x240 0x4A8 0x000 0x0 0x0 0x140>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml new file mode 100644 index 000000000..7dcf68127 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8ulp-pinctrl.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx8ulp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX8ULP IOMUX Controller + +maintainers: + - Jacky Bai <ping.bai@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imx8ulp-iomuxc1 + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 5 integers and represents the mux and config + setting for one pin. The first 4 integers <mux_config_reg input_reg + mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8ulp-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8ULP Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_config_reg" indicates the offset of mux register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_mode" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@298c0000 { + compatible = "fsl,imx8ulp-iomuxc1"; + reg = <0x298c0000 0x10000>; + + pinctrl_lpuart5: lpuart5grp { + fsl,pins = + <0x0138 0x08F0 0x4 0x3 0x3>, + <0x013C 0x08EC 0x4 0x3 0x3>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml new file mode 100644 index 000000000..96e7b6995 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx9-pinctrl.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imx9-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMX9 IOMUX Controller + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - fsl,imx91-iomuxc + - fsl,imx93-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MX8M Plus Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + iomuxc: pinctrl@443c0000 { + compatible = "fsl,imx93-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart3: uart3grp { + fsl,pins = + <0x48 0x1f8 0x41c 0x1 0x0 0x49>, + <0x4c 0x1fc 0x418 0x1 0x0 0x49>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml new file mode 100644 index 000000000..db5fe66ad --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1050.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMXRT1050 IOMUX Controller + +maintainers: + - Giulio Benetti <giulio.benetti@benettiengineering.com> + - Jesse Taube <Mr.Bossman075@gmail.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imxrt1050-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm/boot/dts/imxrt1050-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MXRT1050 Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: iomuxc@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = + <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>, + <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml new file mode 100644 index 000000000..2e880b3e5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MXRT1170 IOMUX Controller + +maintainers: + - Giulio Benetti <giulio.benetti@benettiengineering.com> + - Jesse Taube <Mr.Bossman075@gmail.com> + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imxrt1170-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg + mux_val input_val> are specified using a PIN_FUNC_ID macro, which can + be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MXRT1170 Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: iomuxc@400e8000 { + compatible = "fsl,imxrt1170-iomuxc"; + reg = <0x400e8000 0x4000>; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = + <0x16C 0x3B0 0x620 0x0 0x0 0xf1>, + <0x170 0x3B4 0x61C 0x0 0x0 0xf1>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml new file mode 100644 index 000000000..fcd729afe --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,scu-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX SCU Client Device Node - Pinctrl Based on SCU Message Protocol + +maintainers: + - Dong Aisheng <aisheng.dong@nxp.com> + +description: i.MX SCU Client Device Node + Client nodes are maintained as children of the relevant IMX-SCU device node. + This binding uses the i.MX common pinctrl binding. + (Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt) + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - fsl,imx8qm-iomuxc + - fsl,imx8qxp-iomuxc + - fsl,imx8dxl-iomuxc + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 3 integers and represents the pin ID, the mux value + and pad setting for the pin. The first 2 integers - pin_id and mux_val - are + specified using a PIN_FUNC_ID macro, which can be found in + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer is + the pad setting value like pull-up on this pin. Please refer to the + appropriate i.MX8 Reference Manual for detailed pad CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "pin_id" indicates the pin ID + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "fsl,imx8qxp-iomuxc"; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + 111 0 0x06000020 + 112 0 0x06000020 + >; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml new file mode 100644 index 000000000..3e13587df --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,vf610-iomuxc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Vybrid VF610 IOMUX Controller + +description: + Please refer to fsl,imx-pinctrl.txt in this directory for common binding part + and usage. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: fsl,vf610-iomuxc + + reg: + maxItems: 1 + +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + two integers array, represents a group of pins mux and config setting. + The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a pin + working on a specific function, CONFIG is the pad setting value such + as pull-up, speed, ode for this pin. Please refer to Vybrid VF610 + datasheet for the valid pad config settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: + PIN_FUN_ID refer to vf610-pinfunc.h in device tree source folder + for all available PIN_FUNC_ID for Vybrid VF610. + - description: | + CONFIG bits definition is + PAD_CTL_SPEED_LOW (1 << 12) + PAD_CTL_SPEED_MED (2 << 12) + PAD_CTL_SPEED_HIGH (3 << 12) + PAD_CTL_SRE_FAST (1 << 11) + PAD_CTL_SRE_SLOW (0 << 11) + PAD_CTL_ODE (1 << 10) + PAD_CTL_HYS (1 << 9) + PAD_CTL_DSE_DISABLE (0 << 6) + PAD_CTL_DSE_150ohm (1 << 6) + PAD_CTL_DSE_75ohm (2 << 6) + PAD_CTL_DSE_50ohm (3 << 6) + PAD_CTL_DSE_37ohm (4 << 6) + PAD_CTL_DSE_30ohm (5 << 6) + PAD_CTL_DSE_25ohm (6 << 6) + PAD_CTL_DSE_20ohm (7 << 6) + PAD_CTL_PUS_100K_DOWN (0 << 4) + PAD_CTL_PUS_47K_UP (1 << 4) + PAD_CTL_PUS_100K_UP (2 << 4) + PAD_CTL_PUS_22K_UP (3 << 4) + PAD_CTL_PKE (1 << 3) + PAD_CTL_PUE (1 << 2) + PAD_CTL_OBE_ENABLE (1 << 1) + PAD_CTL_IBE_ENABLE (1 << 0) + PAD_CTL_OBE_IBE_ENABLE (3 << 0) + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt new file mode 100644 index 000000000..a72dc3178 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt @@ -0,0 +1,217 @@ +Imagination Technologies Pistachio SoC pin controllers +====================================================== + +The pin controllers on Pistachio are a combined GPIO controller, (GPIO) +interrupt controller, and pinmux + pinconf device. The system ("east") pin +controller on Pistachio has 99 pins, 90 of which are MFIOs which can be +configured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs +each. The GPIO banks are represented as sub-nodes of the pad controller node. + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +Required properties for pin controller node: +-------------------------------------------- + - compatible: "img,pistachio-system-pinctrl". + - reg: Address range of the pinctrl registers. + +Required properties for GPIO bank sub-nodes: +-------------------------------------------- + - interrupts: Interrupt line for the GPIO bank. + - gpio-controller: Indicates the device is a GPIO controller. + - #gpio-cells: Must be two. The first cell is the GPIO pin number and the + second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for + a list of possible values. + - interrupt-controller: Indicates the device is an interrupt controller. + - #interrupt-cells: Must be two. The first cell is the GPIO pin number and + the second cell encodes the interrupt flags. See + <dt-bindings/interrupt-controller/irq.h> for a list of valid flags. + +Note that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1. + +Required properties for pin configuration sub-nodes: +---------------------------------------------------- + - pins: List of pins to which the configuration applies. See below for a + list of possible pins. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. This is not applicable for + non-MFIO pins. See below for a list of valid functions for each pin. + - bias-high-impedance: Enable high-impedance mode. + - bias-pull-up: Enable weak pull-up. + - bias-pull-down: Enable weak pull-down. + - bias-bus-hold: Enable bus-keeper mode. + - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12. + - input-schmitt-enable: Enable Schmitt trigger. + - input-schmitt-disable: Disable Schmitt trigger. + - slew-rate: Slew rate control. 0 for slow, 1 for fast. + +Pin Functions +--- --------- +mfio0 spim1 +mfio1 spim1, spim0, uart1 +mfio2 spim1, spim0, uart1 +mfio3 spim1 +mfio4 spim1 +mfio5 spim1 +mfio6 spim1 +mfio7 spim1 +mfio8 spim0 +mfio9 spim0 +mfio10 spim0 +mfio11 spis +mfio12 spis +mfio13 spis +mfio14 spis +mfio15 sdhost, mips_trace_clk, mips_trace_data +mfio16 sdhost, mips_trace_dint, mips_trace_data +mfio17 sdhost, mips_trace_trigout, mips_trace_data +mfio18 sdhost, mips_trace_trigin, mips_trace_data +mfio19 sdhost, mips_trace_dm, mips_trace_data +mfio20 sdhost, mips_trace_probe_n, mips_trace_data +mfio21 sdhost, mips_trace_data +mfio22 sdhost, mips_trace_data +mfio23 sdhost +mfio24 sdhost +mfio25 sdhost +mfio26 sdhost +mfio27 sdhost +mfio28 i2c0, spim0 +mfio29 i2c0, spim0 +mfio30 i2c1, spim0 +mfio31 i2c1, spim1 +mfio32 i2c2 +mfio33 i2c2 +mfio34 i2c3 +mfio35 i2c3 +mfio36 i2s_out, audio_clk_in +mfio37 i2s_out, debug_raw_cca_ind +mfio38 i2s_out, debug_ed_sec20_cca_ind +mfio39 i2s_out, debug_ed_sec40_cca_ind +mfio40 i2s_out, debug_agc_done_0 +mfio41 i2s_out, debug_agc_done_1 +mfio42 i2s_out, debug_ed_cca_ind +mfio43 i2s_out, debug_s2l_done +mfio44 i2s_out +mfio45 i2s_dac_clk, audio_sync +mfio46 audio_trigger +mfio47 i2s_in +mfio48 i2s_in +mfio49 i2s_in +mfio50 i2s_in +mfio51 i2s_in +mfio52 i2s_in +mfio53 i2s_in +mfio54 i2s_in, spdif_in +mfio55 uart0, spim0, spim1 +mfio56 uart0, spim0, spim1 +mfio57 uart0, spim0, spim1 +mfio58 uart0, spim1 +mfio59 uart1 +mfio60 uart1 +mfio61 spdif_out +mfio62 spdif_in +mfio63 eth, mips_trace_clk, mips_trace_data +mfio64 eth, mips_trace_dint, mips_trace_data +mfio65 eth, mips_trace_trigout, mips_trace_data +mfio66 eth, mips_trace_trigin, mips_trace_data +mfio67 eth, mips_trace_dm, mips_trace_data +mfio68 eth, mips_trace_probe_n, mips_trace_data +mfio69 eth, mips_trace_data +mfio70 eth, mips_trace_data +mfio71 eth +mfio72 ir +mfio73 pwmpdm, mips_trace_clk, sram_debug +mfio74 pwmpdm, mips_trace_dint, sram_debug +mfio75 pwmpdm, mips_trace_trigout, rom_debug +mfio76 pwmpdm, mips_trace_trigin, rom_debug +mfio77 mdc_debug, mips_trace_dm, rpu_debug +mfio78 mdc_debug, mips_trace_probe_n, rpu_debug +mfio79 ddr_debug, mips_trace_data, mips_debug +mfio80 ddr_debug, mips_trace_data, mips_debug +mfio81 dreq0, mips_trace_data, eth_debug +mfio82 dreq1, mips_trace_data, eth_debug +mfio83 mips_pll_lock, mips_trace_data, usb_debug +mfio84 audio_pll_lock, mips_trace_data, usb_debug +mfio85 rpu_v_pll_lock, mips_trace_data, sdhost_debug +mfio86 rpu_l_pll_lock, mips_trace_data, sdhost_debug +mfio87 sys_pll_lock, dreq2, socif_debug +mfio88 wifi_pll_lock, dreq3, socif_debug +mfio89 bt_pll_lock, dreq4, dreq5 +tck +trstn +tdi +tms +tdo +jtag_comply +safe_mode +por_disable +resetn + +Example: +-------- +pinctrl@18101c00 { + compatible = "img,pistachio-system-pinctrl"; + reg = <0x18101C00 0x400>; + + gpio0: gpio0 { + interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + gpio5: gpio5 { + interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + ... + + uart0_xfer: uart0-xfer { + uart0-rxd { + pins = "mfio55"; + function = "uart0"; + }; + uart0-txd { + pins = "mfio56"; + function = "uart0"; + }; + }; + + uart0_rts_cts: uart0-rts-cts { + uart0-rts { + pins = "mfio57"; + function = "uart0"; + }; + uart0-cts { + pins = "mfio58"; + function = "uart0"; + }; + }; +}; + +uart@... { + ... + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>; + ... +}; + +usb_vbus: fixed-regulator { + ... + gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>; + ... +}; diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml new file mode 100644 index 000000000..84e960255 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ingenic SoCs pin controller + +description: > + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins + may be used as GPIOs, multiplexed device functions are configured within the + GPIO port configuration registers and it is typical to refer to pins using the + naming scheme "PxN" where x is a character identifying the GPIO port with + which the pin is associated and N is an integer from 0 to 31 identifying the + pin within that GPIO port. For example PA0 is the first pin in GPIO port A, + and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B, + the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128 + pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of + 160 pins. The JZ4750, the JZ4755 the JZ4760, the JZ4770 and the JZ4780 contains + 6 GPIO ports, PA to PF, for a total of 192 pins. The JZ4775 contains 7 GPIO + ports, PA to PG, for a total of 224 pins. + +maintainers: + - Paul Cercueil <paul@crapouillou.net> + +properties: + compatible: + oneOf: + - enum: + - ingenic,jz4730-pinctrl + - ingenic,jz4740-pinctrl + - ingenic,jz4725b-pinctrl + - ingenic,jz4750-pinctrl + - ingenic,jz4755-pinctrl + - ingenic,jz4760-pinctrl + - ingenic,jz4770-pinctrl + - ingenic,jz4775-pinctrl + - ingenic,jz4780-pinctrl + - ingenic,x1000-pinctrl + - ingenic,x1500-pinctrl + - ingenic,x1600-pinctrl + - ingenic,x1830-pinctrl + - ingenic,x2000-pinctrl + - ingenic,x2100-pinctrl + - items: + - const: ingenic,jz4760b-pinctrl + - const: ingenic,jz4760-pinctrl + - items: + - const: ingenic,x1000e-pinctrl + - const: ingenic,x1000-pinctrl + - items: + - const: ingenic,x2000e-pinctrl + - const: ingenic,x2000-pinctrl + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^gpio@[0-9]$": + type: object + properties: + compatible: + enum: + - ingenic,jz4730-gpio + - ingenic,jz4740-gpio + - ingenic,jz4725b-gpio + - ingenic,jz4750-gpio + - ingenic,jz4755-gpio + - ingenic,jz4760-gpio + - ingenic,jz4770-gpio + - ingenic,jz4775-gpio + - ingenic,jz4780-gpio + - ingenic,x1000-gpio + - ingenic,x1500-gpio + - ingenic,x1600-gpio + - ingenic,x1830-gpio + - ingenic,x2000-gpio + - ingenic,x2100-gpio + + reg: + items: + - description: The GPIO bank number + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + description: + Refer to ../interrupt-controller/interrupts.txt for more details. + + interrupts: + maxItems: 1 + + required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + function: true + groups: true + pins: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + output-low: true + output-high: true + additionalProperties: false + + - type: object + additionalProperties: + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + function: true + groups: true + pins: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + output-low: true + output-high: true + additionalProperties: false + +examples: + - | + pinctrl@10010000 { + compatible = "ingenic,jz4770-pinctrl"; + reg = <0x10010000 0x600>; + + #address-cells = <1>; + #size-cells = <0>; + + gpio@0 { + compatible = "ingenic,jz4770-gpio"; + reg = <0>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <17>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml new file mode 100644 index 000000000..1144ca289 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/intel,lgm-io.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain SoC pinmux & GPIO controller + +maintainers: + - Rahul Tanwar <rahul.tanwar@linux.intel.com> + +description: | + Pinmux & GPIO controller controls pin multiplexing & configuration including + GPIO function selection & GPIO attributes configuration. + +properties: + compatible: + const: intel,lgm-io + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: pinmux-node.yaml# + + properties: + function: true + groups: true + pins: true + pinmux: true + bias-pull-up: true + bias-pull-down: true + drive-strength: true + slew-rate: true + drive-open-drain: true + output-enable: true + + required: + - function + - groups + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + # Pinmux controller node + - | + pinctrl: pinctrl@e2880000 { + compatible = "intel,lgm-io"; + reg = <0xe2880000 0x100000>; + + uart0-pins { + pins = <64>, /* UART_RX0 */ + <65>; /* UART_TX0 */ + function = "CONSOLE_UART0"; + pinmux = <1>, + <1>; + groups = "CONSOLE_UART0"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml new file mode 100644 index 000000000..ec9848192 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay pin controller + +maintainers: + - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> + +description: | + Intel Keem Bay SoC integrates a pin controller which enables control + of pin directions, input/output values and configuration + for a total of 80 pins. + +properties: + compatible: + const: intel,keembay-pinctrl + + reg: + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + ngpios: + description: The number of GPIOs exposed. + const: 80 + + interrupts: + description: + Specifies the interrupt lines to be used by the controller. + Each interrupt line is shared by up to 4 GPIO lines. + maxItems: 8 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +patternProperties: + '^gpio@[0-9a-f]*$': + type: object + additionalProperties: false + + description: + Child nodes can be specified to contain pin configuration information, + which can then be utilized by pinctrl client devices. + The following properties are supported. + + properties: + pins: + description: | + The name(s) of the pins to be configured in the child node. + Supported pin names are "GPIO0" up to "GPIO79". + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: true + + drive-strength: + description: IO pads drive strength in milli Ampere. + enum: [2, 4, 8, 12] + + bias-bus-hold: + type: boolean + + input-schmitt-enable: + type: boolean + + slew-rate: + description: GPIO slew rate control. + 0 - Fast(~100MHz) + 1 - Slow(~50MHz) + enum: [0, 1] + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - ngpios + - '#gpio-cells' + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + // Example 1 + gpio@0 { + compatible = "intel,keembay-pinctrl"; + reg = <0x600b0000 0x88>, + <0x600b0190 0x1ac>; + gpio-controller; + ngpios = <0x50>; + #gpio-cells = <0x2>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // Example 2 + gpio@1 { + compatible = "intel,keembay-pinctrl"; + reg = <0x600c0000 0x88>, + <0x600c0190 0x1ac>; + gpio-controller; + ngpios = <0x50>; + #gpio-cells = <0x2>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt new file mode 100644 index 000000000..ac4da9fe0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-falcon.txt @@ -0,0 +1,83 @@ +Lantiq FALCON pinmux controller + +Required properties: +- compatible: "lantiq,pinctrl-falcon" +- reg: Should contain the physical address and length of the gpio/pinmux + register range + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Lantiq's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and two pin configuration parameters: +pull-up and open-drain + +The name of each subnode is not important as long as it is unique; all subnodes +should be enumerated and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +We support 2 types of nodes. + +Definition of mux function groups: + +Required subnode-properties: +- lantiq,groups : An array of strings. Each string contains the name of a group. + Valid values for these names are listed below. +- lantiq,function: A string containing the name of the function to mux to the + group. Valid values for function names are listed below. + +Valid values for group and function names: + + mux groups: + por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c, + jtag, slic, pcm, asc1 + + functions: + rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm + + +Definition of pin configurations: + +Required subnode-properties: +- lantiq,pins : An array of strings. Each string contains the name of a pin. + Valid values for these names are listed below. + +Optional subnode-properties: +- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down +- lantiq,drive-current: Boolean, enables drive-current +- lantiq,slew-rate: Boolean, enables slew-rate + +Example: + pinmux0 { + compatible = "lantiq,pinctrl-falcon"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + asc0 { + lantiq,groups = "asc0"; + lantiq,function = "asc"; + }; + ntr { + lantiq,groups = "ntr8k"; + lantiq,function = "ntr"; + }; + i2c { + lantiq,groups = "i2c"; + lantiq,function = "i2c"; + }; + hrst { + lantiq,groups = "hrst"; + lantiq,function = "rst"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt new file mode 100644 index 000000000..6bd9bc61b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/lantiq,pinctrl-xway.txt @@ -0,0 +1,158 @@ +Lantiq XWAY pinmux controller + +Required properties: +- compatible: "lantiq,<chip>-pinctrl", where <chip> is: + "ase" (XWAY AMAZON Family) + "danube" (XWAY DANUBE Family) + "xrx100" (XWAY xRX100 Family) + "xrx200" (XWAY xRX200 Family) + "xrx300" (XWAY xRX300 Family) +- reg: Should contain the physical address and length of the gpio/pinmux + register range + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Lantiq's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those group(s), and two pin configuration parameters: +pull-up and open-drain + +The name of each subnode is not important as long as it is unique; all subnodes +should be enumerated and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +We support 2 types of nodes. + +Definition of mux function groups: + +Required subnode-properties: +- lantiq,groups : An array of strings. Each string contains the name of a group. + Valid values for these names are listed below. +- lantiq,function: A string containing the name of the function to mux to the + group. Valid values for function names are listed below. + +Valid values for group and function names: + +AMAZON: + mux groups: + exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, + spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0, + clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2 + + functions: + spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe + +DANUBE: + mux groups: + exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, + ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1, + spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, + gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, + req1, req2, req3, dfe led0, dfe led1 + + functions: + spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe + +xRX100: + mux groups: + exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk, + ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, + spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, + spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, + clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, + dfe led0, dfe led1 + + functions: + spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe + +xRX200: + mux groups: + exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk, + ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, + spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, + spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts, + usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di, + usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2, + stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, + gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1, + gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2 + + functions: + spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy + +xRX300: + mux groups: + exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle, + nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5, + nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do, + spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx, + usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2, + mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1 + + functions: + spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy + + +Definition of pin configurations: + +Required subnode-properties: +- lantiq,pins : An array of strings. Each string contains the name of a pin. + Valid values for these names are listed below. + +Optional subnode-properties: +- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. + 0: none, 1: down, 2: up. +- lantiq,open-drain: Boolean, enables open-drain on the defined pin. + +Valid values for AMAZON pin names: + Pinconf pins can be referenced via the names io0-io31. + +Valid values for DANUBE pin names: + Pinconf pins can be referenced via the names io0-io31. + +Valid values for xRX100 pin names: + Pinconf pins can be referenced via the names io0-io55. + +Valid values for xRX200 pin names: + Pinconf pins can be referenced via the names io0-io49. + +Valid values for xRX300 pin names: + Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11, + io13-io19,io23-io27,io34-io36, + io42-io43,io48-io61. + +Example: + gpio: pinmux@e100b10 { + compatible = "lantiq,danube-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + #gpio-cells = <2>; + gpio-controller; + reg = <0xE100B10 0xA0>; + + state_default: pinmux { + stp { + lantiq,groups = "stp"; + lantiq,function = "stp"; + }; + pci { + lantiq,groups = "gnt1"; + lantiq,function = "pci"; + }; + conf_out { + lantiq,pins = "io4", "io5", "io6"; /* stp */ + lantiq,open-drain; + lantiq,pull = <0>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml new file mode 100644 index 000000000..bd8a45843 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/loongson,ls2k-pinctrl.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/loongson,ls2k-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-2 SoC Pinctrl Controller + +maintainers: + - zhanghongchen <zhanghongchen@loongson.cn> + - Yinbo Zhu <zhuyinbo@loongson.cn> + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: loongson,ls2k-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + + additionalProperties: false + + patternProperties: + 'pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + + unevaluatedProperties: false + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0, + nand, sata_led, i2s, hda] + function: + description: + The function that a group of pins is muxed to + enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0, + nand, sata_led, i2s, hda] + + required: + - groups + - function + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pctrl: pinctrl@1fe00420 { + compatible = "loongson,ls2k-pinctrl"; + reg = <0x1fe00420 0x18>; + sdio_pins_default: sdio-pins { + sdio-pinmux { + groups = "sdio"; + function = "sdio"; + }; + + sdio-det-pinmux { + groups = "pwm2"; + function = "gpio"; + }; + }; + + pwm1_pins_default: pwm1-pins { + pinmux { + groups = "pwm1"; + function = "pwm1"; + }; + }; + + pwm0_pins_default: pwm0-pins { + pinmux { + groups = "pwm0"; + function = "pwm0"; + }; + }; + + i2c1_pins_default: i2c1-pins { + pinmux { + groups = "i2c1"; + function = "i2c1"; + }; + }; + + i2c0_pins_default: i2c0-pins { + pinmux { + groups = "i2c0"; + function = "i2c0"; + }; + }; + + nand_pins_default: nand-pins { + pinmux { + groups = "nand"; + function = "nand"; + }; + }; + + hda_pins_default: hda-pins { + grp0-pinmux { + groups = "hda"; + function = "hda"; + }; + + grp1-pinmux { + groups = "i2s"; + function = "gpio"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml new file mode 100644 index 000000000..afea9424c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,ac5-pinctrl.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,ac5-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell AC5 pin controller + +maintainers: + - Chris Packham <chris.packham@alliedtelesis.co.nz> + +description: + Bindings for Marvell's AC5 memory-mapped pin controller. + +properties: + compatible: + items: + - const: marvell,ac5-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + marvell,function: + $ref: /schemas/types.yaml#/definitions/string + description: + Indicates the function to select. + enum: [ dev_init_done, ge, gpio, i2c0, i2c1, int_out, led, nand, pcie, ptp, sdio, + spi0, spi1, synce, tsen_int, uart0, uart1, uart2, uart3, uartsd, wd_int, xg ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + items: + enum: [ mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, + mpp10, mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19, + mpp20, mpp21, mpp22, mpp23, mpp24, mpp25, mpp26, mpp27, mpp28, mpp29, + mpp30, mpp31, mpp32, mpp33, mpp34, mpp35, mpp36, mpp37, mpp38, mpp39, + mpp40, mpp41, mpp42, mpp43, mpp44, mpp45 ] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@80020100 { + compatible = "marvell,ac5-pinctrl"; + reg = <0x80020100 0x20>; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "i2c0"; + }; + + i2c0_gpio: i2c0-gpio-pins { + marvell,pins = "mpp26", "mpp27"; + marvell,function = "gpio"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,ap806-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,ap806-pinctrl.yaml new file mode 100644 index 000000000..00a7e358a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,ap806-pinctrl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,ap806-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell AP806 pin controller + +maintainers: + - Gregory Clement <gregory.clement@bootlin.com> + - Miquel Raynal <miquel.raynal@bootlin.com> + +properties: + compatible: + const: marvell,ap806-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + properties: + marvell,function: + $ref: /schemas/types.yaml#/definitions/string + description: + Indicates the function to select. + enum: [ gpio, i2c0, sdio, spi0, uart0, uart1 ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + maxItems: 20 + items: + enum: [ + mpp0, mpp1, mpp2, mpp3, mpp4, mpp5, mpp6, mpp7, mpp8, mpp9, mpp10, + mpp11, mpp12, mpp13, mpp14, mpp15, mpp16, mpp17, mpp18, mpp19 + ] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "marvell,ap806-pinctrl"; + + uart0_pins: uart0-pins { + marvell,pins = "mpp11", "mpp19"; + marvell,function = "uart0"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt new file mode 100644 index 000000000..8662f3aaf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt @@ -0,0 +1,99 @@ +* Marvell Armada 370 SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,88f6710-pinctrl" +- reg: register specifier of MPP registers + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +name pins functions +================================================================================ +mpp0 0 gpio, uart0(rxd) +mpp1 1 gpo, uart0(txd) +mpp2 2 gpio, i2c0(sck), uart0(txd) +mpp3 3 gpio, i2c0(sda), uart0(rxd) +mpp4 4 gpio, vdd(cpu-pd) +mpp5 5 gpo, ge0(txclkout), uart1(txd), spi1(sck), audio(mclk) +mpp6 6 gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo) +mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk) +mpp8 8 gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk) +mpp9 9 gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo) +mpp10 10 gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi) +mpp11 11 gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1), + sata1(prsnt), spi1(cs1) +mpp12 12 gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0), + audio(spdifi) +mpp13 13 gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk), + audio(rmclk) +mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi), + spi0(cs2) +mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso), + spi0(cs3) +mpp16 16 gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk) +mpp17 17 gpo, ge(mdc) +mpp18 18 gpio, ge(mdio) +mpp19 19 gpio, ge0(txclk), ge1(txclkout), tdm(pclk) +mpp20 20 gpo, ge0(txd4), ge1(txd0) +mpp21 21 gpo, ge0(txd5), ge1(txd1), uart1(txd) +mpp22 22 gpo, ge0(txd6), ge1(txd2), uart0(rts) +mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi) +mpp24 24 gpio, ge0(col), ge1(txctl), spi1(cs0) +mpp25 25 gpio, ge0(rxerr), ge1(rxd0), uart1(rxd) +mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso) +mpp27 27 gpio, ge0(rxd4), ge1(rxd2), uart0(cts) +mpp28 28 gpio, ge0(rxd5), ge1(rxd3) +mpp29 29 gpio, ge0(rxd6), ge1(rxctl), i2c1(sda) +mpp30 30 gpio, ge0(rxd7), ge1(rxclk), i2c1(sck) +mpp31 31 gpio, tclk, ge0(txerr) +mpp32 32 gpio, spi0(cs0) +mpp33 33 gpio, dev(bootcs), spi0(cs0) +mpp34 34 gpo, dev(we0), spi0(mosi) +mpp35 35 gpo, dev(oe), spi0(sck) +mpp36 36 gpo, dev(a1), spi0(miso) +mpp37 37 gpo, dev(a0), sata0(prsnt) +mpp38 38 gpio, dev(ready), uart1(cts), uart0(cts) +mpp39 39 gpo, dev(ad0), audio(spdifo) +mpp40 40 gpio, dev(ad1), uart1(rts), uart0(rts) +mpp41 41 gpio, dev(ad2), uart1(rxd) +mpp42 42 gpo, dev(ad3), uart1(txd) +mpp43 43 gpo, dev(ad4), audio(bclk) +mpp44 44 gpo, dev(ad5), audio(mclk) +mpp45 45 gpo, dev(ad6), audio(lrclk) +mpp46 46 gpo, dev(ad7), audio(sdo) +mpp47 47 gpo, dev(ad8), sd0(clk), audio(spdifo) +mpp48 48 gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt), + spi0(cs1) +mpp49 49 gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0), + audio(spdifi) +mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso), + audio(rmclk) +mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi) +mpp52 52 gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck) +mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2), + pcie(clkreq1) +mpp54 54 gpo, dev(ad15), tdm(dtx) +mpp55 55 gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt), + sata0(prsnt) +mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3), + pcie(clkreq0), spi1(cs1) +mpp57 57 gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt), + audio(sdo) +mpp58 58 gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk), + uart0(rts) +mpp59 59 gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk) +mpp60 60 gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rstout), + audio(sdi) +mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk) +mpp62 62 gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0), + audio(mclk), uart0(cts) +mpp63 63 gpio, spi0(sck), tclk +mpp64 64 gpio, spi0(miso), spi0(cs1) +mpp65 65 gpio, spi0(mosi), spi0(cs2) + +Note: According to the datasheet mpp63 is a gpo but there is at least +one example of a gpio usage on the board D-Link DNS-327L diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt new file mode 100644 index 000000000..06e5bb036 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-375-pinctrl.txt @@ -0,0 +1,82 @@ +* Marvell Armada 375 SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,88f6720-pinctrl" +- reg: register specifier of MPP registers + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +name pins functions +================================================================================ +mpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) +mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) +mpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) +mpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) +mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) +mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) +mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk) +mpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) +mpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) +mpp9 9 gpio, spi0(sck), spi1(sck), nand(we) +mpp10 10 gpio, dram(vttctrl), led(c1), nand(re) +mpp11 11 gpio, dev(a0), led(c2), audio(sdo) +mpp12 12 gpio, dev(a1), audio(bclk) +mpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout) +mpp14 14 gpio, i2c0(sda), uart1(txd) +mpp15 15 gpio, i2c0(sck), uart1(rxd) +mpp16 16 gpio, uart0(txd) +mpp17 17 gpio, uart0(rxd) +mpp18 18 gpio, tdm(int) +mpp19 19 gpio, tdm(rst) +mpp20 20 gpio, tdm(pclk) +mpp21 21 gpio, tdm(fsync) +mpp22 22 gpio, tdm(drx) +mpp23 23 gpio, tdm(dtx) +mpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts) +mpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts) +mpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts) +mpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts) +mpp28 28 gpio, led(p3), ge1(txctl), sd(clk) +mpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) +mpp30 30 gpio, ge1(txd0), spi1(cs0) +mpp31 31 gpio, ge1(txd1), spi1(mosi) +mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig) +mpp33 33 gpio, ge1(txd3), spi1(miso) +mpp34 34 gpio, ge1(txclkout), spi1(sck) +mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) +mpp36 36 gpio, pcie0(clkreq) +mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc) +mpp38 38 gpio, pcie1(clkreq), ge(mdio) +mpp39 39 gpio, ref(clkout) +mpp40 40 gpio, uart1(txd) +mpp41 41 gpio, uart1(rxd) +mpp42 42 gpio, spi1(cs2), led(c0) +mpp43 43 gpio, sata0(prsnt), dram(vttctrl) +mpp44 44 gpio, sata0(prsnt) +mpp45 45 gpio, spi0(cs2), pcie0(rstout) +mpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) +mpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) +mpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) +mpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) +mpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) +mpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) +mpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) +mpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3) +mpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl) +mpp55 55 gpio, ge0(rxclk), ge1(rxclk) +mpp56 56 gpio, ge0(txclkout), ge1(txclkout) +mpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) +mpp58 58 gpio, led(c0) +mpp59 59 gpio, led(c1) +mpp60 60 gpio, uart1(txd), led(c2) +mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) +mpp62 62 gpio, i2c1(sck), led(p1) +mpp63 63 gpio, ptp(trig), led(p2), dev(burst/last) +mpp64 64 gpio, dram(vttctrl), led(p3) +mpp65 65 gpio, sata1(prsnt) +mpp66 66 gpio, ptp(evreq), spi1(cs3) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt new file mode 100644 index 000000000..54ec4c0a0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-38x-pinctrl.txt @@ -0,0 +1,80 @@ +* Marvell Armada 380/385 SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or + "marvell,88f6828-pinctrl" depending on the specific variant of the + SoC being used. +- reg: register specifier of MPP registers + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +name pins functions +================================================================================ +mpp0 0 gpio, ua0(rxd) +mpp1 1 gpio, ua0(txd) +mpp2 2 gpio, i2c0(sck) +mpp3 3 gpio, i2c0(sda) +mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts) +mpp5 5 gpio, ge(mdio), ua1(rxd), ua0(cts) +mpp6 6 gpio, ge0(txclkout), ge0(crs), dev(cs3) +mpp7 7 gpio, ge0(txd0), dev(ad9) +mpp8 8 gpio, ge0(txd1), dev(ad10) +mpp9 9 gpio, ge0(txd2), dev(ad11) +mpp10 10 gpio, ge0(txd3), dev(ad12) +mpp11 11 gpio, ge0(txctl), dev(ad13) +mpp12 12 gpio, ge0(rxd0), pcie0(rstout), spi0(cs1), dev(ad14), pcie3(clkreq) +mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pcie2(clkreq) +mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq) +mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi) +mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), pcie1(clkreq) [1] +mpp17 17 gpio, ge0(rxclk), ptp(clk), ua1(rxd), spi0(sck), sata1(prsnt), sata0(prsnt) +mpp18 18 gpio, ge0(rxerr), ptp(trig), ua1(txd), spi0(cs0) +mpp19 19 gpio, ge0(col), ptp(evreq), ge0(txerr), sata1(prsnt), ua0(cts) +mpp20 20 gpio, ge0(txclk), ptp(clk), sata0(prsnt), ua0(rts) +mpp21 21 gpio, spi0(cs1), ge1(rxd0), sata0(prsnt), sd0(cmd), dev(bootcs), sata1(prsnt) +mpp22 22 gpio, spi0(mosi), dev(ad0) +mpp23 23 gpio, spi0(sck), dev(ad2) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) +mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) +mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) +mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2) +mpp28 28 gpio, ge1(txd0), sd0(clk), dev(ad5) +mpp29 29 gpio, ge1(txd1), dev(ale0) +mpp30 30 gpio, ge1(txd2), dev(oe) +mpp31 31 gpio, ge1(txd3), dev(ale1) +mpp32 32 gpio, ge1(txctl), dev(we0) +mpp33 33 gpio, dram(deccerr), dev(ad3) +mpp34 34 gpio, dev(ad1) +mpp35 35 gpio, ref(clk_out1), dev(a1) +mpp36 36 gpio, ptp(trig), dev(a0) +mpp37 37 gpio, ptp(clk), ge1(rxclk), sd0(d3), dev(ad8) +mpp38 38 gpio, ptp(evreq), ge1(rxd1), ref(clk_out0), sd0(d0), dev(ad4) +mpp39 39 gpio, i2c1(sck), ge1(rxd2), ua0(cts), sd0(d1), dev(a2) +mpp40 40 gpio, i2c1(sda), ge1(rxd3), ua0(rts), sd0(d2), dev(ad6) +mpp41 41 gpio, ua1(rxd), ge1(rxctl), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0) +mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) +mpp44 44 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [3] +mpp45 45 gpio, ref(clk_out0), pcie0(rstout), ua1(rxd) +mpp46 46 gpio, ref(clk_out1), pcie0(rstout), ua1(txd) +mpp47 47 gpio, sata0(prsnt), sata1(prsnt), sata2(prsnt) [2], sata3(prsnt) [2] +mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(clkreq) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5), pcie1(clkreq) +mpp50 50 gpio, pcie0(rstout), tdm(drx), audio(extclk), sd0(cmd) +mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig) +mpp52 52 gpio, pcie0(rstout), tdm(int), audio(sdi), sd0(d6), ptp(clk) +mpp53 53 gpio, sata1(prsnt), sata0(prsnt), tdm(rst), audio(bclk), sd0(d7), ptp(evreq) +mpp54 54 gpio, sata0(prsnt), sata1(prsnt), pcie0(rstout), ge0(txerr), sd0(d3) +mpp55 55 gpio, ua1(cts), ge(mdio), pcie1(clkreq) [1], spi1(cs1), sd0(d0), ua1(rxd) +mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) + +[1]: only available on 88F6820 and 88F6828 +[2]: only available on 88F6828 diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt new file mode 100644 index 000000000..a40b60f1c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt @@ -0,0 +1,84 @@ +* Marvell Armada 39x SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or + "marvell,88f6928-pinctrl" depending on the specific variant of the + SoC being used. +- reg: register specifier of MPP registers + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +name pins functions +================================================================================ +mpp0 0 gpio, ua0(rxd) +mpp1 1 gpio, ua0(txd) +mpp2 2 gpio, i2c0(sck) +mpp3 3 gpio, i2c0(sda) +mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc) +mpp5 5 gpio, ua1(rxd), ua0(cts), smi(mdio) +mpp6 6 gpio, dev(cs3), xsmi(mdio) +mpp7 7 gpio, dev(ad9), xsmi(mdc) +mpp8 8 gpio, dev(ad10), ptp(trig) +mpp9 9 gpio, dev(ad11), ptp(clk) +mpp10 10 gpio, dev(ad12), ptp(evreq) +mpp11 11 gpio, dev(ad13), led(clk) +mpp12 12 gpio, pcie0(rstout), dev(ad14), led(stb) +mpp13 13 gpio, dev(ad15), pcie2(clkreq), led(data) +mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd) +mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck) +mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda) +mpp17 17 gpio, ua1(rxd), spi0(sck), sata1(prsnt) [1], sata0(prsnt) [1], smi(mdio) +mpp18 18 gpio, ua1(txd), spi0(cs0), i2c2(sck) +mpp19 19 gpio, sata1(prsnt) [1], ua0(cts), ua1(rxd), i2c2(sda) +mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc) +mpp21 21 gpio, spi0(cs1), sata0(prsnt) [1], sd0(cmd), dev(bootcs), + sata1(prsnt) [1], ge(rxd0) +mpp22 22 gpio, spi0(mosi), dev(ad0) +mpp23 23 gpio, spi0(sck), dev(ad2) +mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready) +mpp25 25 gpio, spi0(cs0), ua0(rts), ua1(txd), sd0(d5), dev(cs0) +mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1) +mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout) +mpp28 28 gpio, sd0(clk), dev(ad5), ge(txd0) +mpp29 29 gpio, dev(ale0), ge(txd1) +mpp30 30 gpio, dev(oe), ge(txd2) +mpp31 31 gpio, dev(ale1), ge(txd3) +mpp32 32 gpio, dev(we0), ge(txctl) +mpp33 33 gpio, dram(deccerr), dev(ad3) +mpp34 34 gpio, dev(ad1) +mpp35 35 gpio, ref(clk), dev(a1) +mpp36 36 gpio, dev(a0) +mpp37 37 gpio, sd0(d3), dev(ad8), ge(rxclk) +mpp38 38 gpio, ref(clk), sd0(d0), dev(ad4), ge(rxd1) +mpp39 39 gpio, i2c1(sck), ua0(cts), sd0(d1), dev(a2), ge(rxd2) +mpp40 40 gpio, i2c1(sda), ua0(rts), sd0(d2), dev(ad6), ge(rxd3) +mpp41 41 gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burst/last), nand(rb0), ge(rxctl) +mpp42 42 gpio, ua1(txd), ua0(rts), dev(ad7) +mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1) +mpp44 44 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(clk) +mpp45 45 gpio, ref(clk), pcie0(rstout), ua1(rxd) +mpp46 46 gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb) +mpp47 47 gpio, sata0(prsnt) [1], sata1(prsnt) [1], sata2(prsnt) [2], + sata3(prsnt) [2], led(data) +mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkreq), ua1(txd) +mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync) [2], + audio(lrclk) [2], sd0(d5), ua2(rxd) +mpp50 50 gpio, pcie0(rstout), tdm(drx) [2], audio(extclk) [2], sd0(cmd), ua2(rxd) +mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd) +mpp52 52 gpio, pcie0(rstout), tdm(int) [2], audio(sdi) [2], sd0(d6), i2c3(sck) +mpp53 53 gpio, sata1(prsnt) [1], sata0(prsnt) [1], tdm(rst) [2], audio(bclk) [2], sd0(d7), i2c3(sda) +mpp54 54 gpio, sata0(prsnt) [1], sata1(prsnt) [1], pcie0(rstout), sd0(d3), ua3(txd) +mpp55 55 gpio, ua1(cts), spi1(cs1), sd0(d0), ua1(rxd), ua3(rxd) +mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd) +mpp57 57 gpio, spi1(sck), sd0(clk), ua1(txd) +mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd) +mpp59 59 gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd0(d2) + +[1]: only available on 88F6925/88F6928 +[2]: only available on 88F6928 diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-7k-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,armada-7k-pinctrl.yaml new file mode 100644 index 000000000..88910ad17 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-7k-pinctrl.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,armada-7k-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 7K/8K pin controller + +maintainers: + - Gregory Clement <gregory.clement@bootlin.com> + - Miquel Raynal <miquel.raynal@bootlin.com> + +properties: + compatible: + enum: + - marvell,armada-7k-pinctrl + - marvell,armada-8k-cpm-pinctrl + - marvell,armada-8k-cps-pinctrl + - marvell,cp115-standalone-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins(-.+)?$': + type: object + additionalProperties: false + + properties: + marvell,function: + $ref: /schemas/types.yaml#/definitions/string + description: + Indicates the function to select. + enum: [ + au, dev, ge, ge0, ge1, gpio, i2c0, i2c1, led, link, mii, mss_gpio0, + mss_gpio1, mss_gpio2, mss_gpio3, mss_gpio4, mss_gpio5, mss_gpio6, + mss_gpio7, mss_i2c, mss_spi, mss_uart, nf, pcie, pcie0, pcie1, pcie2, + ptp, rei, sata0, sata1, sdio, sdio_cd, sdio_wp, sei, spi0, spi1, + synce1, synce2, tdm, uart0, uart1, uart2, uart3, wakeup, xg + ] + + marvell,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Array of MPP pins to be used for the given function. + minItems: 1 + maxItems: 63 + items: + pattern: '^mpp([1-5]?[0-9]|6[0-2])$' + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "marvell,armada-7k-pinctrl"; + + nand_pins: nand-pins { + marvell,pins = + "mpp15", "mpp16", "mpp17", "mpp18", + "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27"; + marvell,function = "dev"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt new file mode 100644 index 000000000..97aef67ee --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt @@ -0,0 +1,46 @@ +* Marvell 98dx3236 pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage + +Required properties: +- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl" +- reg: register specifier of MPP registers + +This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants + +name pins functions +================================================================================ +mpp0 0 gpo, spi0(mosi), dev(ad8) +mpp1 1 gpio, spi0(miso), dev(ad9) +mpp2 2 gpo, spi0(sck), dev(ad10) +mpp3 3 gpio, spi0(cs0), dev(ad11) +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0) +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs) +mpp6 6 gpo, sd0(clk), dev(a2) +mpp7 7 gpio, sd0(d0), dev(ale0) +mpp8 8 gpio, sd0(d1), dev(ale1) +mpp9 9 gpio, sd0(d2), dev(ready0) +mpp10 10 gpio, sd0(d3), dev(ad12) +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13) +mpp12 12 gpo, uart1(txd), uart0(rts), dev(ad14) +mpp13 13 gpio, intr(out), dev(ad15) +mpp14 14 gpio, i2c0(sck) +mpp15 15 gpio, i2c0(sda) +mpp16 16 gpo, dev(oe) +mpp17 17 gpo, dev(clkout) +mpp18 18 gpio, uart1(txd) +mpp19 19 gpio, uart1(rxd), dev(rb) +mpp20 20 gpo, dev(we0) +mpp21 21 gpo, dev(ad0) +mpp22 22 gpo, dev(ad1) +mpp23 23 gpo, dev(ad2) +mpp24 24 gpo, dev(ad3) +mpp25 25 gpo, dev(ad4) +mpp26 26 gpo, dev(ad5) +mpp27 27 gpo, dev(ad6) +mpp28 28 gpo, dev(ad7) +mpp29 29 gpo, dev(a0) +mpp30 30 gpo, dev(a1) +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1) +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt new file mode 100644 index 000000000..76da7222f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt @@ -0,0 +1,99 @@ +* Marvell Armada XP SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", + "marvell,mv78460-pinctrl" +- reg: register specifier of MPP registers + +This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460. + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +* Marvell Armada XP (all variants) + +name pins functions +================================================================================ +mpp0 0 gpio, ge0(txclkout), lcd(d0) +mpp1 1 gpio, ge0(txd0), lcd(d1) +mpp2 2 gpio, ge0(txd1), lcd(d2) +mpp3 3 gpio, ge0(txd2), lcd(d3) +mpp4 4 gpio, ge0(txd3), lcd(d4) +mpp5 5 gpio, ge0(txctl), lcd(d5) +mpp6 6 gpio, ge0(rxd0), lcd(d6) +mpp7 7 gpio, ge0(rxd1), lcd(d7) +mpp8 8 gpio, ge0(rxd2), lcd(d8) +mpp9 9 gpio, ge0(rxd3), lcd(d9) +mpp10 10 gpio, ge0(rxctl), lcd(d10) +mpp11 11 gpio, ge0(rxclk), lcd(d11) +mpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) +mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13) +mpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15) +mpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) +mpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16) +mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17) +mpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) +mpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) +mpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) +mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat) +mpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) +mpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) +mpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) +mpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) +mpp26 26 gpio, lcd(clk), tdm(fsync) +mpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) +mpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) +mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) +mpp30 30 gpio, tdm(int1), sd0(clk) +mpp31 31 gpio, tdm(int2), sd0(cmd) +mpp32 32 gpio, tdm(int3), sd0(d0) +mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) +mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) +mpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) +mpp36 36 gpio, spi0(mosi) +mpp37 37 gpio, spi0(miso) +mpp38 38 gpio, spi0(sck) +mpp39 39 gpio, spi0(cs0) +mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), + spi1(cs1) +mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), + pcie(clkreq1), spi1(cs2) +mpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) +mpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), + spi1(cs3) +mpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), + dram(bat), spi1(cs4) +mpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), + spi1(cs5), dram(vttctrl) +mpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), + spi1(cs6) +mpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), + ref(clkout), spi1(cs7) +mpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb) + +* Marvell Armada XP (mv78260 and mv78460 only) + +name pins functions +================================================================================ +mpp49 49 gpio, dev(we3) +mpp50 50 gpio, dev(we2) +mpp51 51 gpio, dev(ad16) +mpp52 52 gpio, dev(ad17) +mpp53 53 gpio, dev(ad18) +mpp54 54 gpio, dev(ad19) +mpp55 55 gpio, dev(ad20) +mpp56 56 gpio, dev(ad21) +mpp57 57 gpio, dev(ad22) +mpp58 58 gpio, dev(ad23) +mpp59 59 gpio, dev(ad24) +mpp60 60 gpio, dev(ad25) +mpp61 61 gpio, dev(ad26) +mpp62 62 gpio, dev(ad27) +mpp63 63 gpio, dev(ad28) +mpp64 64 gpio, dev(ad29) +mpp65 65 gpio, dev(ad30) +mpp66 66 gpio, dev(ad31) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml new file mode 100644 index 000000000..727da7fb4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,armada3710-xb-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 37xx SoC pin and gpio controller + +maintainers: + - Gregory CLEMENT <gregory.clement@bootlin.com> + - Marek Behún <kabel@kernel.org> + - Miquel Raynal <miquel.raynal@bootlin.com> + +description: > + Each Armada 37xx SoC come with two pin and gpio controller one for the south + bridge and the other for the north bridge. + + Inside this set of register the gpio latch allows exposing some configuration + of the SoC and especially the clock frequency of the xtal. Hence, this node is + a represent as syscon allowing sharing the register between multiple hardware + block. + +properties: + compatible: + items: + - enum: + - marvell,armada3710-sb-pinctrl + - marvell,armada3710-nb-pinctrl + - const: syscon + - const: simple-mfd + + reg: + items: + - description: pinctrl and GPIO controller registers + - description: interrupt controller registers + + gpio: + description: GPIO controller subnode + type: object + additionalProperties: false + + properties: + '#gpio-cells': + const: 2 + + gpio-controller: true + + gpio-ranges: + description: Range of pins managed by the GPIO controller + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + interrupts: + description: List of interrupt specifiers for the GPIO controller + + required: + - '#gpio-cells' + - gpio-ranges + - gpio-controller + - '#interrupt-cells' + - interrupt-controller + - interrupts + + xtal-clk: + type: object + additionalProperties: false + + properties: + compatible: + const: marvell,armada-3700-xtal-clock + + '#clock-cells': + const: 0 + + clock-output-names: true + +patternProperties: + '-pins$': + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + items: + enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1, + pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk, + ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, + smi, spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2, + usb2_drvvbus1, usb32_drvvbus0 ] + + function: + enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire, + pcie, pmic, ptp, pwm, sdio, smi, spi, uart ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl_sb: pinctrl@18800 { + compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; + reg = <0x18800 0x100>, <0x18C00 0x20>; + + gpio { + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + interrupts = + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml new file mode 100644 index 000000000..6ace3bf54 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,berlin2-soc-pinctrl.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/marvell,berlin2-soc-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Berlin pin-controller driver + +maintainers: + - Antoine Tenart <atenart@kernel.org> + - Jisheng Zhang <jszhang@kernel.org> + +description: > + Pin control registers are part of both chip controller and system controller + register sets. Pin controller nodes should be a sub-node of either the chip + controller or system controller node. The pins controlled are organized in + groups, so no actual pin information is needed. + + A pin-controller node should contain subnodes representing the pin group + configurations, one per function. Each subnode has the group name and the + muxing function used. + + Be aware the Marvell Berlin datasheets use the keyword 'mode' for what is + called a 'function' in the pin-controller subsystem. + +properties: + compatible: + items: + - enum: + - marvell,berlin2-soc-pinctrl + - marvell,berlin2-system-pinctrl + - marvell,berlin2cd-soc-pinctrl + - marvell,berlin2cd-system-pinctrl + - marvell,berlin2q-soc-pinctrl + - marvell,berlin2q-system-pinctrl + - marvell,berlin4ct-avio-pinctrl + - marvell,berlin4ct-soc-pinctrl + - marvell,berlin4ct-system-pinctrl + - syna,as370-soc-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + description: Pin group configuration subnodes. + type: object + $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + groups: + description: List of pin group names. + $ref: /schemas/types.yaml#/definitions/string-array + + function: + description: Function used to mux the group. + $ref: /schemas/types.yaml#/definitions/string + + required: + - groups + - function + +allOf: + - if: + properties: + compatible: + contains: + enum: + - marvell,berlin4ct-avio-pinctrl + - marvell,berlin4ct-soc-pinctrl + - marvell,berlin4ct-system-pinctrl + - syna,as370-soc-pinctrl + then: + required: + - reg + +examples: + - | + pinctrl { + compatible = "marvell,berlin2q-system-pinctrl"; + + uart0-pmux { + groups = "GSM12"; + function = "uart0"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt new file mode 100644 index 000000000..cf52477cc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt @@ -0,0 +1,90 @@ +* Marvell Dove SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,dove-pinctrl" +- clocks: (optional) phandle of pdma clock +- reg: register specifiers of MPP, MPP4, and PMU MPP registers + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. +Note: pmu* also allows for Power Management functions listed below + +name pins functions +================================================================================ +mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu* +mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu* +mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt), + uart1(rts), pmu* +mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act), + uart1(cts), lcd-spi(cs1), pmu* +mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu* +mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu* +mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu* +mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu* +mpp8 8 gpio, pmu, watchdog(rstout), pmu* +mpp9 9 gpio, pmu, pex1(clkreq), pmu* +mpp10 10 gpio, pmu, ssp(sclk), pmu* +mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl), + sdio1(ledctrl), pex0(clkreq), pmu* +mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), + sata(act), pmu* +mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp), + ssp(extclk), pmu* +mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu* +mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu* +mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1) +mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda), + ac97-1(sysclko) +mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm) +mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck) +mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso), + ac97(sysclko) +mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0), + uart1(cts), ssp(sfrm) +mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi), + lcd-spi(mosi), uart1(cts), ssp(txd) +mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck), + lcd-spi(sck), ssp(sclk) +mpp_camera 24-39 gpio, camera +mpp_sdio0 40-45 gpio, sdio0 +mpp_sdio1 46-51 gpio, sdio1 +mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp, + ssp/twsi +mpp_spi0 58-61 gpio, spi0 +mpp_uart1 62-63 gpio, uart1 +mpp_nand 64-71 gpo, nand +audio0 - i2s, ac97 +twsi - none, opt1, opt2, opt3 + +Power Management functions (pmu*): +pmu-nc Pin not driven by any PM function +pmu-low Pin driven low (0) +pmu-high Pin driven high (1) +pmic(sdi) Pin is used for PMIC SDI +cpu-pwr-down Pin is used for CPU_PWRDWN +standby-pwr-down Pin is used for STBY_PWRDWN +core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only) +cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only) +bat-fault Pin is used for BATTERY_FAULT +ext0-wakeup Pin is used for EXT0_WU +ext1-wakeup Pin is used for EXT0_WU +ext2-wakeup Pin is used for EXT0_WU +pmu-blink Pin is used for blink function + +Notes: +* group "mpp_audio1" allows the following functions and gpio pins: + - gpio : gpio on pins 52-57 + - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios + - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57 + - spdifo : spdifo on pin 57, gpio on pins 52-55 + - twsi : twsi on pins 56,57, gpio on pins 52-55 + - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios + - ssp : ssp on pins 52-55, gpio on pins 56,57 + - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios +* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated + audio0 pins. +* group "twsi" internally muxes twsi controller to the dedicated or option pins. diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt new file mode 100644 index 000000000..2932f171e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt @@ -0,0 +1,359 @@ +* Marvell Kirkwood SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,88f6180-pinctrl", + "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl", + "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl", + "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl" +- reg: register specifier of MPP registers + +This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x. +It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs. + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +* Marvell Kirkwood 88f6180 + +name pins functions +================================================================================ +mpp0 0 gpio, nand(io2), spi(cs) +mpp1 1 gpo, nand(io3), spi(mosi) +mpp2 2 gpo, nand(io4), spi(sck) +mpp3 3 gpo, nand(io5), spi(miso) +mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) +mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig) +mpp6 6 sysrst(out), spi(mosi), ptp(trig) +mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) +mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), + mii(col) +mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), + mii(crs) +mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig) +mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), + ptp-2(trig) +mpp12 12 gpo, sdio(clk) +mpp13 13 gpio, sdio(cmd), uart1(txd) +mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col) +mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd) +mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) +mpp17 17 gpio, sdio(d3) +mpp18 18 gpo, nand(io0) +mpp19 19 gpo, nand(io1) +mpp35 35 gpio, mii(rxerr) +mpp36 36 gpio, audio(spdifi) +mpp37 37 gpio, audio(spdifo) +mpp38 38 gpio, audio(rmclk) +mpp39 39 gpio, audio(bclk) +mpp40 40 gpio, audio(sdo) +mpp41 41 gpio, audio(lrclk) +mpp42 42 gpio, audio(mclk) +mpp43 43 gpio, audio(sdi) +mpp44 44 gpio, audio(extclk) + +* Marvell Kirkwood 88f6190 + +name pins functions +================================================================================ +mpp0 0 gpio, nand(io2), spi(cs) +mpp1 1 gpo, nand(io3), spi(mosi) +mpp2 2 gpo, nand(io4), spi(sck) +mpp3 3 gpo, nand(io5), spi(miso) +mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk) +mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) +mpp6 6 sysrst(out), spi(mosi), ptp(trig) +mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) +mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), + mii(col), mii-1(rxerr) +mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), + mii(crs), sata0(prsnt) +mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig) +mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), + ptp-2(trig), sata0(act) +mpp12 12 gpo, sdio(clk) +mpp13 13 gpio, sdio(cmd), uart1(txd) +mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col) +mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) +mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs) +mpp17 17 gpio, sdio(d3), sata0(prsnt) +mpp18 18 gpo, nand(io0) +mpp19 19 gpo, nand(io1) +mpp20 20 gpio, ge1(txd0) +mpp21 21 gpio, ge1(txd1), sata0(act) +mpp22 22 gpio, ge1(txd2) +mpp23 23 gpio, ge1(txd3), sata0(prsnt) +mpp24 24 gpio, ge1(rxd0) +mpp25 25 gpio, ge1(rxd1) +mpp26 26 gpio, ge1(rxd2) +mpp27 27 gpio, ge1(rxd3) +mpp28 28 gpio, ge1(col) +mpp29 29 gpio, ge1(txclk) +mpp30 30 gpio, ge1(rxclk) +mpp31 31 gpio, ge1(rxclk) +mpp32 32 gpio, ge1(txclko) +mpp33 33 gpo, ge1(txclk) +mpp34 34 gpio, ge1(txen) +mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr) + +* Marvell Kirkwood 88f6192 + +name pins functions +================================================================================ +mpp0 0 gpio, nand(io2), spi(cs) +mpp1 1 gpo, nand(io3), spi(mosi) +mpp2 2 gpo, nand(io4), spi(sck) +mpp3 3 gpo, nand(io5), spi(miso) +mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act) +mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) +mpp6 6 sysrst(out), spi(mosi), ptp(trig) +mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) +mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), + mii(col), mii-1(rxerr), sata1(prsnt) +mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), + mii(crs), sata0(prsnt) +mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act) +mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), + ptp-2(trig), sata0(act) +mpp12 12 gpo, sdio(clk) +mpp13 13 gpio, sdio(cmd), uart1(txd) +mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt) +mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) +mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), + sata1(act) +mpp17 17 gpio, sdio(d3), sata0(prsnt) +mpp18 18 gpo, nand(io0) +mpp19 19 gpo, nand(io1) +mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), + sata1(act) +mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), + audio(spdifo) +mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), + sata1(prsnt) +mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), + audio(bclk) +mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo) +mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk) +mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk) +mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi) +mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk) +mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst) +mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk) +mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs) +mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx) +mpp33 33 gpo, ge1(txclk), tdm(drx) +mpp34 34 gpio, ge1(txen), tdm(spi-cs1) +mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql) + +* Marvell Kirkwood 88f6281 + +name pins functions +================================================================================ +mpp0 0 gpio, nand(io2), spi(cs) +mpp1 1 gpo, nand(io3), spi(mosi) +mpp2 2 gpo, nand(io4), spi(sck) +mpp3 3 gpo, nand(io5), spi(miso) +mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act) +mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig), sata0(act) +mpp6 6 sysrst(out), spi(mosi), ptp(trig) +mpp7 7 gpo, pex(rsto), spi(cs), ptp(trig) +mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk), + mii(col), mii-1(rxerr), sata1(prsnt) +mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq), + mii(crs), sata0(prsnt) +mpp10 10 gpo, spi(sck), uart0(txd), ptp(trig), sata1(act) +mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq), + ptp-2(trig), sata0(act) +mpp12 12 gpio, sdio(clk) +mpp13 13 gpio, sdio(cmd), uart1(txd) +mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt) +mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act) +mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), + sata1(act) +mpp17 17 gpio, sdio(d3), sata0(prsnt) +mpp18 18 gpo, nand(io0) +mpp19 19 gpo, nand(io1) +mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), + sata1(act) +mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), + audio(spdifo) +mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), + sata1(prsnt) +mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), + audio(bclk) +mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo) +mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk) +mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk) +mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi) +mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk) +mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst) +mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk) +mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs) +mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx) +mpp33 33 gpo, ge1(txclk), tdm(drx) +mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act) +mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql) +mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi) +mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo) +mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk) +mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk) +mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo) +mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk) +mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk) +mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi) +mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk) +mpp45 45 gpio, ts(mp9), tdm(pclk) +mpp46 46 gpio, ts(mp10), tdm(fs) +mpp47 47 gpio, ts(mp11), tdm(drx) +mpp48 48 gpio, ts(mp12), tdm(dtx) +mpp49 49 gpio, ts(mp9), tdm(rx0ql), ptp(clk) + +* Marvell Kirkwood 88f6282 + +name pins functions +================================================================================ +mpp0 0 gpio, nand(io2), spi(cs) +mpp1 1 gpo, nand(io3), spi(mosi) +mpp2 2 gpo, nand(io4), spi(sck) +mpp3 3 gpo, nand(io5), spi(miso) +mpp4 4 gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync) +mpp5 5 gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync) +mpp6 6 sysrst(out), spi(mosi) +mpp7 7 gpo, spi(cs), lcd(pwm) +mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col), + mii-1(rxerr), sata1(prsnt) +mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs), + sata0(prsnt) +mpp10 10 gpo, spi(sck), uart0(txd), sata1(act) +mpp11 11 gpio, spi(miso), uart0(rxd), sata0(act) +mpp12 12 gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda) +mpp13 13 gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm) +mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt), + audio(spdifi), audio-1(sdi) +mpp15 15 gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act), + spi(cs) +mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs), + sata1(act), lcd(extclk) +mpp17 17 gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck) +mpp18 18 gpo, nand(io0), pex(clkreq) +mpp19 19 gpo, nand(io1) +mpp20 20 gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi), + sata1(act), lcd(d0) +mpp21 21 gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql), + audio(spdifo), lcd(d1) +mpp22 22 gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk), + sata1(prsnt), lcd(d2) +mpp23 23 gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql), + audio(bclk), lcd(d3) +mpp24 24 gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo), + lcd(d4) +mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk), + lcd(d5) +mpp26 26 gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk), + lcd(d6) +mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi), + lcd(d7) +mpp28 28 gpio, ge1(col), ts(mp8), tdm(int), audio(extclk), + lcd(d8) +mpp29 29 gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9) +mpp30 30 gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10) +mpp31 31 gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11) +mpp32 32 gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12) +mpp33 33 gpo, ge1(txclk), tdm(drx), lcd(d13) +mpp34 34 gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14) +mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql), + lcd(d15) +mpp36 36 gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda) +mpp37 37 gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck) +mpp38 38 gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18) +mpp39 39 gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19) +mpp40 40 gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20) +mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21) +mpp42 42 gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22) +mpp43 43 gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23) +mpp44 44 gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk) +mpp45 45 gpio, ts(mp9), tdm(pclk), lcd(e) +mpp46 46 gpio, ts(mp10), tdm(fs), lcd(hsync) +mpp47 47 gpio, ts(mp11), tdm(drx), lcd(vsync) +mpp48 48 gpio, ts(mp12), tdm(dtx), lcd(d16) +mpp49 49 gpo, tdm(rx0ql), pex(clkreq), lcd(d17) + +* Marvell Bobcat 98dx4122 + +name pins functions +================================================================================ +mpp0 0 gpio, nand(io2), spi(cs) +mpp1 1 gpo, nand(io3), spi(mosi) +mpp2 2 gpo, nand(io4), spi(sck) +mpp3 3 gpo, nand(io5), spi(miso) +mpp4 4 gpio, nand(io6), uart0(rxd) +mpp5 5 gpo, nand(io7), uart0(txd) +mpp6 6 sysrst(out), spi(mosi) +mpp7 7 gpo, pex(rsto), spi(cs) +mpp8 8 gpio, twsi0(sda), uart0(rts), uart1(rts) +mpp9 9 gpio, twsi(sck), uart0(cts), uart1(cts) +mpp10 10 gpo, spi(sck), uart0(txd) +mpp11 11 gpio, spi(miso), uart0(rxd) +mpp13 13 gpio, uart1(txd) +mpp14 14 gpio, uart1(rxd) +mpp15 15 gpio, uart0(rts) +mpp16 16 gpio, uart0(cts) +mpp18 18 gpo, nand(io0) +mpp19 19 gpo, nand(io1) +mpp34 34 gpio +mpp35 35 gpio +mpp36 36 gpio +mpp37 37 gpio +mpp38 38 gpio +mpp39 39 gpio +mpp40 40 gpio +mpp41 41 gpio +mpp42 42 gpio +mpp43 43 gpio +mpp44 44 gpio +mpp45 45 gpio +mpp49 49 gpio + +* Marvell Poncat2 98dx1135 + +name pins functions +================================================================================ + +mpp0 0 gpio, nand(io2), spi(cs) +mpp1 1 gpo, nand(io3), spi(mosi) +mpp2 2 gpo, nand(io4), spi(sck) +mpp3 3 gpo, nand(io5), spi(miso) +mpp4 4 gpio, nand(io6), uart0(rxd) +mpp5 5 gpo, nand(io7), uart0(txd) +mpp6 6 sysrst(out) +mpp7 7 gpo, spi(cs) +mpp8 8 gpio, twsi0(sda), uart1(rts) +mpp9 9 gpio, twsi(sck), uart1(cts) +mpp10 10 gpo, uart0(txd) +mpp11 11 gpio, uart0(rxd) +mpp13 13 gpio, uart1(txd) +mpp14 14 gpio, uart1(rxd) +mpp15 15 gpio, uart0(rts) +mpp16 16 gpio, uart0(cts) +mpp17 17 gpio, nand(cle) +mpp18 18 gpo, nand(io0) +mpp19 19 gpo, nand(io1) +mpp20 20 gpio +mpp21 21 gpio +mpp22 22 gpio +mpp23 23 gpio +mpp24 24 gpio +mpp25 25 gpio +mpp26 26 gpio +mpp27 27 gpio +mpp28 28 gpio, nand(ren) +mpp29 29 gpio, nand(wen) +mpp30 30 gpio +mpp31 31 gpio +mpp32 32 gpio +mpp33 33 gpio +mpp34 34 gpio, nand(ale) +mpp35 35 gpio, nand(cen) diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt new file mode 100644 index 000000000..0c09f4eb2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt @@ -0,0 +1,46 @@ +* Marvell SoC pinctrl core driver for mpp + +The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins +(mpp) to a specific function. For each SoC family there is a SoC specific +driver using this core driver. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +A Marvell SoC pin configuration node is a node of a group of pins which can +be used for a specific device or function. Each node requires one or more +mpp pins or group of pins and a mpp function common to all pins. + +Required properties for pinctrl driver: +- compatible: "marvell,<soc>-pinctrl" + Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs. + +Required properties for pin configuration node: +- marvell,pins: string array of mpp pins or group of pins to be muxed. +- marvell,function: string representing a function to mux to for all + marvell,pins given in this pin configuration node. The function has to be + common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for + valid pin/pin group names and available function names for each SoC. + +Examples: + +uart1: serial@12100 { + compatible = "ns16550a"; + reg = <0x12100 0x100>; + reg-shift = <2>; + interrupts = <7>; + + pinctrl-0 = <&pmx_uart1_sw>; + pinctrl-names = "default"; +}; + +pinctrl: pinctrl@d0200 { + compatible = "marvell,dove-pinctrl"; + reg = <0xd0200 0x14>, <0xd0440 0x04>, <0xd802c 0x08>; + + pmx_uart1_sw: pmx-uart1-sw { + marvell,pins = "mpp_uart1"; + marvell,function = "uart1"; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt new file mode 100644 index 000000000..ec8aa3c69 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,orion-pinctrl.txt @@ -0,0 +1,93 @@ +* Marvell Orion SoC pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage. + +Required properties: +- compatible: "marvell,88f5181-pinctrl", + "marvell,88f5181l-pinctrl", + "marvell,88f5182-pinctrl", + "marvell,88f5281-pinctrl" + +- reg: two register areas, the first one describing the first two + contiguous MPP registers, and the second one describing the single + final MPP register, separated from the previous one. + +Available mpp pins/groups and functions: +Note: brackets (x) are not part of the mpp name for marvell,function and given +only for more detailed description in this document. + +* Marvell Orion 88f5181l + +name pins functions +================================================================================ +mpp0 0 pcie(rstout), pci(req2), gpio +mpp1 1 gpio, pci(gnt2) +mpp2 2 gpio, pci(req3), pci-1(pme) +mpp3 3 gpio, pci(gnt3) +mpp4 4 gpio, pci(req4) +mpp5 5 gpio, pci(gnt4) +mpp6 6 gpio, pci(req5), pci-1(clk) +mpp7 7 gpio, pci(gnt5), pci-1(clk) +mpp8 8 gpio, ge(col) +mpp9 9 gpio, ge(rxerr) +mpp10 10 gpio, ge(crs) +mpp11 11 gpio, ge(txerr) +mpp12 12 gpio, ge(txd4) +mpp13 13 gpio, ge(txd5) +mpp14 14 gpio, ge(txd6) +mpp15 15 gpio, ge(txd7) +mpp16 16 ge(rxd4) +mpp17 17 ge(rxd5) +mpp18 18 ge(rxd6) +mpp19 19 ge(rxd7) + +* Marvell Orion 88f5182 + +name pins functions +================================================================================ +mpp0 0 pcie(rstout), pci(req2), gpio +mpp1 1 gpio, pci(gnt2) +mpp2 2 gpio, pci(req3), pci-1(pme) +mpp3 3 gpio, pci(gnt3) +mpp4 4 gpio, pci(req4), bootnand(re), sata0(prsnt) +mpp5 5 gpio, pci(gnt4), bootnand(we), sata1(prsnt) +mpp6 6 gpio, pci(req5), nand(re0), sata0(act) +mpp7 7 gpio, pci(gnt5), nand(we0), sata1(act) +mpp8 8 gpio, ge(col) +mpp9 9 gpio, ge(rxerr) +mpp10 10 gpio, ge(crs) +mpp11 11 gpio, ge(txerr) +mpp12 12 gpio, ge(txd4), nand(re1), sata0(ledprsnt) +mpp13 13 gpio, ge(txd5), nand(we1), sata1(ledprsnt) +mpp14 14 gpio, ge(txd6), nand(re2), sata0(ledact) +mpp15 15 gpio, ge(txd7), nand(we2), sata1(ledact) +mpp16 16 uart1(rxd), ge(rxd4), gpio +mpp17 17 uart1(txd), ge(rxd5), gpio +mpp18 18 uart1(cts), ge(rxd6), gpio +mpp19 19 uart1(rts), ge(rxd7), gpio + +* Marvell Orion 88f5281 + +name pins functions +================================================================================ +mpp0 0 pcie(rstout), pci(req2), gpio +mpp1 1 gpio, pci(gnt2) +mpp2 2 gpio, pci(req3), pci(pme) +mpp3 3 gpio, pci(gnt3) +mpp4 4 gpio, pci(req4), bootnand(re) +mpp5 5 gpio, pci(gnt4), bootnand(we) +mpp6 6 gpio, pci(req5), nand(re0) +mpp7 7 gpio, pci(gnt5), nand(we0) +mpp8 8 gpio, ge(col) +mpp9 9 gpio, ge(rxerr) +mpp10 10 gpio, ge(crs) +mpp11 11 gpio, ge(txerr) +mpp12 12 gpio, ge(txd4), nand(re1) +mpp13 13 gpio, ge(txd5), nand(we1) +mpp14 14 gpio, ge(txd6), nand(re2) +mpp15 15 gpio, ge(txd7), nand(we2) +mpp16 16 uart1(rxd), ge(rxd4) +mpp17 17 uart1(txd), ge(rxd5) +mpp18 18 uart1(cts), ge(rxd6) +mpp19 19 uart1(rts), ge(rxd7) diff --git a/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml new file mode 100644 index 000000000..b3ea36474 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/maxim,max77620-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pinmux controller function for Maxim MAX77620 Power management IC + +maintainers: + - Svyatoslav Ryhel <clamor95@gmail.com> + +description: + Device has 8 GPIO pins which can be configured as GPIO as well as the + special IO functions. + +allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + +patternProperties: + "^(pin|gpio).": + type: object + additionalProperties: false + + properties: + pins: + items: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7 ] + + function: + items: + enum: [ gpio, lpm-control-in, fps-out, 32k-out1, sd0-dvs-in, sd1-dvs-in, + reference-out ] + + drive-push-pull: true + drive-open-drain: true + bias-pull-up: true + bias-pull-down: true + + maxim,active-fps-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + FPS source for the GPIOs to get enabled/disabled when system is in + active state. Valid values are: + - MAX77620_FPS_SRC_0: FPS source is FPS0. + - MAX77620_FPS_SRC_1: FPS source is FPS1 + - MAX77620_FPS_SRC_2: FPS source is FPS2 + - MAX77620_FPS_SRC_NONE: GPIO is not controlled by FPS events and + it gets enabled/disabled by register access. + Absence of this property will leave the FPS configuration register + for that GPIO to default configuration. + + maxim,active-fps-power-up-slot: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Sequencing event slot number on which the GPIO get enabled when + master FPS input event set to HIGH. This is applicable if FPS source + is selected as FPS0, FPS1 or FPS2. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + maxim,active-fps-power-down-slot: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Sequencing event slot number on which the GPIO get disabled when + master FPS input event set to LOW. This is applicable if FPS source + is selected as FPS0, FPS1 or FPS2. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + maxim,suspend-fps-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This is same as property "maxim,active-fps-source" but value get + configured when system enters in to suspend state. + + maxim,suspend-fps-power-up-slot: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This is same as property "maxim,active-fps-power-up-slot" but this + value get configured into FPS configuration register when system + enters into suspend. This is applicable if suspend state FPS source + is selected as FPS0, FPS1 or FPS2. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + maxim,suspend-fps-power-down-slot: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + This is same as property "maxim,active-fps-power-down-slot" but this + value get configured into FPS configuration register when system + enters into suspend. This is applicable if suspend state FPS source + is selected as FPS0, FPS1 or FPS2. + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + required: + - pins + +additionalProperties: false + +# see maxim,max77620.yaml for an example diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml new file mode 100644 index 000000000..aa71398cf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -0,0 +1,181 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT65xx Pin Controller + +maintainers: + - Sean Wang <sean.wang@kernel.org> + +description: + The MediaTek's MT65xx Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt2701-pinctrl + - mediatek,mt2712-pinctrl + - mediatek,mt6397-pinctrl + - mediatek,mt7623-pinctrl + - mediatek,mt8127-pinctrl + - mediatek,mt8135-pinctrl + - mediatek,mt8167-pinctrl + - mediatek,mt8173-pinctrl + - mediatek,mt8516-pinctrl + + reg: + maxItems: 1 + + pins-are-numbered: + $ref: /schemas/types.yaml#/definitions/flag + description: + Specify the subnodes are using numbered pinmux to specify pins. (UNUSED) + deprecated: true + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-line-names: true + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: + Should be phandles of the syscfg node. + + interrupt-controller: true + + interrupts: + minItems: 1 + maxItems: 3 + + "#interrupt-cells": + const: 2 + +required: + - compatible + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +patternProperties: + 'pins$': + type: object + additionalProperties: false + patternProperties: + '(^pins|pins?$)': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + description: + Besides generic pinconfig options, it can be used as the pull up + settings for 2 pull resistors, R0 and R1. User can configure those + special pins. Some macros have been defined for this usage, such + as MTK_PUPD_SET_R1R0_00. See dt-bindings/pinctrl/mt65xx.h for + valid arguments. + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + description: + Can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, + etc. See dt-bindings/pinctrl/mt65xx.h for valid arguments. + + required: + - pinmux + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt8135-pinfunc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@1c20800 { + compatible = "mediatek,mt8135-pinctrl"; + reg = <0 0x1000B000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + + i2c0_pins_a: i2c0-pins { + pins1 { + pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>, + <MT8135_PIN_101_SCL0__FUNC_SCL0>; + bias-disable; + }; + }; + + i2c1_pins_a: i2c1-pins { + pins { + pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>, + <MT8135_PIN_196_SCL1__FUNC_SCL1>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + i2c2_pins_a: i2c2-pins { + pins1 { + pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>; + bias-pull-down; + }; + + pins2 { + pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>; + bias-pull-up; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml new file mode 100644 index 000000000..f4bab7a13 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -0,0 +1,248 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6779 Pin Controller + +maintainers: + - Andy Teng <andy.teng@mediatek.com> + - Sean Wang <sean.wang@kernel.org> + +description: + The MediaTek pin controller on MT6779 is used to control pin functions, pull + up/down resistance and drive strength options. + +properties: + compatible: + enum: + - mediatek,mt6779-pinctrl + - mediatek,mt6797-pinctrl + + reg: + description: Physical addresses for GPIO base(s) and EINT registers. + + reg-names: true + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: + GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + description: + Specifies the summary IRQ. + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + const: mediatek,mt6779-pinctrl + then: + properties: + reg: + minItems: 9 + maxItems: 9 + + reg-names: + items: + - const: gpio + - const: iocfg_rm + - const: iocfg_br + - const: iocfg_lm + - const: iocfg_lb + - const: iocfg_rt + - const: iocfg_lt + - const: iocfg_tl + - const: eint + - if: + properties: + compatible: + contains: + const: mediatek,mt6797-pinctrl + then: + properties: + reg: + minItems: 5 + maxItems: 5 + + reg-names: + items: + - const: gpio + - const: iocfgl + - const: iocfgb + - const: iocfgr + - const: iocfgt + - if: + properties: + reg-names: + contains: + const: eint + then: + required: + - interrupts + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-[0-9]*$': + type: object + additionalProperties: false + + patternProperties: + '-pins*$': + type: object + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 8, 12, 16] + + slew-rate: + enum: [0, 1] + + mediatek,pull-up-adv: + description: | + Pull up settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as + below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as + below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pinmux + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt6779-pinfunc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + + mmc0_pins_default: mmc0-0 { + cmd-dat-pins { + pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO167__FUNC_MSDC0_CMD>; + input-enable; + mediatek,pull-up-adv = <1>; + }; + clk-pins { + pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; + mediatek,pull-down-adv = <2>; + }; + rst-pins { + pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; + mediatek,pull-up-adv = <0>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml new file mode 100644 index 000000000..68e91c05f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6795-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6795 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Sean Wang <sean.wang@kernel.org> + +description: + The MediaTek's MT6795 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6795-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: GPIO valid number range. + maxItems: 1 + + reg: + description: + Physical address base for GPIO base and eint registers. + minItems: 2 + + reg-names: + items: + - const: base + - const: eint + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: Interrupt outputs to the system interrupt controller (sysirq). + minItems: 1 + items: + - description: EINT interrupt + - description: EINT event_b interrupt + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + } + }; + /* GPIO45 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO45__FUNC_SDA0>; + } + }; + }; + $ref: pinmux-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt6795 pull down PUPD/R0/R1 type define value. + description: + For normal pull down type, it is not necessary to specify R1R0 + values; When pull down type is PUPD/R0/R1, adding R1R0 defines + will set different resistance values. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt6795 pull up PUPD/R0/R1 type define value. + description: + For normal pull up type, it is not necessary to specify R1R0 + values; When pull up type is PUPD/R0/R1, adding R1R0 defines will + set different resistance values. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + mediatek,pull-up-adv: + description: | + Pull up settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as + below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as + below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pinmux + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/pinctrl/mt6795-pinfunc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6795-pinctrl"; + reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; + reg-names = "base", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 196>; + interrupt-controller; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + i2c0-pins { + pins-sda-scl { + pinmux = <PINMUX_GPIO45__FUNC_SDA0>, + <PINMUX_GPIO46__FUNC_SCL0>; + }; + }; + + mmc0-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO155__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO156__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO157__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO158__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO159__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO160__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO161__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO162__FUNC_MSDC0_CMD>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-clk { + pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>; + bias-pull-up = <MTK_PUPD_SET_R1R0_10>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml new file mode 100644 index 000000000..8d44194a7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6878-pinctrl.yaml @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6878-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6878 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + - Igor Belwon <igor.belwon@mentallysanemainliners.org> + +description: + The MediaTek MT6878 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6878-pinctrl + + reg: + items: + - description: pin controller base + - description: bl group IO + - description: bm group IO + - description: br group IO + - description: bl1 group IO + - description: br1 group IO + - description: lm group IO + - description: lt group IO + - description: rm group IO + - description: rt group IO + - description: EINT controller E block + - description: EINT controller S block + - description: EINT controller W block + - description: EINT controller C block + + reg-names: + items: + - const: base + - const: bl + - const: bm + - const: br + - const: bl1 + - const: br1 + - const: lm + - const: lt + - const: rm + - const: rt + - const: eint-e + - const: eint-s + - const: eint-w + - const: eint-c + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: + maxItems: 216 + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux are defined as macros in + arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [75000, 5000] + description: Pull down RSEL type resistance values (in ohms) + description: + For normal pull down type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull down type a resistance value (in ohms) can be added. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [10000, 5000, 4000, 3000] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> + #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6878-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11d50000 0x1000>, + <0x11d60000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11eb0000 0x1000>, + <0x11ec0000 0x1000>, + <0x11ce0000 0x1000>, + <0x11de0000 0x1000>, + <0x11e60000 0x1000>, + <0x1c01e000 0x1000>; + reg-names = "base", "bl", "bm", "br", "bl1", "br1", + "lm", "lt", "rm", "rt", "eint-e", "eint-s", + "eint-w", "eint-c"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + gpio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + bias-pull-up = <4000>; + drive-strength = <6>; + }; + }; + + i2c0-pins { + pins-bus { + pinmux = <PINMUX_GPIO99__FUNC_SCL0>, + <PINMUX_GPIO100__FUNC_SDA0>; + bias-pull-down = <75000>; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml new file mode 100644 index 000000000..fa189fe00 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6893-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6893 Pin Controller + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +description: + The MediaTek's MT6893 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt6893-pinctrl + + reg: + items: + - description: pin controller base + - description: rm group IO + - description: bm group IO + - description: lm group IO + - description: lb group IO + - description: rt group IO + - description: lt group IO + - description: tm group IO + - description: External Interrupt (EINT) controller base + + reg-names: + items: + - const: base + - const: rm + - const: bm + - const: lm + - const: lb + - const: rt + - const: lt + - const: tm + - const: eint + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux are defined as macros in + arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [75000, 5000] + description: Pull down RSEL type resistance values (in ohms) + description: + For normal pull down type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull down type a resistance value (in ohms) can be added. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [10000, 5000, 4000, 3000] + description: Pull up RSEL type resistance values (in ohms) + description: + For normal pull up type there is no need to specify a resistance + value, hence this can be specified as a boolean property. + For RSEL pull up type a resistance value (in ohms) can be added. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> + #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6893-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x0200>, + <0x11d10000 0x0200>, + <0x11e20000 0x0200>, + <0x11e70000 0x0200>, + <0x11ea0000 0x0200>, + <0x11f20000 0x0200>, + <0x11f30000 0x0200>, + <0x1100b000 0x1000>; + reg-names = "base", "rm", "bm", "lm", "lb", "rt", + "lt", "tm", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + gpio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + bias-pull-up = <4000>; + drive-strength = <6>; + }; + }; + + i2c0-pins { + pins-bus { + pinmux = <PINMUX_GPIO99__FUNC_SCL0>, + <PINMUX_GPIO100__FUNC_SDA0>; + bias-pull-down = <75000>; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml new file mode 100644 index 000000000..591bc0664 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7620-pinctrl.yaml @@ -0,0 +1,298 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7620 Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + MediaTek MT7620 pin controller for MT7620 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,mt7620-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, + pa, pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, + refclk, rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, + wdt refclk, wdt rst, wled] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: ephy + then: + properties: + groups: + enum: [ephy] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi, + spi refclk, uartf, uartlite, wdt, wled] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: nand + then: + properties: + groups: + enum: [nd_sd] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcie refclk + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcie rst + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: refclk + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: rgmii1 + then: + properties: + groups: + enum: [rgmii1] + + - if: + properties: + function: + const: rgmii2 + then: + properties: + groups: + enum: [rgmii2] + + - if: + properties: + function: + const: sd + then: + properties: + groups: + enum: [nd_sd] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi refclk + then: + properties: + groups: + enum: [spi refclk] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdt refclk + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wdt rst + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wled + then: + properties: + groups: + enum: [wled] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,mt7620-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml new file mode 100644 index 000000000..e568b9c13 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7621-pinctrl.yaml @@ -0,0 +1,261 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7621 Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + MediaTek MT7621 pin controller for MT7621 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,mt7621-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk, + pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi, + uart1, uart2, uart3, wdt refclk, wdt rst] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, + uart1, uart2, uart3, wdt] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: nand1 + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: nand2 + then: + properties: + groups: + enum: [sdhci] + + - if: + properties: + function: + const: pcie refclk + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcie rst + then: + properties: + groups: + enum: [pcie] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: rgmii1 + then: + properties: + groups: + enum: [rgmii1] + + - if: + properties: + function: + const: rgmii2 + then: + properties: + groups: + enum: [rgmii2] + + - if: + properties: + function: + const: sdhci + then: + properties: + groups: + enum: [sdhci] + + - if: + properties: + function: + const: spdif2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: spdif3 + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: uart3 + then: + properties: + groups: + enum: [uart3] + + - if: + properties: + function: + const: wdt refclk + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wdt rst + then: + properties: + groups: + enum: [wdt] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,mt7621-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml new file mode 100644 index 000000000..6b925c509 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -0,0 +1,401 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7622 Pin Controller + +maintainers: + - Sean Wang <sean.wang@kernel.org> + +description: + The MediaTek's MT7622 Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt7622-pinctrl + - mediatek,mt7629-pinctrl + + reg: + maxItems: 2 + + reg-names: + items: + - const: base + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +if: + required: + - interrupt-controller +then: + required: + - reg-names + - interrupts + - "#interrupt-cells" + +patternProperties: + '-pins(-[a-z]+)?$': + type: object + additionalProperties: false + patternProperties: + '^mux(-|$)': + type: object + additionalProperties: false + description: + pinmux configuration nodes. + $ref: /schemas/pinctrl/pinmux-node.yaml + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [antsel, emmc, eth, i2c, i2s, ir, led, flash, pcie, pmic, pwm, + sd, spi, tdm, uart, watchdog, wifi] + + groups: + description: + An array of strings. Each string contains the name of a group. + + drive-strength: + enum: [4, 8, 12, 16] + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: antsel + then: + properties: + groups: + items: + enum: [antsel0, antsel1, antsel2, antsel3, antsel4, antsel5, + antsel6, antsel7, antsel8, antsel9, antsel10, + antsel11, antsel12, antsel13, antsel14, antsel15, + antsel16, antsel17, antsel18, antsel19, antsel20, + antsel21, antsel22, antsel23, antsel24, antsel25, + antsel26, antsel27, antsel28, antsel29] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + items: + enum: [emmc, emmc_rst] + - if: + properties: + function: + const: eth + then: + properties: + groups: + items: + enum: [esw, esw_p0_p1, esw_p2_p3_p4, rgmii_via_esw, + rgmii_via_gmac1, rgmii_via_gmac2, mdc_mdio] + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c0, i2c_0, i2c_1, i2c1_0, i2c1_1, i2c1_2, i2c2_0, + i2c2_1, i2c2_2] + - if: + properties: + function: + const: i2s + then: + properties: + groups: + items: + enum: [i2s_in_mclk_bclk_ws, i2s1_in_data, i2s2_in_data, + i2s3_in_data, i2s4_in_data, i2s_out_mclk_bclk_ws, + i2s1_out_data, i2s2_out_data, i2s3_out_data, + i2s4_out_data] + - if: + properties: + function: + const: ir + then: + properties: + groups: + enum: [ir_0_tx, ir_1_tx, ir_2_tx, ir_0_rx, ir_1_rx, ir_2_rx] + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [ephy_leds, ephy0_led, ephy1_led, ephy2_led, ephy3_led, + ephy4_led, wled, wf2g_led, wf5g_led] + - if: + properties: + function: + const: flash + then: + properties: + groups: + enum: [par_nand, snfi, spi_nor] + - if: + properties: + function: + const: pcie + then: + properties: + groups: + items: + enum: [pcie0_0_waken, pcie0_1_waken, pcie1_0_waken, + pcie0_0_clkreq, pcie0_1_clkreq, pcie1_0_clkreq, + pcie0_pad_perst, pcie1_pad_perst, pcie_pereset, + pcie_wake, pcie_clkreq] + - if: + properties: + function: + const: pmic + then: + properties: + groups: + enum: [pmic_bus] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + items: + enum: [pwm_ch1_0, pwm_ch1_1, pwm_ch1_2, pwm_ch2_0, pwm_ch2_1, + pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0, + pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1, + pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3, + pwm_ch7_0, pwm_ch7_2, pwm_0, pwm_1] + - if: + properties: + function: + const: sd + then: + properties: + groups: + enum: [sd_0, sd_1] + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spic0_0, spic0_1, spic1_0, spic1_1, spic2_0_wp_hold, + spic2_0, spi_0, spi_1, spi_wp, spi_hold] + - if: + properties: + function: + const: tdm + then: + properties: + groups: + enum: [tdm_0_out_mclk_bclk_ws, tdm_0_in_mclk_bclk_ws, + tdm_0_out_data, tdm_0_in_data, tdm_1_out_mclk_bclk_ws, + tdm_1_in_mclk_bclk_ws, tdm_1_out_data, tdm_1_in_data] + - if: + properties: + function: + const: uart + then: + properties: + groups: + enum: [uart0_0_tx_rx, uart1_0_tx_rx, uart1_0_rts_cts, + uart1_1_tx_rx, uart1_1_rts_cts, uart2_0_tx_rx, + uart2_0_rts_cts, uart2_1_tx_rx, uart2_1_rts_cts, + uart2_2_tx_rx, uart2_2_rts_cts, uart2_3_tx_rx, + uart3_0_tx_rx, uart3_1_tx_rx, uart3_1_rts_cts, + uart4_0_tx_rx, uart4_1_tx_rx, uart4_1_rts_cts, + uart4_2_tx_rx, uart4_2_rts_cts, uart0_txd_rxd, + uart1_0_txd_rxd, uart1_0_cts_rts, uart1_1_txd_rxd, + uart1_1_cts_rts, uart2_0_txd_rxd, uart2_0_cts_rts, + uart2_1_txd_rxd, uart2_1_cts_rts] + - if: + properties: + function: + const: watchdog + then: + properties: + groups: + enum: [watchdog] + - if: + properties: + function: + const: wifi + then: + properties: + groups: + enum: [wf0_2g, wf0_5g] + + '^conf(-|$)': + type: object + additionalProperties: false + description: + pinconf configuration nodes. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + groups: + description: + An array of strings. Each string contains the name of a group. + Valid values are the same as the pinmux node. + + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [GPIO_A, I2S1_IN, I2S1_OUT, I2S_BCLK, I2S_WS, I2S_MCLK, TXD0, + RXD0, SPI_WP, SPI_HOLD, SPI_CLK, SPI_MOSI, SPI_MISO, SPI_CS, + I2C_SDA, I2C_SCL, I2S2_IN, I2S3_IN, I2S4_IN, I2S2_OUT, + I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1, + G2_TXD2, G2_TXD3, G2_TXEN, G2_TXC, G2_RXD0, G2_RXD1, G2_RXD2, + G2_RXD3, G2_RXDV, G2_RXC, NCEB, NWEB, NREB, NDL4, NDL5, NDL6, + NDL7, NRB, NCLE, NALE, NDL0, NDL1, NDL2, NDL3, MDI_TP_P0, + MDI_TN_P0, MDI_RP_P0, MDI_RN_P0, MDI_TP_P1, MDI_TN_P1, + MDI_RP_P1, MDI_RN_P1, MDI_RP_P2, MDI_RN_P2, MDI_TP_P2, + MDI_TN_P2, MDI_TP_P3, MDI_TN_P3, MDI_RP_P3, MDI_RN_P3, + MDI_RP_P4, MDI_RN_P4, MDI_TP_P4, MDI_TN_P4, PMIC_SCL, + PMIC_SDA, SPIC1_CLK, SPIC1_MOSI, SPIC1_MISO, SPIC1_CS, + GPIO_D, WATCHDOG, RTS3_N, CTS3_N, TXD3, RXD3, PERST0_N, + PERST1_N, WLED_N, EPHY_LED0_N, AUXIN0, AUXIN1, AUXIN2, + AUXIN3, TXD4, RXD4, RTS4_N, CST4_N, PWM1, PWM2, PWM3, PWM4, + PWM5, PWM6, PWM7, GPIO_E, TOP_5G_CLK, TOP_5G_DATA, + WF0_5G_HB0, WF0_5G_HB1, WF0_5G_HB2, WF0_5G_HB3, WF0_5G_HB4, + WF0_5G_HB5, WF0_5G_HB6, XO_REQ, TOP_RST_N, SYS_WATCHDOG, + EPHY_LED0_N_JTDO, EPHY_LED1_N_JTDI, EPHY_LED2_N_JTMS, + EPHY_LED3_N_JTCLK, EPHY_LED4_N_JTRST_N, WF2G_LED_N, + WF5G_LED_N, GPIO_9, GPIO_10, GPIO_11, GPIO_12, UART1_TXD, + UART1_RXD, UART1_CTS, UART1_RTS, UART2_TXD, UART2_RXD, + UART2_CTS, UART2_RTS, SMI_MDC, SMI_MDIO, PCIE_PERESET_N, + PWM_0, GPIO_0, GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, + GPIO_6, GPIO_7, GPIO_8, UART0_TXD, UART0_RXD, TOP_2G_CLK, + TOP_2G_DATA, WF0_2G_HB0, WF0_2G_HB1, WF0_2G_HB2, WF0_2G_HB3, + WF0_2G_HB4, WF0_2G_HB5, WF0_2G_HB6] + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-enable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [4, 8, 12, 16] + + slew-rate: + enum: [0, 1] + + mediatek,tdsel: + description: + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@10211000 { + compatible = "mediatek,mt7622-pinctrl"; + reg = <0 0x10211000 0 0x1000>, + <0 0x10005000 0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + + pinctrl_eth_default: eth-pins { + mux-mdio { + groups = "mdc_mdio"; + function = "eth"; + drive-strength = <12>; + }; + + mux-gmac2 { + groups = "rgmii_via_gmac2"; + function = "eth"; + drive-strength = <12>; + }; + + mux-esw { + groups = "esw"; + function = "eth"; + drive-strength = <8>; + }; + + conf-mdio { + pins = "MDC"; + bias-pull-up; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml new file mode 100644 index 000000000..31849dd59 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt76x8-pinctrl.yaml @@ -0,0 +1,450 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt76x8-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT76X8 Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + MediaTek MT76X8 pin controller for MT7628 and MT7688 SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,mt76x8-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn, + p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn, + p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, + pwm_uart2, refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, + spi, spi cs1, spis, sw_r, uart0, uart1, uart2, utif, wdt, + wled_an, wled_kn, -] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: antenna + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: debug + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, + p2led_an, p2led_kn, p3led_an, p3led_kn, p4led_an, + p4led_kn, perst, pwm0, pwm1, refclk, sdmode, spi, + spi cs1, spis, uart0, uart1, uart2, wdt, wled_an, + wled_kn] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an, + p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, + sdmode] + + - if: + properties: + function: + const: p0led_an + then: + properties: + groups: + enum: [p0led_an] + + - if: + properties: + function: + const: p0led_kn + then: + properties: + groups: + enum: [p0led_kn] + + - if: + properties: + function: + const: p1led_an + then: + properties: + groups: + enum: [p1led_an] + + - if: + properties: + function: + const: p1led_kn + then: + properties: + groups: + enum: [p1led_kn] + + - if: + properties: + function: + const: p2led_an + then: + properties: + groups: + enum: [p2led_an] + + - if: + properties: + function: + const: p2led_kn + then: + properties: + groups: + enum: [p2led_kn] + + - if: + properties: + function: + const: p3led_an + then: + properties: + groups: + enum: [p3led_an] + + - if: + properties: + function: + const: p3led_kn + then: + properties: + groups: + enum: [p3led_kn] + + - if: + properties: + function: + const: p4led_an + then: + properties: + groups: + enum: [p4led_an] + + - if: + properties: + function: + const: p4led_kn + then: + properties: + groups: + enum: [p4led_kn] + + - if: + properties: + function: + const: pcie + then: + properties: + groups: + enum: [gpio] + + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [i2s] + + - if: + properties: + function: + const: perst + then: + properties: + groups: + enum: [perst] + + - if: + properties: + function: + const: pwm + then: + properties: + groups: + enum: [uart1, uart2] + + - if: + properties: + function: + const: pwm0 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: pwm1 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: pwm_uart2 + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: refclk + then: + properties: + groups: + enum: [gpio, refclk, spi cs1] + + - if: + properties: + function: + const: rsvd + then: + properties: + groups: + enum: [p0led_an, p0led_kn, wled_an, wled_kn] + + - if: + properties: + function: + const: sdxc + then: + properties: + groups: + enum: [sdmode] + + - if: + properties: + function: + const: sdxc d5 d4 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: sdxc d6 + then: + properties: + groups: + enum: [pwm1] + + - if: + properties: + function: + const: sdxc d7 + then: + properties: + groups: + enum: [pwm0] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi cs1 + then: + properties: + groups: + enum: [spi cs1] + + - if: + properties: + function: + const: spis + then: + properties: + groups: + enum: [spis] + + - if: + properties: + function: + const: sw_r + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart0 + then: + properties: + groups: + enum: [uart0] + + - if: + properties: + function: + const: uart1 + then: + properties: + groups: + enum: [uart1] + + - if: + properties: + function: + const: uart2 + then: + properties: + groups: + enum: [uart2] + + - if: + properties: + function: + const: utif + then: + properties: + groups: + enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, + p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis] + + - if: + properties: + function: + const: wdt + then: + properties: + groups: + enum: [wdt] + + - if: + properties: + function: + const: wled_an + then: + properties: + groups: + enum: [wled_an] + + - if: + properties: + function: + const: wled_kn + then: + properties: + groups: + enum: [wled_kn] + + - if: + properties: + function: + const: "-" + then: + properties: + groups: + enum: [i2c, spi cs1, uart0] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,mt76x8-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml new file mode 100644 index 000000000..74d52a741 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml @@ -0,0 +1,480 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7981 Pin Controller + +maintainers: + - Daniel Golle <daniel@makrotopia.org> + +description: + The MediaTek's MT7981 Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt7981-pinctrl + + reg: + minItems: 9 + maxItems: 9 + + reg-names: + items: + - const: gpio + - const: iocfg_rt + - const: iocfg_rm + - const: iocfg_rb + - const: iocfg_lb + - const: iocfg_bl + - const: iocfg_tm + - const: iocfg_tl + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^.*mux.*$': + type: object + additionalProperties: false + description: | + pinmux configuration nodes. + + The following table shows the effective values of "group", "function" + properties and chip pinout pins + + groups function pins (in pin#) + --------------------------------------------------------------------- + "wa_aice1" "wa_aice" 0, 1 + "wa_aice2" "wa_aice" 0, 1 + "wm_uart_0" "uart" 0, 1 + "dfd" "dfd" 0, 1, 4, 5 + "watchdog" "watchdog" 2 + "pcie_pereset" "pcie" 3 + "jtag" "jtag" 4, 5, 6, 7, 8 + "wm_jtag_0" "jtag" 4, 5, 6, 7, 8 + "wo0_jtag_0" "jtag" 9, 10, 11, 12, 13 + "uart2_0" "uart" 4, 5, 6, 7 + "gbe_led0" "led" 8 + "pta_ext_0" "pta" 4, 5, 6 + "pwm2" "pwm" 7 + "net_wo0_uart_txd_0" "uart" 8 + "spi1_0" "spi" 4, 5, 6, 7 + "i2c0_0" "i2c" 6, 7 + "dfd_ntrst" "dfd" 8 + "wm_aice1" "wa_aice" 9, 10 + "pwm0_0" "pwm" 13 + "pwm0_1" "pwm" 15 + "pwm1_0" "pwm" 14 + "pwm1_1" "pwm" 15 + "net_wo0_uart_txd_1" "uart" 14 + "net_wo0_uart_txd_2" "uart" 15 + "gbe_led1" "led" 13 + "pcm" "pcm" 9, 10, 11, 12, 13, 25 + "watchdog1" "watchdog" 13 + "udi" "udi" 9, 10, 11, 12, 13 + "drv_vbus" "usb" 14 + "emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, + 24, 25 + + "snfi" "flash" 16, 17, 18, 19, 20, 21 + "spi0" "spi" 16, 17, 18, 19 + "spi0_wp_hold" "spi" 20, 21 + "spi1_1" "spi" 22, 23, 24, 25 + "spi2" "spi" 26, 27, 28, 29 + "spi2_wp_hold" "spi" 30, 31 + "uart1_0" "uart" 16, 17, 18, 19 + "uart1_1" "uart" 26, 27, 28, 29 + "uart2_1" "uart" 22, 23, 24, 25 + "pta_ext_1" "pta" 22, 23, 24 + "wm_aurt_1" "uart" 20, 21 + "wm_aurt_2" "uart" 30, 31 + "wm_jtag_1" "jtag" 20, 21, 22, 23, 24 + "wo0_jtag_1" "jtag" 25, 26, 27, 28, 29 + "wa_aice3" "wa_aice" 28, 20 + "wm_aice2" "wa_aice" 30, 31 + "i2c0_1" "i2c" 30, 31 + "u2_phy_i2c" "i2c" 30, 31 + "uart0" "uart" 32, 33 + "sgmii1_phy_i2c" "i2c" 32, 33 + "u3_phy_i2c" "i2c" 32, 33 + "sgmii0_phy_i2c" "i2c" 32, 33 + "pcie_clk" "pcie" 34 + "pcie_wake" "pcie" 35 + "i2c0_2" "i2c" 36, 37 + "smi_mdc_mdio" "eth" 36, 37 + "gbe_ext_mdc_mdio" "eth" 36, 37 + "wf0_mode1" "eth" 40, 41, 42, 43, 44, 45, 46, 47, 48, + 49, 50, 51, 52, 53, 54, 55, 56 + + "wf0_mode3" "eth" 45, 46, 47, 48, 49, 51 + "wf2g_led0" "led" 30 + "wf2g_led1" "led" 34 + "wf5g_led0" "led" 31 + "wf5g_led1" "led" 35 + "mt7531_int" "eth" 38 + "ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22, + 23, 24, 25, 34, 35 + + $ref: /schemas/pinctrl/pinmux-node.yaml + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led, + pwm, spi, uart, watchdog, flash, pcie] + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: wa_aice + then: + properties: + groups: + enum: [wa_aice1, wa_aice2, wm_aice1_1, wa_aice3, wm_aice1_2] + - if: + properties: + function: + const: dfd + then: + properties: + groups: + enum: [dfd, dfd_ntrst] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1] + - if: + properties: + function: + const: pta + then: + properties: + groups: + enum: [pta_ext_0, pta_ext_1] + - if: + properties: + function: + const: pcm + then: + properties: + groups: + enum: [pcm] + - if: + properties: + function: + const: udi + then: + properties: + groups: + enum: [udi] + - if: + properties: + function: + const: usb + then: + properties: + groups: + enum: [drv_vbus] + - if: + properties: + function: + const: ant + then: + properties: + groups: + enum: [ant_sel] + - if: + properties: + function: + const: eth + then: + properties: + groups: + enum: [smi_mdc_mdio, gbe_ext_mdc_mdio, wf0_mode1, wf0_mode3, + mt7531_int] + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c0_0, i2c0_1, u2_phy_i2c, sgmii1_phy_i2c, u3_phy_i2c, + sgmii0_phy_i2c, i2c0_2] + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, + wf5g_led1] + - if: + properties: + function: + const: pwm + then: + properties: + groups: + items: + enum: [pwm2, pwm0_0, pwm0_1, pwm1_0, pwm1_1] + maxItems: 3 + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, + spi2_wp_hold] + maxItems: 4 + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [wm_uart_0, uart2_0, net_wo0_uart_txd_0, + net_wo0_uart_txd_1, net_wo0_uart_txd_2, uart1_0, + uart1_1, uart2_1, wm_aurt_1, wm_aurt_2, uart0] + - if: + properties: + function: + const: watchdog + then: + properties: + groups: + enum: [watchdog] + - if: + properties: + function: + const: flash + then: + properties: + groups: + items: + enum: [emmc_45, snfi] + maxItems: 1 + - if: + properties: + function: + const: pcie + then: + properties: + groups: + items: + enum: [pcie_clk, pcie_wake, pcie_pereset] + maxItems: 3 + + '^.*conf.*$': + type: object + additionalProperties: false + description: pinconf configuration nodes. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [GPIO_WPS, GPIO_RESET, SYS_WATCHDOG, PCIE_PERESET_N, + JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N, + WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK, + WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI, + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_CLK_REQ, PCIE_WAKE_N, SMI_MDC, SMI_MDIO, + GBE_INT, GBE_RESET, WF_DIG_RESETB, WF_CBA_RESETB, + WF_XO_REQ, WF_TOP_CLK, WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, + WF_HB4, WF_HB0, WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, + WF_HB9, WF_HB10] + maxItems: 57 + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + input-enable: true + + input-disable: true + + output-enable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,pull-up-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull up settings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull down settings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", + "iocfg_rb", "iocfg_lb", "iocfg_bl", + "iocfg_tm", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 56>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + mdio_pins: mdio-pins { + mux { + function = "eth"; + groups = "smi_mdc_mdio"; + }; + }; + + spi0_flash_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + + conf-pu { + pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-up = <MTK_PUPD_SET_R1R0_11>; + }; + + conf-pd { + pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; + drive-strength = <MTK_DRIVE_8mA>; + bias-pull-down = <MTK_PUPD_SET_R1R0_11>; + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml new file mode 100644 index 000000000..5ad65135f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -0,0 +1,462 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7986 Pin Controller + +maintainers: + - Sean Wang <sean.wang@kernel.org> + +description: + The MediaTek's MT7986 Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt7986a-pinctrl + - mediatek,mt7986b-pinctrl + + reg: + minItems: 8 + maxItems: 8 + + reg-names: + items: + - const: gpio + - const: iocfg_rt + - const: iocfg_rb + - const: iocfg_lt + - const: iocfg_lb + - const: iocfg_tr + - const: iocfg_tl + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: + GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^.*mux.*$': + type: object + additionalProperties: false + description: | + pinmux configuration nodes. + + The following table shows the effective values of "group", "function" + properties and chip pinout pins + + groups function pins (in pin#) + --------------------------------------------------------------------- + "watchdog" "watchdog" 0 + "wifi_led" "led" 1, 2 + "i2c" "i2c" 3, 4 + "uart1_0" "uart" 7, 8, 9, 10 + "uart1_rx_tx" "uart" 42, 43 + "uart1_cts_rts" "uart" 44, 45 + "pcie_clk" "pcie" 9 + "pcie_wake" "pcie" 10 + "spi1_0" "spi" 11, 12, 13, 14 + "pwm1_1" "pwm" 20, + "pwm0" "pwm" 21, + "pwm1_0" "pwm" 22, + "snfi" "flash" 23, 24, 25, 26, 27, 28 + "spi1_2" "spi" 29, 30, 31, 32 + "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 32 + + "spi1_1" "spi" 23, 24, 25, 26 + "uart1_2_rx_tx" "uart" 29, 30 + "uart1_2_cts_rts" "uart" 31, 32 + "uart1_1" "uart" 23, 24, 25, 26 + "uart2_0_rx_tx" "uart" 29, 30 + "uart2_0_cts_rts" "uart" 31, 32 + "spi0" "spi" 33, 34, 35, 36 + "spi0_wp_hold" "spi" 37, 38 + "uart1_3_rx_tx" "uart" 35, 36 + "uart1_3_cts_rts" "uart" 37, 38 + "uart2_1" "uart" 33, 34, 35, 36 + "spi1_3" "spi" 33, 34, 35, 36 + "uart0" "uart" 39, 40 + "pcie_pereset" "pcie" 41 + "uart1" "uart" 42, 43, 44, 45 + "uart2" "uart" 46, 47, 48, 49 + "emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, + 60, 61 + + "pcm" "audio" 62, 63, 64, 65 + "i2s" "audio" 62, 63, 64, 65 + "switch_int" "eth" 66 + "mdc_mdio" "eth" 67 + "wf_2g" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83 + "wf_5g" "wifi" 91, 92, 93, 94, 95, 96, 97, 98, 99, 100 + "wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, + 84, 85 + + $ref: /schemas/pinctrl/pinmux-node.yaml + properties: + function: + description: + A string containing the name of the function to mux to the group. + There is no "audio", "pcie" functions on mt7986b, you can only use + those functions on mt7986a. + enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart, + watchdog, wifi] + groups: + description: + An array of strings. Each string contains the name of a group. + There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm", and + "i2s" groups on mt7986b, you can only use those groups on mt7986a. + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: audio + then: + properties: + groups: + enum: [pcm, i2s] + - if: + properties: + function: + const: emmc + then: + properties: + groups: + enum: [emmc_45, emmc_51] + - if: + properties: + function: + const: eth + then: + properties: + groups: + enum: [switch_int, mdc_mdio] + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [wifi_led] + - if: + properties: + function: + const: flash + then: + properties: + groups: + enum: [snfi] + - if: + properties: + function: + const: pcie + then: + properties: + groups: + items: + enum: [pcie_clk, pcie_wake, pcie_pereset] + maxItems: 3 + - if: + properties: + function: + const: pwm + then: + properties: + groups: + items: + enum: [pwm0, pwm1_0, pwm1_1] + maxItems: 2 + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3] + maxItems: 2 + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1, + uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx, + uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts, + uart2_1, uart0, uart1, uart2] + maxItems: 2 + - if: + properties: + function: + const: watchdog + then: + properties: + groups: + enum: [watchdog] + - if: + properties: + function: + const: wifi + then: + properties: + groups: + items: + enum: [wf_2g, wf_5g, wf_dbdc] + maxItems: 3 + '^.*conf.*$': + type: object + additionalProperties: false + description: + pinconf configuration nodes. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. There + is no PIN 41 to PIN 65 above on mt7686b, you can only use those + pins on mt7986a. + items: + enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0, + GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7, + GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, + GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, + SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, + SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD, + UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART1_CTS, + UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, + EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3, + EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7, + EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_DRX, + PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO, + WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK, + WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0, + WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9, + WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ, + WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3, + WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7, + WF1_HB8] + maxItems: 101 + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + input-enable: true + + input-disable: true + + output-enable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,pull-up-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull up settings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull down settings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1"; + }; + }; + + uart1_3_pins: uart1-3-pins { + mux { + function = "uart"; + groups = "uart1_3_rx_tx", "uart1_3_cts_rts"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2"; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml new file mode 100644 index 000000000..1f31b520c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml @@ -0,0 +1,580 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT7988 Pin Controller + +maintainers: + - Sean Wang <sean.wang@kernel.org> + +description: + The MediaTek's MT7988 Pin controller is used to control SoC pins. + +properties: + compatible: + enum: + - mediatek,mt7988-pinctrl + + reg: + minItems: 7 + maxItems: 7 + + reg-names: + items: + - const: gpio + - const: iocfg_tr + - const: iocfg_br + - const: iocfg_rb + - const: iocfg_lb + - const: iocfg_tl + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: + GPIO valid number range. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + +patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + + '-pins$': + type: object + additionalProperties: false + + properties: + mux: + type: object + additionalProperties: false + $ref: /schemas/pinctrl/pinmux-node.yaml + description: | + pinmux configuration nodes. + + The following table shows the effective values of "group", "function" + properties and chip pinout pins + + groups function pins (in pin#) + --------------------------------------------------------------------- + "tops_jtag0_0" "jtag" 0, 1, 2, 3, 4 + "wo0_jtag" "jtag" 50, 51, 52, 53, 54 + "wo1_jtag" "jtag" 50, 51, 52, 53, 54 + "wo2_jtag" "jtag" 50, 51, 52, 53, 54 + "jtag" "jtag" 58, 59, 60, 61, 62 + "tops_jtag0_1" "jtag" 58, 59, 60, 61, 62 + "int_usxgmii" "int_usxgmii" 2, 3 + "pwm0" "pwm" 57 + "pwm1" "pwm" 21 + "pwm2" "pwm" 80 + "pwm2_0" "pwm" 58 + "pwm3" "pwm" 81 + "pwm3_0" "pwm" 59 + "pwm4" "pwm" 82 + "pwm4_0" "pwm" 60 + "pwm5" "pwm" 83 + "pwm5_0" "pwm" 61 + "pwm6" "pwm" 69 + "pwm6_0" "pwm" 62 + "pwm7" "pwm" 70 + "pwm7_0" "pwm" 4 + "dfd" "dfd" 0, 1, 2, 3, 4 + "xfi_phy0_i2c0" "i2c" 0, 1 + "xfi_phy1_i2c0" "i2c" 0, 1 + "xfi_phy_pll_i2c0" "i2c" 3, 4 + "xfi_phy_pll_i2c1" "i2c" 3, 4 + "i2c0_0" "i2c" 5, 6 + "i2c1_sfp" "i2c" 5, 6 + "xfi_pextp_phy0_i2c" "i2c" 5, 6 + "xfi_pextp_phy1_i2c" "i2c" 5, 6 + "i2c0_1" "i2c" 15, 16 + "u30_phy_i2c0" "i2c" 15, 16 + "u32_phy_i2c0" "i2c" 15, 16 + "xfi_phy0_i2c1" "i2c" 15, 16 + "xfi_phy1_i2c1" "i2c" 15, 16 + "xfi_phy_pll_i2c2" "i2c" 15, 16 + "i2c1_0" "i2c" 17, 18 + "u30_phy_i2c1" "i2c" 17, 18 + "u32_phy_i2c1" "i2c" 17, 18 + "xfi_phy_pll_i2c3" "i2c" 17, 18 + "sgmii0_i2c" "i2c" 17, 18 + "sgmii1_i2c" "i2c" 17, 18 + "i2c1_2" "i2c" 69, 70 + "i2c2_0" "i2c" 69, 70 + "i2c2_1" "i2c" 71, 72 + "mdc_mdio0" "eth" 5, 6 + "2p5g_ext_mdio" "eth" 28, 29 + "gbe_ext_mdio" "eth" 30, 31 + "mdc_mdio1" "eth" 69, 70 + "pcie_wake_n0_0" "pcie" 7 + "pcie_clk_req_n0_0" "pcie" 8 + "pcie_wake_n3_0" "pcie" 9 + "pcie_clk_req_n3" "pcie" 10 + "pcie_clk_req_n0_1" "pcie" 10 + "pcie_p0_phy_i2c" "pcie" 7, 8 + "pcie_p1_phy_i2c" "pcie" 7, 8 + "pcie_p3_phy_i2c" "pcie" 9, 10 + "pcie_p2_phy_i2c" "pcie" 7, 8 + "ckm_phy_i2c" "pcie" 9, 10 + "pcie_wake_n0_1" "pcie" 13 + "pcie_wake_n3_1" "pcie" 14 + "pcie_2l_0_pereset" "pcie" 19 + "pcie_1l_1_pereset" "pcie" 20 + "pcie_clk_req_n2_1" "pcie" 63 + "pcie_2l_1_pereset" "pcie" 73 + "pcie_1l_0_pereset" "pcie" 74 + "pcie_wake_n1_0" "pcie" 75 + "pcie_clk_req_n1" "pcie" 76 + "pcie_wake_n2_0" "pcie" 77 + "pcie_clk_req_n2_0" "pcie" 78 + "pcie_wake_n2_1" "pcie" 79 + "pmic" "pmic" 11 + "watchdog" "watchdog" 12 + "spi0_wp_hold" "spi" 22, 23 + "spi0" "spi" 24, 25, 26, 27 + "spi1" "spi" 28, 29, 30, 31 + "spi2" "spi" 32, 33, 34, 35 + "spi2_wp_hold" "spi" 36, 37 + "snfi" "flash" 22, 23, 24, 25, 26, 27 + "emmc_45" "flash" 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 + "sdcard" "flash" 32, 33, 34, 35, 36, 37 + "emmc_51" "flash" 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49 + "uart2" "uart" 0, 1, 2, 3 + "tops_uart0_0" "uart" 22, 23 + "uart2_0" "uart" 28, 29, 30, 31 + "uart1_0" "uart" 32, 33, 34, 35 + "uart2_1" "uart" 32, 33, 34, 35 + "net_wo0_uart_txd_0" "uart" 28 + "net_wo1_uart_txd_0" "uart" 29 + "net_wo2_uart_txd_0" "uart" 30 + "tops_uart1_0" "uart" 28, 29 + "tops_uart0_1" "uart" 30, 31 + "tops_uart1_1" "uart" 36, 37 + "uart0" "uart" 55, 56 + "tops_uart0_2" "uart" 55, 56 + "uart2_2" "uart" 50, 51, 52, 53 + "uart1_1" "uart" 58, 59, 60, 61 + "uart2_3" "uart" 58, 59, 60, 61 + "uart1_2" "uart" 80, 81, 82, 83 + "uart1_2_lite" "uart" 80, 81 + "tops_uart1_2" "uart" 80, 81 + "net_wo0_uart_txd_1" "uart" 80 + "net_wo1_uart_txd_1" "uart" 81 + "net_wo2_uart_txd_1" "uart" 82 + "udi" "udi" 32, 33, 34, 35, 36 + "i2s" "audio" 50, 51, 52, 53, 54 + "pcm" "audio" 50, 51, 52, 53 + "gbe0_led1" "led" 58 + "gbe1_led1" "led" 59 + "gbe2_led1" "led" 60 + "gbe3_led1" "led" 61 + "2p5gbe_led1" "led" 62 + "gbe0_led0" "led" 64 + "gbe1_led0" "led" 65 + "gbe2_led0" "led" 66 + "gbe3_led0" "led" 67 + "2p5gbe_led0" "led" 68 + "drv_vbus_p1" "usb" 63 + "drv_vbus" "usb" 79 + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [audio, dfd, eth, flash, i2c, int_usxgmii, jtag, led, pcie, pmic, pwm, spi, + uart, udi, usb, watchdog] + groups: + description: + An array of strings. Each string contains the name of a group. + + required: + - function + - groups + + allOf: + - if: + properties: + function: + const: audio + then: + properties: + groups: + enum: [i2s, pcm] + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag, tops_jtag0_0, tops_jtag0_1, wo0_jtag, wo1_jtag, wo2_jtag] + - if: + properties: + function: + const: int_usxgmii + then: + properties: + groups: + const: int_usxgmii + - if: + properties: + function: + const: dfd + then: + properties: + groups: + const: dfd + - if: + properties: + function: + const: flash + then: + properties: + groups: + enum: [emmc_45, emmc_51, sdcard, snfi] + - if: + properties: + function: + const: eth + then: + properties: + groups: + enum: [2p5g_ext_mdio, gbe_ext_mdio, mdc_mdio0, mdc_mdio1] + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [xfi_phy0_i2c0, xfi_phy1_i2c0, xfi_phy_pll_i2c0, + xfi_phy_pll_i2c1, i2c0_0, i2c1_sfp, xfi_pextp_phy0_i2c, + xfi_pextp_phy1_i2c, i2c0_1, u30_phy_i2c0, u32_phy_i2c0, + xfi_phy0_i2c1, xfi_phy1_i2c1, xfi_phy_pll_i2c2, i2c1_0, + u30_phy_i2c1, u32_phy_i2c1, xfi_phy_pll_i2c3, sgmii0_i2c, + sgmii1_i2c, i2c1_2, i2c2_0, i2c2_1] + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [2p5gbe_led0, 2p5gbe_led1, gbe0_led0, gbe0_led1, gbe1_led0, gbe1_led1, + gbe2_led0, gbe2_led1, gbe3_led0, gbe3_led1, wf5g_led0, wf5g_led1] + - if: + properties: + function: + const: pcie + then: + properties: + groups: + items: + enum: [pcie_wake_n0_0, pcie_clk_req_n0_0, pcie_wake_n3_0, + pcie_clk_req_n3, pcie_p0_phy_i2c, pcie_p1_phy_i2c, + pcie_p3_phy_i2c, pcie_p2_phy_i2c, ckm_phy_i2c, + pcie_wake_n0_1, pcie_wake_n3_1, pcie_2l_0_pereset, + pcie_1l_1_pereset, pcie_clk_req_n2_1, pcie_2l_1_pereset, + pcie_1l_0_pereset, pcie_wake_n1_0, pcie_clk_req_n1, + pcie_wake_n2_0, pcie_clk_req_n2_0, pcie_wake_n2_1, + pcie_clk_req_n0_1] + maxItems: 3 + - if: + properties: + function: + const: pmic + then: + properties: + groups: + const: pmic + - if: + properties: + function: + const: pwm + then: + properties: + groups: + items: + enum: [pwm0, pwm1, pwm2, pwm2_0, pwm3, pwm3_0, pwm4, pwm4_0, pwm5, pwm5_0, + pwm6, pwm6_0, pwm7, pwm7_0] + maxItems: 2 + - if: + properties: + function: + const: spi + then: + properties: + groups: + items: + enum: [spi0, spi0_wp_hold, spi1, spi2, spi2_wp_hold] + maxItems: 2 + - if: + properties: + function: + const: uart + then: + properties: + groups: + items: + enum: [net_wo0_uart_txd_0, net_wo0_uart_txd_1, net_wo1_uart_txd_0, + net_wo1_uart_txd_1, net_wo2_uart_txd_0, net_wo2_uart_txd_1, + tops_uart0_0, tops_uart0_1, tops_uart0_2, tops_uart1_0, + tops_uart1_1, tops_uart1_2, uart0, uart1_0, uart1_1, uart1_2, + uart1_2_lite, uart2, uart2_0, uart2_1, uart2_3] + maxItems: 2 + - if: + properties: + function: + const: watchdog + then: + properties: + groups: + const: watchdog + - if: + properties: + function: + const: udi + then: + properties: + groups: + const: udi + - if: + properties: + function: + const: usb + then: + properties: + groups: + items: + enum: [drv_vbus, drv_vbus_p1] + maxItems: 1 + + patternProperties: + '^conf(-[-a-z]*)?$': + type: object + additionalProperties: false + description: + pinconf configuration nodes. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + An array of strings. Each string contains the name of a pin. + items: + enum: [UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, GPIO_A, SMI_0_MDC, + SMI_0_MDIO, PCIE30_2L_0_WAKE_N, PCIE30_2L_0_CLKREQ_N, + PCIE30_1L_1_WAKE_N, PCIE30_1L_1_CLKREQ_N, GPIO_P, WATCHDOG, + GPIO_RESET, GPIO_WPS, PMIC_I2C_SCL, PMIC_I2C_SDA, I2C_1_SCL, + I2C_1_SDA, PCIE30_2L_0_PRESET_N, PCIE30_1L_1_PRESET_N, PWMD1, + SPI0_WP, SPI0_HOLD, SPI0_CSB, SPI0_MISO, SPI0_MOSI, SPI0_CLK, + SPI1_CSB, SPI1_MISO, SPI1_MOSI, SPI1_CLK, SPI2_CLK, SPI2_MOSI, + SPI2_MISO, SPI2_CSB, SPI2_HOLD, SPI2_WP, EMMC_RSTB, EMMC_DSL, + EMMC_CK, EMMC_CMD, EMMC_DATA_7, EMMC_DATA_6, EMMC_DATA_5, + EMMC_DATA_4, EMMC_DATA_3, EMMC_DATA_2, EMMC_DATA_1, + EMMC_DATA_0, PCM_FS_I2S_LRCK, PCM_CLK_I2S_BCLK, + PCM_DRX_I2S_DIN, PCM_DTX_I2S_DOUT, PCM_MCK_I2S_MCLK, + UART0_RXD, UART0_TXD, PWMD0, JTAG_JTDI, JTAG_JTDO, JTAG_JTMS, + JTAG_JTCLK, JTAG_JTRST_N, USB_DRV_VBUS_P1, LED_A, LED_B, LED_C, + LED_D, LED_E, GPIO_B, GPIO_C, I2C_2_SCL, I2C_2_SDA, + PCIE30_2L_1_PRESET_N, PCIE30_1L_0_PRESET_N, + PCIE30_2L_1_WAKE_N, PCIE30_2L_1_CLKREQ_N, + PCIE30_1L_0_WAKE_N, PCIE30_1L_0_CLKREQ_N, USB_DRV_VBUS_P0, + UART1_RXD, UART1_TXD, UART1_CTS, UART1_RTS] + maxItems: 84 + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + input-enable: true + + input-disable: true + + output-enable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + mediatek,pull-up-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull up settings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3' + Pull down settings for 2 pull resistors, R0 and R1. Valid arguments + are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt65xx.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7988-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d00000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_tr", + "iocfg_br", "iocfg_rb", + "iocfg_lb", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 84>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + + i2c0_pins: i2c0-g0-pins { + mux { + function = "i2c"; + groups = "i2c0_1"; + }; + }; + + mdio0_pins: mdio0-pins { + mux { + function = "eth"; + groups = "mdc_mdio0"; + }; + + conf { + pins = "SMI_0_MDC", "SMI_0_MDIO"; + drive-strength = <8>; + }; + }; + + mmc0_pins_emmc_51: mmc0-emmc-51-pins { + mux { + function = "flash"; + groups = "emmc_51"; + }; + }; + + mmc0_pins_sdcard: mmc0-sdcard-pins { + mux { + function = "flash"; + groups = "sdcard"; + }; + }; + + pcie0_pins: pcie0-pins { + mux { + function = "pcie"; + groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", + "pcie_wake_n0_0"; + }; + }; + + pcie1_pins: pcie1-pins { + mux { + function = "pcie"; + groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", + "pcie_wake_n1_0"; + }; + }; + + pcie2_pins: pcie2-pins { + mux { + function = "pcie"; + groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", + "pcie_wake_n2_0"; + }; + }; + + pcie3_pins: pcie3-pins { + mux { + function = "pcie"; + groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", + "pcie_wake_n3_0"; + }; + }; + + uart0_pins: uart0-pins { + mux { + function = "uart"; + groups = "uart0"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml new file mode 100644 index 000000000..3db2438fa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -0,0 +1,239 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8183-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8183 Pin Controller + +maintainers: + - Sean Wang <sean.wang@kernel.org> + +description: + The MediaTek's MT8183 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8183-pinctrl + + reg: + minItems: 10 + maxItems: 10 + + reg-names: + items: + - const: iocfg0 + - const: iocfg1 + - const: iocfg2 + - const: iocfg3 + - const: iocfg4 + - const: iocfg5 + - const: iocfg6 + - const: iocfg7 + - const: iocfg8 + - const: eint + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: + GPIO valid number range. + + gpio-line-names: true + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +patternProperties: + '-pins(-[a-z]+)?$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in <soc>-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + mediatek,drive-strength-adv: + deprecated: true + description: | + DEPRECATED: Please use drive-strength-microamp instead. + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + description: | + Pull up settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as + below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as + below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt8183-pinfunc.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8183-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11e80000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11e90000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11c50000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg1", "iocfg2", + "iocfg3", "iocfg4", "iocfg5", + "iocfg6", "iocfg7", "iocfg8", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 192>; + interrupt-controller; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + i2c0_pins_a: i2c0-pins { + pins1 { + pinmux = <PINMUX_GPIO48__FUNC_SCL5>, + <PINMUX_GPIO49__FUNC_SDA5>; + mediatek,pull-up-adv = <3>; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins_a: i2c1-pins { + pins { + pinmux = <PINMUX_GPIO50__FUNC_SCL3>, + <PINMUX_GPIO51__FUNC_SDA3>; + mediatek,pull-down-adv = <2>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml new file mode 100644 index 000000000..69136ddd0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8186-pinctrl.yaml @@ -0,0 +1,275 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8186 Pin Controller + +maintainers: + - Sean Wang <sean.wang@mediatek.com> + +description: + The MediaTek's MT8186 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8186-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + + reg: + description: + Physical address base for GPIO base registers. There are 8 different GPIO + physical address base in mt8186. + maxItems: 8 + + reg-names: + description: + GPIO base register names. + items: + - const: iocfg0 + - const: iocfg_lt + - const: iocfg_lm + - const: iocfg_lb + - const: iocfg_bl + - const: iocfg_rb + - const: iocfg_rt + - const: eint + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq + maxItems: 1 + + mediatek,rsel-resistance-in-si-unit: + type: boolean + description: + Identifying i2c pins pull up/down type which is RSEL. It can support RSEL + define or si unit value(ohm) to set different resistance. + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + } + }; + /* GPIO128 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>; + } + }; + }; + $ref: pinmux-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8186 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203] + description: mt8186 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8186 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8186. + For pull down type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "75000" & "5000" + in mt8186. + An example of using RSEL define: + pincontroller { + i2c0_pin { + pins { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>; + bias-pull-down = <MTK_PULL_SET_RSEL_001>; + } + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel-resistance-in-si-unit; + } + pincontroller { + i2c0_pin { + pins { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>; + bias-pull-down = <75000>; + } + }; + }; + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8186 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203] + description: mt8186 pull up RSEL type define value. + - enum: [1000, 5000, 10000, 75000] + description: mt8186 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8186. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" define in + mt8186. It can also support resistance value(ohm) "1000" & "5000" + & "10000" & "75000" in mt8186. + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel-resistance-in-si-unit; + } + pincontroller { + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO128__FUNC_SDA0>; + bias-pull-up = <1000>; + } + }; + }; + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt8186-pinfunc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8186-pinctrl"; + reg = <0x10005000 0x1000>, + <0x10002000 0x0200>, + <0x10002200 0x0200>, + <0x10002400 0x0200>, + <0x10002600 0x0200>, + <0x10002A00 0x0200>, + <0x10002c00 0x0200>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", + "iocfg_lb", "iocfg_bl", "iocfg_rb", + "iocfg_rt", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 185>; + interrupt-controller; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + pio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + output-low; + }; + }; + + spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO0__FUNC_SPI0_CLK_B>, + <PINMUX_GPIO1__FUNC_SPI0_CSB_B>, + <PINMUX_GPIO2__FUNC_SPI0_MO_B>; + bias-disable; + }; + pins-spi-mi { + pinmux = <PINMUX_GPIO3__FUNC_SPI0_MI_B>; + bias-pull-down; + }; + }; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO127__FUNC_SCL0>, + <PINMUX_GPIO128__FUNC_SDA0>; + bias-pull-up = <MTK_PULL_SET_RSEL_001>; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml new file mode 100644 index 000000000..e994b0c70 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -0,0 +1,232 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8188 Pin Controller + +maintainers: + - Hui Liu <hui.liu@mediatek.com> + +description: + The MediaTek's MT8188 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8188-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier, should be two. The first cell is the + pin number, the second cell is used to specify optional parameters which + are defined in <dt-bindings/gpio/gpio.h>. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + + reg: + items: + - description: gpio registers base address + - description: rm group io configuration registers base address + - description: lt group io configuration registers base address + - description: lm group io configuration registers base address + - description: rt group io configuration registers base address + - description: eint registers base address + + reg-names: + items: + - const: iocfg0 + - const: iocfg_rm + - const: iocfg_lt + - const: iocfg_lm + - const: iocfg_rt + - const: eint + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + + mediatek,rsel-resistance-in-si-unit: + type: boolean + description: + We provide two methods to select the resistance for I2C when pull up or + pull down. The first is by RSEL definition value, another one is by + resistance value(ohm). This flag is used to identify if the method is + resistance(si unit) value. + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h + directly, for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8188 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8188 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8188 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it doesn't need add RSEL & R1R0 + define and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull down type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "75000" & "5000" + in mt8188. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8188 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8188 pull up RSEL type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] + description: mt8188 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to set + different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8188. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support + "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" & + "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" & + "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" & + "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" define in + mt8188. It can also support resistance value(ohm) "1000" & "1500" + & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" in mt8188. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8188-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c00000 0x1000>, + <0x11e10000 0x1000>, + <0x11e20000 0x1000>, + <0x11ea0000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", + "iocfg_lt", "iocfg_lm", "iocfg_rt", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 176>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + pio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>; + output-low; + }; + }; + + spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, + <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, + <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>; + drive-strength = <6>; + }; + pins-spi-mi { + pinmux = <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + }; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO55__FUNC_B1_SCL0>, + <PINMUX_GPIO56__FUNC_B1_SDA0>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml new file mode 100644 index 000000000..32e4653da --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8189-pinctrl.yaml @@ -0,0 +1,213 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8189-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8189 Pin Controller + +maintainers: + - Lei Xue <lei.xue@mediatek.com> + - Cathy Xu <ot_cathy.xu@mediatek.com> + +description: + The MediaTek's MT8189 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8189-pinctrl + + reg: + items: + - description: gpio base + - description: lm group IO + - description: rb0 group IO + - description: rb1 group IO + - description: bm0 group IO + - description: bm1 group IO + - description: bm2 group IO + - description: lt0 group IO + - description: lt1 group IO + - description: rt group IO + - description: eint0 group IO + - description: eint1 group IO + - description: eint2 group IO + - description: eint3 group IO + - description: eint4 group IO + + reg-names: + items: + - const: base + - const: lm + - const: rb0 + - const: rb1 + - const: bm0 + - const: bm1 + - const: bm2 + - const: lt0 + - const: lt1 + - const: rt + - const: eint0 + - const: eint1 + - const: eint2 + - const: eint3 + - const: eint4 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in arch/arm64/boot/dts/mediatek/mt8189-pinfunc.h + directly, for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8189 pull down PUPD/R0/R1 type define value. + - enum: [75000, 5000] + description: mt8189 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it doesn't need add R1R0 define + and resistance value. + + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8189. + + For pull down type is PD/RSEL, it can add resistance value(ohm) + to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8189 pull up PUPD/R0/R1 type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000] + description: mt8189 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add R1R0 define + and resistance value. + + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8189. + + For pull up type is PU/RSEL, it can add resistance value(ohm) + to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt65xx.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #define PINMUX_GPIO51__FUNC_SCL0 (MTK_PIN_NO(51) | 2) + #define PINMUX_GPIO52__FUNC_SDA0 (MTK_PIN_NO(52) | 2) + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8189-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11b50000 0x1000>, + <0x11c50000 0x1000>, + <0x11c60000 0x1000>, + <0x11d20000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e30000 0x1000>, + <0x11f20000 0x1000>, + <0x11ce0000 0x1000>, + <0x11de0000 0x1000>, + <0x11e60000 0x1000>, + <0x1c01e000 0x1000>, + <0x11f00000 0x1000>; + reg-names = "base", "lm", "rb0", "rb1", "bm0" , "bm1", + "bm2", "lt0", "lt1", "rt", "eint0", "eint1", + "eint2", "eint3", "eint4"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 182>; + interrupt-controller; + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO51__FUNC_SCL0>, + <PINMUX_GPIO52__FUNC_SDA0>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml new file mode 100644 index 000000000..949dcd6fd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8192 Pin Controller + +maintainers: + - Sean Wang <sean.wang@mediatek.com> + +description: + The MediaTek's MT8192 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8192-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: GPIO valid number range. + maxItems: 1 + + gpio-line-names: true + + reg: + description: + Physical address base for GPIO base registers. There are 11 GPIO physical + address base in mt8192. + maxItems: 11 + + reg-names: + description: + GPIO base register names. + maxItems: 11 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: pinmux-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. + + drive-strength: + description: + It can support some arguments, such as MTK_DRIVE_4mA, + MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. It can only + support 2/4/6/8/10/12/14/16mA in mt8192. + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull down type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: PUPD/R1/R0 pull up type. See MTK_PUPD_SET_R1R0_ + defines in dt-bindings/pinctrl/mt65xx.h. + - enum: [200, 201, 202, 203] + description: RSEL pull up type. See MTK_PULL_SET_RSEL_ defines + in dt-bindings/pinctrl/mt65xx.h. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt8192-pinfunc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e70000 0x1000>, + <0x11ea0000 0x1000>, + <0x11f20000 0x1000>, + <0x11f30000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + spi1-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>, + <PINMUX_GPIO159__FUNC_SPI1_A_MO>, + <PINMUX_GPIO156__FUNC_SPI1_A_CLK>; + bias-disable; + }; + + pins-miso { + pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>; + bias-pull-down; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml new file mode 100644 index 000000000..33cb71775 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8195-pinctrl.yaml @@ -0,0 +1,286 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8195 Pin Controller + +maintainers: + - Sean Wang <sean.wang@mediatek.com> + +description: + The MediaTek's MT8195 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8195-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: GPIO valid number range. + maxItems: 1 + + gpio-line-names: true + + reg: + description: + Physical address base for GPIO base registers. There are 8 GPIO physical + address base in mt8195. + maxItems: 8 + + reg-names: + description: + GPIO base register names. + maxItems: 8 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + + mediatek,rsel-resistance-in-si-unit: + type: boolean + description: + Identifying i2c pins pull up/down type which is RSEL. It can support RSEL + define or si unit value(ohm) to set different resistance. + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + patternProperties: + '^pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + gpio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + } + }; + /* GPIO8 set as multifunction SDA0 */ + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>; + } + }; + }; + $ref: pinmux-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8195 pull down PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8195 pull down RSEL type define value. + - enum: [75000, 5000] + description: mt8195 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8195. + For pull down type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" + & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" + & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" + define in mt8195. It can also support resistance value(ohm) + "75000" & "5000" in mt8195. + + An example of using RSEL define: + pincontroller { + i2c0_pin { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>; + bias-pull-down = <MTK_PULL_SET_RSEL_001>; + } + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel-resistance-in-si-unit; + } + pincontroller { + i2c0_pin { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>; + bias-pull-down = <75000>; + } + }; + }; + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8195 pull up PUPD/R0/R1 type define value. + - enum: [200, 201, 202, 203, 204, 205, 206, 207] + description: mt8195 pull up RSEL type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 10000, 75000] + description: mt8195 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add RSEL & R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8195. + For pull up type is RSEL, it can add RSEL define & resistance + value(ohm) to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". + It can support "MTK_PULL_SET_RSEL_000" & "MTK_PULL_SET_RSEL_001" + & "MTK_PULL_SET_RSEL_010" & "MTK_PULL_SET_RSEL_011" + & "MTK_PULL_SET_RSEL_100" & "MTK_PULL_SET_RSEL_101" + & "MTK_PULL_SET_RSEL_110" & "MTK_PULL_SET_RSEL_111" + define in mt8195. It can also support resistance value(ohm) "1000" + & "1500" & "2000" & "3000" & "4000" & "5000" & "10000" & "75000" + in mt8195. + An example of using RSEL define: + pincontroller { + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>; + bias-pull-up = <MTK_PULL_SET_RSEL_001>; + } + }; + }; + An example of using si unit resistance value(ohm): + &pio { + mediatek,rsel-resistance-in-si-unit; + } + pincontroller { + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>; + bias-pull-up = <1000>; + } + }; + }; + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt8195-pinfunc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + # + pio: pinctrl@10005000 { + compatible = "mediatek,mt8195-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11eb0000 0x1000>, + <0x11f40000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 144>; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + pio-pins { + pins { + pinmux = <PINMUX_GPIO0__FUNC_GPIO0>; + output-low; + }; + }; + + spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, + <PINMUX_GPIO134__FUNC_SPIM0_MO>, + <PINMUX_GPIO133__FUNC_SPIM0_CLK>; + bias-disable; + }; + pins-spi-mi { + pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; + bias-pull-down; + }; + }; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>, + <PINMUX_GPIO9__FUNC_SCL0>; + bias-disable; + drive-strength-microamp = <1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml new file mode 100644 index 000000000..9082bd625 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml @@ -0,0 +1,236 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8196 Pin Controller + +maintainers: + - Lei Xue <lei.xue@mediatek.com> + - Cathy Xu <ot_cathy.xu@mediatek.com> + +description: + The MediaTek's MT8196 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8196-pinctrl + + reg: + items: + - description: gpio base + - description: rt group IO + - description: rm1 group IO + - description: rm2 group IO + - description: rb group IO + - description: bm1 group IO + - description: bm2 group IO + - description: bm3 group IO + - description: lt group IO + - description: lm1 group IO + - description: lm2 group IO + - description: lb1 group IO + - description: lb2 group IO + - description: tm1 group IO + - description: tm2 group IO + - description: tm3 group IO + - description: eint0 group IO + - description: eint1 group IO + - description: eint2 group IO + - description: eint3 group IO + - description: eint4 group IO + + reg-names: + items: + - const: base + - const: rt + - const: rm1 + - const: rm2 + - const: rb + - const: bm1 + - const: bm2 + - const: bm3 + - const: lt + - const: lm1 + - const: lm2 + - const: lb1 + - const: lb2 + - const: tm1 + - const: tm2 + - const: tm3 + - const: eint0 + - const: eint1 + - const: eint2 + - const: eint3 + - const: eint4 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: + Number of cells in GPIO specifier, should be two. The first cell is the + pin number, the second cell is used to specify optional parameters which + are defined in <dt-bindings/gpio/gpio.h>. + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-line-names: true + +# PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h + directly, for this SoC. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8196 pull down PUPD/R0/R1 type define value. + - enum: [75000, 5000] + description: mt8196 pull down RSEL type si unit value(ohm). + description: | + For pull down type is normal, it doesn't need add R1R0 define + and resistance value. + For pull down type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8196. + For pull down type is PD/RSEL, it can add resistance value(ohm) + to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support resistance + value(ohm) "75000" & "5000" in mt8196. + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: mt8196 pull up PUPD/R0/R1 type define value. + - enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000] + description: mt8196 pull up RSEL type si unit value(ohm). + description: | + For pull up type is normal, it don't need add R1R0 define + and resistance value. + For pull up type is PUPD/R0/R1 type, it can add R1R0 define to + set different resistance. It can support "MTK_PUPD_SET_R1R0_00" & + "MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" & + "MTK_PUPD_SET_R1R0_11" define in mt8196. + For pull up type is PU/RSEL, it can add resistance value(ohm) + to set different resistance by identifying property + "mediatek,rsel-resistance-in-si-unit". It can support resistance + value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" & + "75000" in mt8196. + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/mt65xx.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1) + #define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1) + + pio: pinctrl@1002d000 { + compatible = "mediatek,mt8196-pinctrl"; + reg = <0x1002d000 0x1000>, + <0x12000000 0x1000>, + <0x12020000 0x1000>, + <0x12040000 0x1000>, + <0x12060000 0x1000>, + <0x12820000 0x1000>, + <0x12840000 0x1000>, + <0x12860000 0x1000>, + <0x13000000 0x1000>, + <0x13020000 0x1000>, + <0x13040000 0x1000>, + <0x130f0000 0x1000>, + <0x13110000 0x1000>, + <0x13800000 0x1000>, + <0x13820000 0x1000>, + <0x13860000 0x1000>, + <0x12080000 0x1000>, + <0x12880000 0x1000>, + <0x13080000 0x1000>, + <0x13880000 0x1000>, + <0x1c54a000 0x1000>; + reg-names = "base", "rt", "rm1", "rm2", "rb" , "bm1", + "bm2", "bm3", "lt", "lm1", "lm2", "lb1", + "lb2", "tm1", "tm2", "tm3", "eint0", "eint1", + "eint2", "eint3", "eint4"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 271>; + interrupt-controller; + interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>; + #interrupt-cells = <2>; + + i2c0-pins { + pins { + pinmux = <PINMUX_GPIO99__FUNC_SCL0>, + <PINMUX_GPIO100__FUNC_SDA0>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml new file mode 100644 index 000000000..7b43e7857 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,230 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8365 Pin Controller + +maintainers: + - Zhiyong Tao <zhiyong.tao@mediatek.com> + - Bernhard Rosenkränzer <bero@baylibre.com> + +description: + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + maxItems: 1 + + mediatek,pctl-regmap: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + minItems: 1 + maxItems: 2 + description: + Should be phandles of the syscfg node. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below mentioned gpio + binding representation for description of particular cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +patternProperties: + "-pins$": + type: object + additionalProperties: false + patternProperties: + "pins$": + type: object + additionalProperties: false + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + description: + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined as macros in <soc>-pinfunc.h directly. + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull up R1/R0 type define value. + description: | + For pull up type is normal, it don't need add R1/R0 define. + For pull up type is R1/R0 type, it can add value to set different + resistance. Valid arguments are described as below: + 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 103: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + + bias-pull-down: + oneOf: + - type: boolean + - enum: [100, 101, 102, 103] + description: Pull down R1/R0 type define value. + description: | + For pull down type is normal, it don't need add R1/R0 define. + For pull down type is R1/R0 type, it can add value to set + different resistance. Valid arguments are described as below: + 100: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 101: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 102: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 103: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + input-enable: true + + input-disable: true + + output-low: true + + output-high: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-strength-microamp: + enum: [125, 250, 500, 1000] + + mediatek,drive-strength-adv: + deprecated: true + description: | + DEPRECATED: Please use drive-strength-microamp instead. + Describe the specific driving setup property. + For I2C pins, the existing generic driving setup can only support + 2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they + can support 0.125/0.25/0.5/1mA adjustment. If we enable specific + driving setup, the existing generic setup will be disabled. + The specific driving setup is controlled by E1E0EN. + When E1=0/E0=0, the strength is 0.125mA. + When E1=0/E0=1, the strength is 0.25mA. + When E1=1/E0=0, the strength is 0.5mA. + When E1=1/E0=1, the strength is 1mA. + EN is used to enable or disable the specific driving setup. + Valid arguments are described as below: + 0: (E1, E0, EN) = (0, 0, 0) + 1: (E1, E0, EN) = (0, 0, 1) + 2: (E1, E0, EN) = (0, 1, 0) + 3: (E1, E0, EN) = (0, 1, 1) + 4: (E1, E0, EN) = (1, 0, 0) + 5: (E1, E0, EN) = (1, 0, 1) + 6: (E1, E0, EN) = (1, 1, 0) + 7: (E1, E0, EN) = (1, 1, 1) + So the valid arguments are from 0 to 7. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + mediatek,pull-up-adv: + deprecated: true + description: | + DEPRECATED: Please use bias-pull-up instead. + Pull up settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as + below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + deprecated: true + description: | + DEPRECATED: Please use bias-pull-down instead. + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as + below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + mediatek,tdsel: + description: + An integer describing the steps for output level shifter duty + cycle when asserted (high pulse width adjustment). Valid arguments + are from 0 to 15. + $ref: /schemas/types.yaml#/definitions/uint32 + + mediatek,rdsel: + description: + An integer describing the steps for input level shifter duty cycle + when asserted (high pulse width adjustment). Valid arguments are + from 0 to 63. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - pinmux + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt8365-pinfunc.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + + pio-pins { + pins { + pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, <MT8365_PIN_60_SCL1__FUNC_SCL1_0>; + mediatek,pull-up-adv = <3>; + bias-pull-up; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml new file mode 100644 index 000000000..e07f4723d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mcp23s08.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mcp23s08.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip I/O expander with serial interface (I2C/SPI) + +maintainers: + - Himanshu Bhavani <himanshu.bhavani@siliconsignals.io> + +description: + Microchip MCP23008, MCP23017, MCP23S08, MCP23S17, MCP23S18 GPIO expander + chips.These chips provide 8 or 16 GPIO pins with either I2C or SPI interface. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - microchip,mcp23s08 + - microchip,mcp23s17 + - microchip,mcp23s18 + - microchip,mcp23008 + - microchip,mcp23017 + - microchip,mcp23018 + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + maxItems: 1 + + reset-gpios: + description: GPIO specifier for active-low reset pin. + maxItems: 1 + + microchip,spi-present-mask: + description: + Multiple SPI chips can share the same SPI chipselect. Set a bit in + bit0-7 in this mask to 1 if there is a chip connected with the + corresponding spi address set. For example if you have a chip with + address 3 connected, you have to set bit3 to 1, which is 0x08. mcp23s08 + chip variant only supports bits 0-3. It is not possible to mix mcp23s08 + and mcp23s17 on the same chipselect. Set at least one bit to 1 for SPI + chips. + $ref: /schemas/types.yaml#/definitions/uint8 + + microchip,irq-mirror: + type: boolean + description: + Sets the mirror flag in the IOCON register. Devices with two interrupt + outputs (these are the devices ending with 17 and those that have 16 IOs) + have two IO banks IO 0-7 form bank 1 and IO 8-15 are bank 2. These chips + have two different interrupt outputs One for bank 1 and another for + bank 2. If irq-mirror is set, both interrupts are generated regardless of + the bank that an input change occurred on. If it is not set,the interrupt + are only generated for the bank they belong to. + + microchip,irq-active-high: + type: boolean + description: + Sets the INTPOL flag in the IOCON register.This configures the IRQ output + polarity as active high. + + drive-open-drain: + type: boolean + description: + Sets the ODR flag in the IOCON register. This configures the IRQ output as + open drain active low. + + pinmux: + type: object + properties: + pins: + description: + The list of GPIO pins controlled by this node. Each pin name + corresponds to a physical pin on the GPIO expander. + items: + pattern: '^gpio([0-9]|[1][0-5])$' + maxItems: 16 + + bias-pull-up: + type: boolean + description: + Configures pull-up resistors for the GPIO pins. Absence of this + property will leave the configuration in its default state. + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + gpio@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + microchip,irq-mirror; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio0>, <&gpiopullups>; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + + gpiopullups: pinmux { + pins = "gpio0", "gpio1", "gpio2", "gpio3", + "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15"; + bias-pull-up; + }; + }; + }; + + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + gpio@0 { + compatible = "microchip,mcp23s17"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <1000000>; + microchip,spi-present-mask = /bits/ 8 <0x01>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml new file mode 100644 index 000000000..3c98eb35f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC iomux0 + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: + iomux0 is responsible for routing some functions to either the FPGA fabric, + or to MSSIOs. It only performs muxing, and has no IO configuration role, as + fabric IOs are configured separately and just routing a function to MSSIOs is + not sufficient for it to actually get mapped to an MSSIO, just makes it + possible. + +properties: + compatible: + oneOf: + - const: microchip,mpfs-pinctrl-iomux0 + - items: + - const: microchip,pic64gx-pinctrl-iomux0 + - const: microchip,mpfs-pinctrl-iomux0 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ spi0, spi1, i2c0, i2c1, can0, can1, qspi, uart0, uart1, uart2, + uart3, uart4, mdio0, mdio1 ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ spi0_fabric, spi0_mssio, spi1_fabric, spi1_mssio, i2c0_fabric, + i2c0_mssio, i2c1_fabric, i2c1_mssio, can0_fabric, can0_mssio, + can1_fabric, can1_mssio, qspi_fabric, qspi_mssio, + uart0_fabric, uart0_mssio, uart1_fabric, uart1_mssio, + uart2_fabric, uart2_mssio, uart3_fabric, uart3_mssio, + uart4_fabric, uart4_mssio, mdio0_fabric, mdio0_mssio, + mdio1_fabric, mdio1_mssio ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #size-cells = <1>; + #address-cells = <1>; + + pinctrl@200 { + compatible = "microchip,mpfs-pinctrl-iomux0"; + reg = <0x200 0x4>; + + mux-spi0-fabric { + function = "spi0"; + groups = "spi0_fabric"; + }; + + mux-spi1-mssio { + function = "spi1"; + groups = "spi1_mssio"; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml new file mode 100644 index 000000000..fe0519616 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-mssio.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-mssio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip Polarfire SoC MSSIO pinctrl + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +properties: + compatible: + oneOf: + - const: microchip,mpfs-pinctrl-mssio + - items: + - const: microchip,pic64gx-pinctrl-mssio + - const: microchip,mpfs-pinctrl-mssio + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '-cfg$': + type: object + additionalProperties: false + + patternProperties: + '-pins$': + type: object + additionalProperties: false + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + description: + The list of IOs that properties in the pincfg node apply to. + + function: + description: + A string containing the name of the function to mux for these + pins. The "reserved" function tristates a pin. + enum: [ sd, emmc, qspi, spi, usb, uart, i2c, can, mdio, misc + reserved, gpio, fabric-test, tied-low, tied-high, tristate ] + + bias-bus-hold: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + low-power-enable: true + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 16, 20 ] + + power-source: + description: + Which bank voltage to use. This cannot differ for pins in a + given bank, the whole bank uses the same voltage. + enum: [ 1200000, 1500000, 1800000, 2500000, 3300000 ] + + microchip,clamp-diode: + $ref: /schemas/types.yaml#/definitions/flag + description: + Reflects the "Clamp Diode" setting in the MSS Configurator for + this pin. This setting controls whether or not input voltage + clamping should be enabled. + + microchip,ibufmd: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: + Reflects the "IBUFMD" bits in the MSS Configurator output files + for this pin. + + required: + - pins + - function + - power-source + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@204 { + compatible = "microchip,mpfs-pinctrl-mssio"; + reg = <0x204 0x7c>; + + ikrd-spi1-cfg { + spi1-pins { + pins = <30>, <31>, <32>, <33>; + function = "spi"; + bias-pull-up; + drive-strength = <8>; + power-source = <3300000>; + microchip,ibufmd = <0x1>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt new file mode 100644 index 000000000..51efd2085 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt @@ -0,0 +1,60 @@ +* Microchip PIC32 Pin Controller + +Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and +../interrupt-controller/interrupts.txt for generic information regarding +pin controller, GPIO, and interrupt bindings. + +PIC32 'pin configuration node' is a node of a group of pins which can be +used for a specific device or function. This node represents configurations of +pins, optional function, and optional mux related configuration. + +Required properties for pin controller node: + - compatible: "microchip,pic32mada-pinctrl" + - reg: Address range of the pinctrl registers. + - clocks: Clock specifier (see clock bindings for details) + +Required properties for pin configuration sub-nodes: + - pins: List of pins to which the configuration applies. + +Optional properties for pin configuration sub-nodes: +---------------------------------------------------- + - function: Mux function for the specified pins. + - bias-pull-up: Enable weak pull-up. + - bias-pull-down: Enable weak pull-down. + - input-enable: Set the pin as an input. + - output-low: Set the pin as an output level low. + - output-high: Set the pin as an output level high. + - microchip,digital: Enable digital I/O. + - microchip,analog: Enable analog I/O. + +Example: + +pic32_pinctrl: pinctrl@1f801400{ + #address-cells = <1>; + #size-cells = <1>; + compatible = "microchip,pic32mzda-pinctrl"; + reg = <0x1f801400 0x400>; + clocks = <&rootclk PB1CLK>; + + pinctrl_uart2: pinctrl_uart2 { + uart2-tx { + pins = "G9"; + function = "U2TX"; + microchip,digital; + output-low; + }; + uart2-rx { + pins = "B0"; + function = "U2RX"; + microchip,digital; + input-enable; + }; + }; +}; + +uart2: serial@1f822200 { + compatible = "microchip,pic32mzda-uart"; + reg = <0x1f822200 0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml new file mode 100644 index 000000000..e3792679d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PIC64GX GPIO2 Mux + +maintainers: + - Conor Dooley <conor.dooley@microchip.com> + +description: + The "GPIO2 Mux" determines whether GPIO2 or select other functions are + available on package pins on PIC64GX. Some of these functions must be + mapped to this mux via iomux0 for settings here to have any impact. + +properties: + compatible: + const: microchip,pic64gx-pinctrl-gpio2 + + reg: + maxItems: 1 + + pinctrl-use-default: true + +patternProperties: + '^mux-': + type: object + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, gpio ] + + groups: + description: + An array of strings. Each string contains the name of a group. + items: + enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, + gpio_mdio0, gpio_mdio1, gpio_spi0, gpio_can0, gpio_pcie, + gpio_qspi, gpio_uart3, gpio_uart4, gpio_can1, gpio_uart2 ] + + required: + - function + - groups + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@41000000 { + compatible = "microchip,pic64gx-pinctrl-gpio2"; + reg = <0x41000000 0x4>; + pinctrl-use-default; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_gpio2>, + <&uart3_gpio2>, <&uart4_gpio2>, <&can1_gpio2>, <&can0_gpio2>, + <&uart2_gpio2>; + + mux-gpio2 { + function = "gpio"; + groups = "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie", + "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml new file mode 100644 index 000000000..9fbbafcdc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi/Microchip Serial GPIO controller + +maintainers: + - Lars Povlsen <lars.povlsen@microchip.com> + +description: | + By using a serial interface, the SIO controller significantly extend + the number of available GPIOs with a minimum number of additional + pins on the device. The primary purpose of the SIO controllers is to + connect control signals from SFP modules and to act as an LED + controller. + +properties: + $nodename: + pattern: '^gpio@[0-9a-f]+$' + + compatible: + oneOf: + - enum: + - microchip,sparx5-sgpio + - mscc,ocelot-sgpio + - mscc,luton-sgpio + - items: + - enum: + - microchip,lan9691-sgpio + - const: microchip,sparx5-sgpio + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + microchip,sgpio-port-ranges: + description: This is a sequence of tuples, defining intervals of + enabled ports in the serial input stream. The enabled ports must + match the hardware configuration in order for signals to be + properly written/read to/from the controller holding + registers. Being tuples, then number of arguments must be + even. The tuples mast be ordered (low, high) and are + inclusive. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "low" indicates start bit number of range + minimum: 0 + maximum: 31 + - description: | + "high" indicates end bit number of range + minimum: 0 + maximum: 31 + minItems: 1 + maxItems: 32 + + bus-frequency: + description: The sgpio controller frequency (Hz). This dictates + the serial bitstream speed, which again affects the latency in + getting control signals back and forth between external shift + registers. The speed must be no larger than half the system + clock, and larger than zero. + default: 12500000 + + resets: + maxItems: 1 + + reset-names: + items: + - const: switch + +patternProperties: + '^gpio@[0-1]$': + type: object + properties: + compatible: + oneOf: + - items: + - enum: + - microchip,lan9691-sgpio-bank + - const: microchip,sparx5-sgpio-bank + - const: microchip,sparx5-sgpio-bank + + reg: + description: | + The GPIO bank number. "0" is designates the input pin bank, + "1" the output bank. + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + description: | + Specifies the pin (port and bit) and flags. Note that the + SGIO pin is defined by *2* numbers, a port number between 0 + and 31, and a bit index, 0 to 3. The maximum bit number is + controlled indirectly by the "ngpios" property: (ngpios/32). + const: 3 + + interrupts: + description: Specifies the sgpio IRQ (in parent controller) + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the pin (port and bit) and flags, as defined in + defined in include/dt-bindings/interrupt-controller/irq.h + const: 3 + + ngpios: + description: The numbers of GPIO's exposed. This must be a + multiple of 32. + minimum: 32 + maximum: 128 + + required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - ngpios + + additionalProperties: false + +additionalProperties: false + +required: + - compatible + - reg + - clocks + - microchip,sgpio-port-ranges + - '#address-cells' + - '#size-cells' + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + sgpio2: gpio@1101059c { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microchip,sparx5-sgpio"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x1101059c 0x118>; + microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>; + bus-frequency = <25000000>; + sgpio_in2: gpio@0 { + reg = <0>; + compatible = "microchip,sparx5-sgpio-bank"; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + }; + sgpio_out2: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <96>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml new file mode 100644 index 000000000..930955caa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsemi Ocelot pin controller + +maintainers: + - Alexandre Belloni <alexandre.belloni@bootlin.com> + - Lars Povlsen <lars.povlsen@microchip.com> + +properties: + compatible: + oneOf: + - enum: + - microchip,lan96455f-pinctrl + - microchip,lan966x-pinctrl + - microchip,lan9691-pinctrl + - microchip,sparx5-pinctrl + - mscc,jaguar2-pinctrl + - mscc,luton-pinctrl + - mscc,ocelot-pinctrl + - mscc,serval-pinctrl + - mscc,servalt-pinctrl + - items: + - enum: + - microchip,lan9698-pinctrl + - microchip,lan9696-pinctrl + - microchip,lan9694-pinctrl + - microchip,lan9693-pinctrl + - microchip,lan9692-pinctrl + - const: microchip,lan9691-pinctrl + - items: + - enum: + - microchip,lan96457f-pinctrl + - microchip,lan96459f-pinctrl + - const: microchip,lan96455f-pinctrl + + reg: + items: + - description: Base address + - description: Extended pin configuration registers + minItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: true + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + resets: + maxItems: 1 + + reset-names: + description: Optional shared switch reset. + items: + - const: switch + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pinmux-node.yaml + - $ref: pincfg-node.yaml + + properties: + function: true + pins: true + output-high: true + output-low: true + drive-strength: true + + required: + - function + - pins + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + enum: + - microchip,lan966x-pinctrl + - microchip,lan9691-pinctrl + - microchip,sparx5-pinctrl + then: + properties: + reg: + minItems: 2 + +additionalProperties: false + +examples: + - | + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + reg = <0x71070034 0x28>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + + uart_pins: uart-pins { + pins = "GPIO_6", "GPIO_7"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_12", "GPIO_13"; + function = "uart2"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml new file mode 100644 index 000000000..763a49bd0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 pin control and GPIO + +maintainers: + - Shan-Chun Hung <schung@nuvoton.com> + - Jacky Huang <ychuang3@nuvoton.com> + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - nuvoton,ma35d1-pinctrl + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + nuvoton,sys: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the system-management node. + + ranges: true + +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: + The interrupt outputs to sysirq. + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - reg + - clocks + - interrupt-controller + - '#interrupt-cells' + - interrupts + + additionalProperties: false + + "-grp$": + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + patternProperties: + "-pins$": + type: object + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + nuvoton,pins: + description: + Each entry consists of 4 parameters and represents the mux and config + setting for one pin. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + items: + items: + - minimum: 0 + maximum: 13 + description: + Pin bank. + - minimum: 0 + maximum: 15 + description: + Pin bank index. + - minimum: 0 + maximum: 15 + description: + Mux 0 means GPIO and mux 1 to 15 means the specific device function. + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + drive-strength-microamp: + oneOf: + - enum: [ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000 ] + description: 1.8V I/O driving strength + - enum: [ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000 ] + description: 3.3V I/O driving strength + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-schmitt-disable: true + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - nuvoton,sys + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + + pinctrl@40040000 { + compatible = "nuvoton,ma35d1-pinctrl"; + reg = <0x40040000 0xc00>; + #address-cells = <1>; + #size-cells = <1>; + nuvoton,sys = <&sys>; + ranges = <0x0 0x40040000 0x400>; + + gpio@0 { + reg = <0x0 0x40>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk GPA_GATE>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart-grp { + uart11-pins { + nuvoton,pins = <11 0 2>, + <11 1 2>, + <11 2 2>, + <11 3 2>; + power-source = <1>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt new file mode 100644 index 000000000..a1264cc86 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm7xx-pinctrl.txt @@ -0,0 +1,216 @@ +Nuvoton NPCM7XX Pin Controllers + +The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through +the multiplexing block, Each pin supports GPIO functionality (GPIOx) +and multiple functions that directly connect the pin to different +hardware blocks. + +Required properties: +- #address-cells : should be 1. +- #size-cells : should be 1. +- compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX. +- ranges : defines mapping ranges between pin controller node (parent) + to GPIO bank node (children). + +=== GPIO Bank Subnode === + +The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO. + +Required GPIO Bank subnode-properties: +- reg : specifies physical base address and size of the GPIO + bank registers. +- gpio-controller : Marks the device node as a GPIO controller. +- #gpio-cells : Must be <2>. The first cell is the gpio pin number + and the second cell is used for optional parameters. +- interrupts : contain the GPIO bank interrupt with flags for falling edge. +- gpio-ranges : defines the range of pins managed by the GPIO bank controller. + +For example, GPIO bank subnodes like the following: + gpio0: gpio@f0010000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + +=== Pin Mux Subnode === + +- pin: A string containing the name of the pin + An array of strings, each string containing the name of a pin. + These pin are used for selecting pin configuration. + +The following are the list of pins available: + "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0", + "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL", "GPIO6/IOX2CK/SMB2DSDA", + "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2", "GPIO10/IOXHLD", + "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA", + "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0", + "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA", "GPIO19/PSPI2CK/SMB4BSCL", + "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL", "GPIO22/SMB4DSDA/SMB14SDA", + "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI", "GPIO26/SMB5SDA", + "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA", + "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3", "GPIO37/SMB3CSDA", + "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL", "GPIO41/BSPRXD", + "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD", "GPIO44/nCTS1/JTDI2/BU1CTS", + "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2", + "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2", "GPO51/nRTS2/STRAP2", + "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2", "GPIO55/nRI2", + "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA", + "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5", + "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2", + "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6", "GPIO71/FANIN7", + "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11", + "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15", + "GPIO80/PWM0", "GPIO81/PWM1", "GPIO82/PWM2", "GPIO83/PWM3", "GPIO84/R2TXD0", + "GPIO85/R2TXD1", "GPIO86/R2TXEN", "GPIO87/R2RXD0", "GPIO88/R2RXD1", "GPIO89/R2CRSDV", + "GPIO90/R2RXERR", "GPIO91/R2MDC", "GPIO92/R2MDIO", "GPIO93/GA20/SMB5DSCL", + "GPIO94/nKBRST/SMB5DSDA", "GPIO95/nLRESET/nESPIRST", "GPIO96/RG1TXD0", + "GPIO97/RG1TXD1", "GPIO98/RG1TXD2", "GPIO99/RG1TXD3","GPIO100/RG1TXC", + "GPIO101/RG1TXCTL", "GPIO102/RG1RXD0", "GPIO103/RG1RXD1", "GPIO104/RG1RXD2", + "GPIO105/RG1RXD3", "GPIO106/RG1RXC", "GPIO107/RG1RXCTL", "GPIO108/RG1MDC", + "GPIO109/RG1MDIO", "GPIO110/RG2TXD0/DDRV0", "GPIO111/RG2TXD1/DDRV1", + "GPIO112/RG2TXD2/DDRV2", "GPIO113/RG2TXD3/DDRV3", "GPIO114/SMB0SCL", + "GPIO115/SMB0SDA", "GPIO116/SMB1SCL", "GPIO117/SMB1SDA", "GPIO118/SMB2SCL", + "GPIO119/SMB2SDA", "GPIO120/SMB2CSDA", "GPIO121/SMB2CSCL", "GPIO122/SMB2BSDA", + "GPIO123/SMB2BSCL", "GPIO124/SMB1CSDA", "GPIO125/SMB1CSCL","GPIO126/SMB1BSDA", + "GPIO127/SMB1BSCL", "GPIO128/SMB8SCL", "GPIO129/SMB8SDA", "GPIO130/SMB9SCL", + "GPIO131/SMB9SDA", "GPIO132/SMB10SCL", "GPIO133/SMB10SDA","GPIO134/SMB11SCL", + "GPIO135/SMB11SDA", "GPIO136/SD1DT0", "GPIO137/SD1DT1", "GPIO138/SD1DT2", + "GPIO139/SD1DT3", "GPIO140/SD1CLK", "GPIO141/SD1WP", "GPIO142/SD1CMD", + "GPIO143/SD1CD/SD1PWR", "GPIO144/PWM4", "GPIO145/PWM5", "GPIO146/PWM6", + "GPIO147/PWM7", "GPIO148/MMCDT4", "GPIO149/MMCDT5", "GPIO150/MMCDT6", + "GPIO151/MMCDT7", "GPIO152/MMCCLK", "GPIO153/MMCWP", "GPIO154/MMCCMD", + "GPIO155/nMMCCD/nMMCRST", "GPIO156/MMCDT0", "GPIO157/MMCDT1", "GPIO158/MMCDT2", + "GPIO159/MMCDT3", "GPIO160/CLKOUT/RNGOSCOUT", "GPIO161/nLFRAME/nESPICS", + "GPIO162/SERIRQ", "GPIO163/LCLK/ESPICLK", "GPIO164/LAD0/ESPI_IO0", + "GPIO165/LAD1/ESPI_IO1", "GPIO166/LAD2/ESPI_IO2", "GPIO167/LAD3/ESPI_IO3", + "GPIO168/nCLKRUN/nESPIALERT", "GPIO169/nSCIPME", "GPIO170/nSMI", "GPIO171/SMB6SCL", + "GPIO172/SMB6SDA", "GPIO173/SMB7SCL", "GPIO174/SMB7SDA", "GPIO175/PSPI1CK/FANIN19", + "GPIO176/PSPI1DO/FANIN18", "GPIO177/PSPI1DI/FANIN17", "GPIO178/R1TXD0", + "GPIO179/R1TXD1", "GPIO180/R1TXEN", "GPIO181/R1RXD0", "GPIO182/R1RXD1", + "GPIO183/SPI3CK", "GPO184/SPI3D0/STRAP9", "GPO185/SPI3D1/STRAP10", + "GPIO186/nSPI3CS0", "GPIO187/nSPI3CS1", "GPIO188/SPI3D2/nSPI3CS2", + "GPIO189/SPI3D3/nSPI3CS3", "GPIO190/nPRD_SMI", "GPIO191", "GPIO192", "GPIO193/R1CRSDV", + "GPIO194/SMB0BSCL", "GPIO195/SMB0BSDA", "GPIO196/SMB0CSCL", "GPIO197/SMB0DEN", + "GPIO198/SMB0DSDA", "GPIO199/SMB0DSCL", "GPIO200/R2CK", "GPIO201/R1CK", + "GPIO202/SMB0CSDA", "GPIO203/FANIN16", "GPIO204/DDC2SCL", "GPIO205/DDC2SDA", + "GPIO206/HSYNC2", "GPIO207/VSYNC2", "GPIO208/RG2TXC/DVCK", "GPIO209/RG2TXCTL/DDRV4", + "GPIO210/RG2RXD0/DDRV5", "GPIO211/RG2RXD1/DDRV6", "GPIO212/RG2RXD2/DDRV7", + "GPIO213/RG2RXD3/DDRV8", "GPIO214/RG2RXC/DDRV9", "GPIO215/RG2RXCTL/DDRV10", + "GPIO216/RG2MDC/DDRV11", "GPIO217/RG2MDIO/DVHSYNC", "GPIO218/nWDO1", + "GPIO219/nWDO2", "GPIO220/SMB12SCL", "GPIO221/SMB12SDA", "GPIO222/SMB13SCL", + "GPIO223/SMB13SDA", "GPIO224/SPIXCK", "GPO225/SPIXD0/STRAP12", "GPO226/SPIXD1/STRAP13", + "GPIO227/nSPIXCS0", "GPIO228/nSPIXCS1", "GPO229/SPIXD2/STRAP3", "GPIO230/SPIXD3", + "GPIO231/nCLKREQ", "GPI255/DACOSEL" + +Optional Properties: + bias-disable, bias-pull-down, bias-pull-up, input-enable, + input-disable, output-high, output-low, drive-push-pull, + drive-open-drain, input-debounce, slew-rate, drive-strength + + slew-rate valid arguments are: + <0> - slow + <1> - fast + drive-strength valid arguments are: + <2> - 2mA + <4> - 4mA + <8> - 8mA + <12> - 12mA + <16> - 16mA + <24> - 24mA + +For example, pinctrl might have pinmux subnodes like the following: + + gpio0_iox1d1_pin: gpio0-iox1d1-pin { + pins = "GPIO0/IOX1DI"; + output-high; + }; + gpio0_iox1ck_pin: gpio0-iox1ck-pin { + pins = "GPIO2/IOX1CK"; + output_high; + }; + +=== Pin Group Subnode === + +Required pin group subnode-properties: +- groups : A string containing the name of the group to mux. +- function: A string containing the name of the function to mux to the + group. + +The following are the list of the available groups and functions : + smb0, smb0b, smb0c, smb0d, smb0den, smb1, smb1b, smb1c, smb1d, + smb2, smb2b, smb2c, smb2d, smb3, smb3b, smb3c, smb3d, smb4, smb4b, + smb4c, smb4d, smb4den, smb5, smb5b, smb5c, smb5d, ga20kbc, smb6, + smb7, smb8, smb9, smb10, smb11, smb12, smb13, smb14, smb15, fanin0, + fanin1, fanin2, fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, + fanin9, fanin10, fanin11 fanin12 fanin13, fanin14, fanin15, faninx, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, rg1, rg1mdio, rg2, + rg2mdio, ddr, uart1, uart2, bmcuart0a, bmcuart0b, bmcuart1, iox1, + iox2, ioxh, gspi, mmc, mmcwp, mmccd, mmcrst, mmc8, r1, r1err, r1md, + r2, r2err, r2md, sd1, sd1pwr, wdog1, wdog2, scipme, sci, serirq, + jtag2, spix, spixcs1, pspi1, pspi2, ddc, clkreq, clkout, spi3, spi3cs1, + spi3quad, spi3cs2, spi3cs3, spi0cs1, lpc, lpcclk, espi, lkgpo0, lkgpo1, + lkgpo2, nprd_smi + +For example, pinctrl might have group subnodes like the following: + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + r1_pins: r1-pins { + groups = "r1"; + function = "r1"; + }; + +Examples +======== +pinctrl: pinctrl@f0800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nuvoton,npcm750-pinctrl"; + ranges = <0 0xf0010000 0x8000>; + + gpio0: gpio@f0010000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + .... + + gpio7: gpio@f0017000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x7000 0x80>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 224 32>; + }; + + gpio0_iox1d1_pin: gpio0-iox1d1-pin { + pins = "GPIO0/IOX1DI"; + output-high; + }; + + iox1_pins: iox1-pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-pins { + groups = "iox2"; + function = "iox2"; + }; + + .... + + clkreq_pins: clkreq-pins { + groups = "clkreq"; + function = "clkreq"; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml new file mode 100644 index 000000000..8cd1f4422 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,npcm845-pinctrl.yaml @@ -0,0 +1,215 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM845 Pin Controller and GPIO + +maintainers: + - Tomer Maimon <tmaimon77@gmail.com> + +description: + The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through + the multiplexing block, Each pin supports GPIO functionality (GPIOx) + and multiple functions that directly connect the pin to different + hardware blocks. + +properties: + compatible: + const: nuvoton,npcm845-pinctrl + + ranges: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + nuvoton,sysgcr: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to access GCR registers. + +patternProperties: + '^gpio@': + type: object + additionalProperties: false + + description: + Eight GPIO banks that each contain 32 GPIOs. + + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-ranges: + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - reg + - interrupts + - gpio-ranges + + '-mux$': + $ref: pinmux-node.yaml# + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, + smb5b, smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, + smb16, smb17, smb18, smb19, smb20, smb21, smb22, smb23, + smb23b, smb4d, smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, + spi0cs3, spi1cs0, spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, + smb3b, bmcuart0a, uart1, jtag2, bmcuart1, uart2, sg1mdio, + bmcuart0b, r1err, r1md, r1oen, r2oen, rmii3, r3oen, smb3d, + fanin0, fanin1, fanin2, fanin3, fanin4, fanin5, fanin6, + fanin7, fanin8, fanin9, fanin10, fanin11, fanin12, fanin13, + fanin14, fanin15, pwm0, pwm1, pwm2, pwm3, r2, r2err, r2md, + r3rxer, ga20kbc, smb5d, lpc, espi, rg2, ddr, i3c0, i3c1, + i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, smb2c, smb2b, smb1c, + smb1b, smb8, smb9, smb10, smb11, sd1, sd1pwr, pwm4, pwm5, + pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, mmc8, mmc, mmcwp, mmccd, + mmcrst, clkout, serirq, scipme, smi, smb6, smb6b, smb6c, + smb6d, smb7, smb7b, smb7c, smb7d, spi1, faninx, r1, spi3, + spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, smb0b, smb0c, + smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, smb12, smb13, + spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, hgpio3, hgpio4, + hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, bu6, gpo187 ] + + function: + description: + The function that a group of pins is muxed to + enum: [ iox1, iox2, smb1d, smb2d, lkgpo1, lkgpo2, ioxh, gspi, smb5b, + smb5c, lkgpo0, pspi, jm1, jm2, smb4b, smb4c, smb15, smb16, + smb17, smb18, smb19, smb20, smb21, smb22, smb23, smb23b, smb4d, + smb14, smb5, smb4, smb3, spi0cs1, spi0cs2, spi0cs3, spi1cs0, + spi1cs1, spi1cs2, spi1cs3, spi1cs23, smb3c, smb3b, bmcuart0a, + uart1, jtag2, bmcuart1, uart2, sg1mdio, bmcuart0b, r1err, r1md, + r1oen, r2oen, rmii3, r3oen, smb3d, fanin0, fanin1, fanin2, + fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, fanin9, fanin10, + fanin11, fanin12, fanin13, fanin14, fanin15, pwm0, pwm1, pwm2, + pwm3, r2, r2err, r2md, r3rxer, ga20kbc, smb5d, lpc, espi, rg2, + ddr, i3c0, i3c1, i3c2, i3c3, i3c4, i3c5, smb0, smb1, smb2, + smb2c, smb2b, smb1c, smb1b, smb8, smb9, smb10, smb11, sd1, + sd1pwr, pwm4, pwm5, pwm6, pwm7, pwm8, pwm9, pwm10, pwm11, + mmc8, mmc, mmcwp, mmccd, mmcrst, clkout, serirq, scipme, smi, + smb6, smb6b, smb6c, smb6d, smb7, smb7b, smb7c, smb7d, spi1, + faninx, r1, spi3, spi3cs1, spi3quad, spi3cs2, spi3cs3, nprd_smi, + smb0b, smb0c, smb0den, smb0d, ddc, rg2mdio, wdog1, wdog2, + smb12, smb13, spix, spixcs1, clkreq, hgpio0, hgpio1, hgpio2, + hgpio3, hgpio4, hgpio5, hgpio6, hgpio7, bu4, bu4b, bu5, bu5b, + bu6, gpo187 ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + '^pin': + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + items: + pattern: '^GPIO([0-9]|[0-9][0-9]|1[0-9][0-9]|2[0-4][0-9]|25[0-6])' + + bias-disable: true + + bias-pull-up: true + + bias-pull-down: true + + input-enable: true + + output-low: true + + output-high: true + + drive-push-pull: true + + drive-open-drain: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + minItems: 1 + maxItems: 4 + + slew-rate: + description: | + 0: Low rate + 1: High rate + enum: [0, 1] + + drive-strength: + enum: [ 0, 1, 2, 4, 8, 12 ] + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - ranges + - '#address-cells' + - '#size-cells' + - nuvoton,sysgcr + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@f0010000 { + compatible = "nuvoton,npcm845-pinctrl"; + ranges = <0x0 0x0 0xf0010000 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + nuvoton,sysgcr = <&gcr>; + + gpio0: gpio@0 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0xb0>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + fanin0_pin: fanin0-mux { + groups = "fanin0"; + function = "fanin0"; + }; + + pin34_slew: pin34-slew { + pins = "GPIO34/I3C4_SDA"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 000000000..08442c880 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer <j.neuschaefer@gmx.net> + +properties: + compatible: + const: nuvoton,wpcm450-pinctrl + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + # There are three kinds of subnodes: + # 1. a GPIO controller node for each GPIO bank + # 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 3. a pinconf node configures properties of a single pin + + "^gpio@[0-7]$": + type: object + additionalProperties: false + + description: + Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18 + GPIOs. Some GPIOs support interrupts. + + properties: + reg: + minimum: 0 + maximum: 7 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 3 + description: + The interrupts associated with this GPIO bank + + required: + - reg + - gpio-controller + - '#gpio-cells' + + "^mux-": + $ref: pinmux-node.yaml# + + properties: + groups: + description: + One or more groups of pins to mux to a certain function + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7, gpio ] + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + + "^cfg-": + $ref: pincfg-node.yaml# + + properties: + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + items: + pattern: "^gpio1?[0-9]{1,2}$" + + input-debounce: + maxItems: 1 + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + gpio0: gpio@0 { + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, + <3 IRQ_TYPE_LEVEL_HIGH>, + <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + mux-rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinmux_uid: mux-uid { + groups = "gspi", "sspi"; + function = "gpio"; + }; + + pinctrl_uid: cfg-uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>; + + button-uid { + label = "UID"; + linux,code = <102>; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml new file mode 100644 index 000000000..96c608bcb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-pinmux-common.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +description: | + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of + the phrase "pin configuration node". + + Tegra's pin configuration nodes act as a container for an arbitrary number + of subnodes. Each of these subnodes represents some desired configuration + for a pin, a group, or a list of pins or groups. This configuration can + include the mux function to select on those pin(s)/ group(s), and various + pin configuration parameters, such as pull-up, tristate, drive strength, + etc. + + The name of each subnode is not important; all subnodes should be + enumerated and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function or tristate parameter. For this + reason, even seemingly boolean values are actually tristates in this + binding: unspecified, off, or on. Unspecified is represented as an absent + property, and off/on are represented as integer values 0 and 1. + + Note that many of these properties are only valid for certain specific pins + or groups. See the Tegra TRM and various pinmux spreadsheets for complete + details regarding which groups support which functionality. The Linux + pinctrl driver may also be a useful reference, since it consolidates, + disambiguates, and corrects data from all those sources. + +properties: + nvidia,pins: + $ref: /schemas/types.yaml#/definitions/string-array + description: An array of strings. Each string contains the name of a pin + or group. Valid values for these names are listed below. + + nvidia,function: + $ref: /schemas/types.yaml#/definitions/string + description: A string containing the name of the function to mux to the + pin or group. Valid values for function names are listed below. See the + Tegra TRM to determine which are valid for each pin or group. + + nvidia,pull: + description: Pull-down/up setting to apply to the pin. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: none + const: 0 + - description: down + const: 1 + - description: up + const: 2 + + nvidia,tristate: + description: Tristate setting to apply to the pin. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: drive + const: 0 + - description: tristate + const: 1 + + nvidia,schmitt: + description: Enable Schmitt trigger on the input. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: disable Schmitt trigger on the input + const: 0 + - description: enable Schmitt trigger on the input + const: 1 + + nvidia,pull-down-strength: + description: Controls drive strength. 0 is weakest. The range of valid + values depends on the pingroup. See "CAL_DRVDN" in the Tegra TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,pull-up-strength: + description: Controls drive strength. 0 is weakest. The range of valid + values depends on the pingroup. See "CAL_DRVUP" in the Tegra TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,high-speed-mode: + description: Enable high speed mode the pins. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: normal speed mode + const: 0 + - description: high speed mode + const: 1 + + nvidia,low-power-mode: + description: Controls the drive power or current. Valid values are from 0 + through 3, where 0 specifies the least power and 3 specifies the most + power. See "Low Power Mode" or "LPMD1" and "LPMD0" in the Tegra TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + nvidia,enable-input: + description: Enable the pin's input path. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: disable input (i.e. output only) + const: 0 + - description: enable input + const: 1 + + nvidia,open-drain: + description: Open-drain configuration for the pin. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: disable open-drain + const: 0 + - description: enable open-drain + const: 1 + + nvidia,lock: + description: Lock the pin configuration against further changes until + reset. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: disable pin configuration lock + const: 0 + - description: enable pin configuration lock + const: 1 + + nvidia,io-reset: + description: reset the I/O path + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + + nvidia,rcv-sel: + description: select VIL/VIH receivers + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: normal receivers + const: 0 + - description: high-voltage receivers + const: 1 + + nvidia,drive-type: + description: Drive type to configure for the pin. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + nvidia,io-hv: + description: Select high-voltage receivers. + $ref: /schemas/types.yaml#/definitions/uint32 + oneOf: + - description: Use normal receivers. + const: 0 + - description: Use high-voltage receivers. + const: 1 + + nvidia,slew-rate-rising: + description: Controls rising signal slew rate. 0 is fastest. The range of + valid values depends on the pingroup. See "DRVDN_SLWR" in the Tegra TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + + nvidia,slew-rate-falling: + description: Controls falling signal slew rate. 0 is fastest. The range of + valid values depends on the pingroup. See "DRVUP_SLWF" in the Tegra TRM. + $ref: /schemas/types.yaml#/definitions/uint32 + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml new file mode 100644 index 000000000..1690c0ef5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra114-pinmux.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra114-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra114 pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra114-pinmux + + reg: + items: + - description: pad control registers + - description: mux registers + +patternProperties: + "^pinmux(-[a-z0-9-_]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + additionalProperties: false + properties: + nvidia,pins: + items: + enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, + ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, + ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1, + ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1, + dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, + sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, + sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5, + clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5, + uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, + uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, + uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, + pu5, pu6, gen1_i2c_sda_pc5, gen1_i2c_scl_pc4, dap4_fs_pp4, + dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0, + clk3_req_pee1, gmi_wp_n_pc7, gmi_iordy_pi5, gmi_wait_pi7, + gmi_adv_n_pk0, gmi_clk_pk1, gmi_cs0_n_pj0, gmi_cs1_n_pj2, + gmi_cs2_n_pk3, gmi_cs3_n_pk4, gmi_cs4_n_pk2, gmi_cs6_n_pi3, + gmi_cs7_n_pi6, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2, + gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6, + gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2, + gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, + gmi_ad15_ph7, gmi_a16_pj7, gmi_a17_pb0, gmi_a18_pb1, + gmi_a19_pk7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_p_pj3, + gmi_rst_n_pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, + sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, + sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, + sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, + sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, + cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, + pbb7, pcc2, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, kb_row0_pr0, + kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, + kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, kb_row8_ps0, + kb_row9_ps1, kb_row10_ps2, kb_col0_pq0, kb_col1_pq1, + kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, + kb_col6_pq6, kb_col7_pq7, clk_32k_out_pa0, sys_clk_req_pz5, + core_pwr_req, cpu_pwr_req, pwr_int_n, owr, dap1_fs_pn0, + dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, clk1_req_pee2, + clk1_out_pw4, spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, + dap2_din_pa4, dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0, + gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, + gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, + gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, + sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5, + sdmmc3_dat3_pb4, hdmi_cec_pee3, sdmmc1_wp_n_pv3, + sdmmc3_cd_n_pv2, gpio_w2_aud_pw2, gpio_w3_aud_pw3, + usb_vbus_en0_pn4, usb_vbus_en1_pn5, sdmmc3_clk_lb_in_pee5, + sdmmc3_clk_lb_out_pee4, reset_out_n, + # drive groups + drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3, + drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1, + drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3, + drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3, + drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf, + drive_gmg, drive_gmh, drive_owr, drive_uda ] + + nvidia,function: + enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, + displaya, displaya_alt, displayb, dtv, emc_dll, extperiph1, + extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, + i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, + nand, nand_alt, owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, + reset_out_n, rsvd1, rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, + sdmmc3, sdmmc4, soc, spdif, spi1, spi2, spi3, spi4, spi5, + spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, usb, + vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt3 ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,pull-down-strength: true + nvidia,pull-up-strength: true + nvidia,high-speed-mode: true + nvidia,low-power-mode: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,io-reset: true + nvidia,rcv-sel: true + nvidia,drive-type: true + nvidia,slew-rate-rising: true + nvidia,slew-rate-falling: true + + required: + - nvidia,pins + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + pinmux@70000868 { + compatible = "nvidia,tegra114-pinmux"; + reg = <0x70000868 0x148>, /* Pad control registers */ + <0x70003000 0x40c>; /* PinMux registers */ + + pinmux { + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml new file mode 100644 index 000000000..9b7368bd3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-pinmux.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra124-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra124 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: The Tegra124 pinctrl binding is very similar to the Tegra20 and + Tegra30 pinctrl binding, as described in nvidia,tegra20-pinmux.yaml and + nvidia,tegra30-pinmux.yaml. In fact, this document assumes that binding as a + baseline, and only documents the differences between the two bindings. + +properties: + compatible: + oneOf: + - const: nvidia,tegra124-pinmux + - items: + - const: nvidia,tegra132-pinmux + - const: nvidia,tegra124-pinmux + + reg: + items: + - description: driver strength and pad control registers + - description: pinmux registers + - description: MIPI_PAD_CTRL registers + +patternProperties: + "^pinmux(-[a-z0-9-_]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + additionalProperties: false + properties: + nvidia,pins: + $ref: /schemas/types.yaml#/definitions/string-array + items: + enum: [ ulpi_data0_po1, ulpi_data1_po2, ulpi_data2_po3, + ulpi_data3_po4, ulpi_data4_po5, ulpi_data5_po6, + ulpi_data6_po7, ulpi_data7_po0, ulpi_clk_py0, ulpi_dir_py1, + ulpi_nxt_py2, ulpi_stp_py3, dap3_fs_pp0, dap3_din_pp1, + dap3_dout_pp2, dap3_sclk_pp3, pv0, pv1, sdmmc1_clk_pz0, + sdmmc1_cmd_pz1, sdmmc1_dat3_py4, sdmmc1_dat2_py5, + sdmmc1_dat1_py6, sdmmc1_dat0_py7, clk2_out_pw5, + clk2_req_pcc5, hdmi_int_pn7, ddc_scl_pv4, ddc_sda_pv5, + uart2_rxd_pc3, uart2_txd_pc2, uart2_rts_n_pj6, + uart2_cts_n_pj5, uart3_txd_pw6, uart3_rxd_pw7, + uart3_cts_n_pa1, uart3_rts_n_pc0, pu0, pu1, pu2, pu3, pu4, + pu5, pu6, gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, dap4_fs_pp4, + dap4_din_pp5, dap4_dout_pp6, dap4_sclk_pp7, clk3_out_pee0, + clk3_req_pee1, pc7, pi5, pi7, pk0, pk1, pj0, pj2, pk3, pk4, + pk2, pi3, pi6, pg0, pg1, pg2, pg3, pg4, pg5, pg6, pg7, ph0, + ph1, ph2, ph3, ph4, ph5, ph6, ph7, pj7, pb0, pb1, pk7, pi0, + pi1, pi2, pi4, gen2_i2c_scl_pt5, gen2_i2c_sda_pt6, + sdmmc4_clk_pcc4, sdmmc4_cmd_pt7, sdmmc4_dat0_paa0, + sdmmc4_dat1_paa1, sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, + sdmmc4_dat4_paa4, sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, + sdmmc4_dat7_paa7, cam_mclk_pcc0, pcc1, pbb0, + cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, + pbb7, pcc2, jtag_rtck, pwr_i2c_scl_pz6, pwr_i2c_sda_pz7, + kb_row0_pr0, kb_row1_pr1, kb_row2_pr2, kb_row3_pr3, + kb_row4_pr4, kb_row5_pr5, kb_row6_pr6, kb_row7_pr7, + kb_row8_ps0, kb_row9_ps1, kb_row10_ps2, kb_row11_ps3, + kb_row12_ps4, kb_row13_ps5, kb_row14_ps6, kb_row15_ps7, + kb_col0_pq0, kb_col1_pq1, kb_col2_pq2, kb_col3_pq3, + kb_col4_pq4, kb_col5_pq5, kb_col6_pq6, kb_col7_pq7, + clk_32k_out_pa0, core_pwr_req, cpu_pwr_req, pwr_int_n, + clk_32k_in, owr, dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, + dap1_sclk_pn3, dap_mclk1_req_pee2, dap_mclk1_pw4, + spdif_in_pk6, spdif_out_pk5, dap2_fs_pa2, dap2_din_pa4, + dap2_dout_pa5, dap2_sclk_pa3, dvfs_pwm_px0, + gpio_x1_aud_px1, gpio_x3_aud_px3, dvfs_clk_px2, + gpio_x4_aud_px4, gpio_x5_aud_px5, gpio_x6_aud_px6, + gpio_x7_aud_px7, sdmmc3_clk_pa6, sdmmc3_cmd_pa7, + sdmmc3_dat0_pb7, sdmmc3_dat1_pb6, sdmmc3_dat2_pb5, + sdmmc3_dat3_pb4, pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, + pex_wake_n_pdd3, pex_l1_rst_n_pdd5, pex_l1_clkreq_n_pdd6, + hdmi_cec_pee3, sdmmc1_wp_n_pv3, sdmmc3_cd_n_pv2, + gpio_w2_aud_pw2, gpio_w3_aud_pw3, usb_vbus_en0_pn4, + usb_vbus_en1_pn5, sdmmc3_clk_lb_out_pee4, + sdmmc3_clk_lb_in_pee5, gmi_clk_lb, reset_out_n, + kb_row16_pt0, kb_row17_pt1, usb_vbus_en2_pff1, pff2, + dp_hpd_pff0, + # drive groups + drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3, + drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_dap1, + drive_dap2, drive_dap3, drive_dap4, drive_dbg, drive_sdio3, + drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3, + drive_sdio1, drive_ddc, drive_gma, drive_gme, drive_gmf, + drive_gmg, drive_gmh, drive_owr, drive_uda, drive_gpv, + drive_dev3, drive_cec, drive_usb_vbus_en, drive_ao3, + drive_ao0, drive_hv0, drive_sdio4, drive_ao4, + # MIPI pad control groups + mipi_pad_ctrl_dsi_b ] + + nvidia,function: + enum: [ blink, cec, cldvfs, clk12, cpu, dap, dap1, dap2, dev3, + displaya, displaya_alt, displayb, dtv, extperiph1, + extperiph2, extperiph3, gmi, gmi_alt, hda, hsi, i2c1, i2c2, + i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, i2s3, i2s4, irda, kbc, + owr, pmi, pwm0, pwm1, pwm2, pwm3, pwron, reset_out_n, rsvd1, + rsvd2, rsvd3, rsvd4, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, + spdif, spi1, spi2, spi3, spi4, spi5, spi6, trace, uarta, + uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5, + vgp6, vi, vi_alt1, vi_alt3, vimclk2, vimclk2_alt, sata, ccla, + pe0, pe, pe1, dp, rtck, sys, clk, tmds, csi, dsi_b ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,pull-down-strength: true + nvidia,pull-up-strength: true + nvidia,high-speed-mode: true + nvidia,low-power-mode: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,io-reset: true + nvidia,rcv-sel: true + nvidia,drive-type: true + nvidia,slew-rate-rising: true + nvidia,slew-rate-falling: true + + required: + - nvidia,pins + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/clock/tegra124-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@70000868 { + compatible = "nvidia,tegra124-pinmux"; + reg = <0x70000868 0x164>, /* Pad control registers */ + <0x70003000 0x434>, /* Mux registers */ + <0x70000820 0x8>; /* MIPI pad control */ + + sdmmc4_default: pinmux { + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt new file mode 100644 index 000000000..02e971c39 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt @@ -0,0 +1,135 @@ +Device tree binding for NVIDIA Tegra XUSB pad controller +======================================================== + +NOTE: It turns out that this binding isn't an accurate description of the XUSB +pad controller. While the description is good enough for the functional subset +required for PCIe and SATA, it lacks the flexibility to represent the features +needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt. +The binding described in this file is deprecated and should not be used. + +The Tegra XUSB pad controller manages a set of lanes, each of which can be +assigned to one out of a set of different pads. Some of these pads have an +associated PHY that must be powered up before the pad can be used. + +This document defines the device-specific binding for the XUSB pad controller. + +Refer to pinctrl-bindings.txt in this directory for generic information about +pin controller device tree bindings and ../phy/phy-bindings.txt for details on +how to describe and reference PHYs in device trees. + +Required properties: +-------------------- +- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl". + Otherwise, must contain '"nvidia,<chip>-xusb-padctl", + "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210. +- reg: Physical base address and length of the controller's registers. +- resets: Must contain an entry for each entry in reset-names. + See ../reset/reset.txt for details. +- reset-names: Must include the following entries: + - padctl +- #phy-cells: Should be 1. The specifier is the index of the PHY to reference. + See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values. + +Lane muxing: +------------ + +Child nodes contain the pinmux configurations following the conventions from +the pinctrl-bindings.txt document. Typically a single, static configuration is +given and applied at boot time. + +Each subnode describes groups of lanes along with parameters and pads that +they should be assigned to. The name of these subnodes is not important. All +subnodes should be parsed solely based on their content. + +Each subnode only applies the parameters that are explicitly listed. In other +words, if a subnode that lists a function but no pin configuration parameters +implies no information about any pin configuration parameters. Similarly, a +subnode that describes only an IDDQ parameter implies no information about +what function the pins are assigned to. For this reason even seemingly boolean +values are actually tristates in this binding: unspecified, off or on. +Unspecified is represented as an absent property, and off/on are represented +as integer values 0 and 1. + +Required properties: +- nvidia,lanes: An array of strings. Each string is the name of a lane. + +Optional properties: +- nvidia,function: A string that is the name of the function (pad) that the + pin or group should be assigned to. Valid values for function names are + listed below. +- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) + +Note that not all of these properties are valid for all lanes. Lanes can be +divided into three groups: + + - otg-0, otg-1, otg-2: + + Valid functions for this group are: "snps", "xusb", "uart", "rsvd". + + The nvidia,iddq property does not apply to this group. + + - ulpi-0, hsic-0, hsic-1: + + Valid functions for this group are: "snps", "xusb". + + The nvidia,iddq property does not apply to this group. + + - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: + + Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". + + +Example: +======== + +SoC file extract: +----------------- + + padctl@7009f000 { + compatible = "nvidia,tegra124-xusb-padctl"; + reg = <0x0 0x7009f000 0x0 0x1000>; + resets = <&tegra_car 142>; + reset-names = "padctl"; + + #phy-cells = <1>; + }; + +Board file extract: +------------------- + + pcie-controller@1003000 { + ... + + phys = <&padctl 0>; + phy-names = "pcie"; + + ... + }; + + ... + + padctl: padctl@7009f000 { + pinctrl-0 = <&padctl_default>; + pinctrl-names = "default"; + + padctl_default: pinmux { + usb3 { + nvidia,lanes = "pcie-0", "pcie-1"; + nvidia,function = "usb3"; + nvidia,iddq = <0>; + }; + + pcie { + nvidia,lanes = "pcie-2", "pcie-3", + "pcie-4"; + nvidia,function = "pcie"; + nvidia,iddq = <0>; + }; + + sata { + nvidia,lanes = "sata-0"; + nvidia,function = "sata"; + nvidia,iddq = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml new file mode 100644 index 000000000..ac764d0ac --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml @@ -0,0 +1,285 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra186-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra186-pinmux + - nvidia,tegra186-pinmux-aon + + reg: + items: + - description: pinmux registers + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + unevaluatedProperties: false + properties: + nvidia,function: + enum: [ aud, can0, can1, ccla, dca, dcb, dcc, directdc, directdc1, + displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp, + dspk0, dspk1, dtv, eqos, extperiph1, extperiph2, extperiph3, + extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c7, + i2c8, i2c9, i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, iqc0, iqc1, + nv, pe, pe0, pe1, pe2, qspi, rsvd0, rsvd1, rsvd2, rsvd3, + sata, sce, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, + spi2, spi3, spi4, touch, uarta, uartb, uartc, uartd, uarte, + uartf, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, + wdt ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + + required: + - nvidia,pins + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-pinmux + then: + patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + additionalProperties: + properties: + nvidia,pins: + description: An array of strings. Each string contains the name + of a pin or group. Valid values for these names are listed + below. + items: + enum: [ pex_l0_rst_n_pa0, pex_l0_clkreq_n_pa1, + pex_wake_n_pa2, pex_l1_rst_n_pa3, + pex_l1_clkreq_n_pa4, pex_l2_rst_n_pa5, + pex_l2_clkreq_n_pa6, uart4_tx_pb0, uart4_rx_pb1, + uart4_rts_pb2, uart4_cts_pb3, gpio_wan1_pb4, + gpio_wan2_pb5, gpio_wan3_pb6, gpio_wan4_pc0, + dap2_sclk_pc1, dap2_dout_pc2, dap2_din_pc3, + dap2_fs_pc4, gen1_i2c_scl_pc5, gen1_i2c_sda_pc6, + sdmmc1_clk_pd0, sdmmc1_cmd_pd1, sdmmc1_dat0_pd2, + sdmmc1_dat1_pd3, sdmmc1_dat2_pd4, sdmmc1_dat3_pd5, + eqos_txc_pe0, eqos_td0_pe1, eqos_td1_pe2, + eqos_td2_pe3, eqos_td3_pe4, eqos_tx_ctl_pe5, + eqos_rd0_pe6, eqos_rd1_pe7, eqos_rd2_pf0, + eqos_rd3_pf1, eqos_rx_ctl_pf2, eqos_rxc_pf3, + eqos_mdio_pf4, eqos_mdc_pf5, sdmmc3_clk_pg0, + sdmmc3_cmd_pg1, sdmmc3_dat0_pg2, sdmmc3_dat1_pg3, + sdmmc3_dat2_pg4, sdmmc3_dat3_pg5, gpio_wan5_ph0, + gpio_wan6_ph1, gpio_wan7_ph2, gpio_wan8_ph3, + bcpu_pwr_req_ph4, mcpu_pwr_req_ph5, gpu_pwr_req_ph6, + gpio_pq0_pi0, gpio_pq1_pi1, gpio_pq2_pi2, + gpio_pq3_pi3, gpio_pq4_pi4, gpio_pq5_pi5, + gpio_pq6_pi6, gpio_pq7_pi7, dap1_sclk_pj0, + dap1_dout_pj1, dap1_din_pj2, dap1_fs_pj3, + aud_mclk_pj4, gpio_aud0_pj5, gpio_aud1_pj6, + gpio_aud2_pj7, gpio_aud3_pk0, gen7_i2c_scl_pl0, + gen7_i2c_sda_pl1, gen9_i2c_scl_pl2, gen9_i2c_sda_pl3, + usb_vbus_en0_pl4, usb_vbus_en1_pl5, gp_pwm6_pl6, + gp_pwm7_pl7, dmic1_dat_pm0, dmic1_clk_pm1, + dmic2_dat_pm2, dmic2_clk_pm3, dmic4_dat_pm4, + dmic4_clk_pm5, gpio_cam1_pn0, gpio_cam2_pn1, + gpio_cam3_pn2, gpio_cam4_pn3, gpio_cam6_pn5, + gpio_cam7_pn6, extperiph1_clk_po0, + extperiph2_clk_po1, cam_i2c_scl_po2, cam_i2c_sda_po3, + dp_aux_ch0_hpd_pp0, dp_aux_ch1_hpd_pp1, hdmi_cec_pp2, + gpio_edp0_pp3, gpio_edp1_pp4, gpio_edp2_pp5, + gpio_edp3_pp6, directdc1_clk_pq0, directdc1_in_pq1, + directdc1_out0_pq2, directdc1_out1_pq3, + directdc1_out2_pq4, directdc1_out3_pq5, + qspi_sck_pr0, qspi_io0_pr1, qspi_io1_pr2, + qspi_io2_pr3, qspi_io3_pr4, qspi_cs_n_pr5, + uart1_tx_pt0, uart1_rx_pt1, uart1_rts_pt2, + uart1_cts_pt3, uart2_tx_px0, uart2_rx_px1, + uart2_rts_px2, uart2_cts_px3, uart5_tx_px4, + uart5_rx_px5, uart5_rts_px6, uart5_cts_px7, + gpio_mdm1_py0, gpio_mdm2_py1, gpio_mdm3_py2, + gpio_mdm4_py3, gpio_mdm5_py4, gpio_mdm6_py5, + gpio_mdm7_py6, ufs0_ref_clk_pbb0, ufs0_rst_pbb1, + dap4_sclk_pcc0, dap4_dout_pcc1, dap4_din_pcc2, + dap4_fs_pcc3, directdc_comp, sdmmc1_comp, eqos_comp, + sdmmc3_comp, qspi_comp, + # drive groups + drive_gpio_aud3_pk0, drive_gpio_aud2_pj7, + drive_gpio_aud1_pj6, drive_gpio_aud0_pj5, + drive_aud_mclk_pj4, drive_dap1_fs_pj3, + drive_dap1_din_pj2, drive_dap1_dout_pj1, + drive_dap1_sclk_pj0, drive_dmic1_clk_pm1, + drive_dmic1_dat_pm0, drive_dmic2_dat_pm2, + drive_dmic2_clk_pm3, drive_dmic4_dat_pm4, + drive_dmic4_clk_pm5, drive_dap4_fs_pcc3, + drive_dap4_din_pcc2, drive_dap4_dout_pcc1, + drive_dap4_sclk_pcc0, drive_extperiph2_clk_po1, + drive_extperiph1_clk_po0, drive_cam_i2c_sda_po3, + drive_cam_i2c_scl_po2, drive_gpio_cam1_pn0, + drive_gpio_cam2_pn1, drive_gpio_cam3_pn2, + drive_gpio_cam4_pn3, drive_gpio_cam5_pn4, + drive_gpio_cam6_pn5, drive_gpio_cam7_pn6, + drive_dap2_din_pc3, drive_dap2_dout_pc2, + drive_dap2_fs_pc4, drive_dap2_sclk_pc1, + drive_uart4_cts_pb3, drive_uart4_rts_pb2, + drive_uart4_rx_pb1, drive_uart4_tx_pb0, + drive_gpio_wan4_pc0, drive_gpio_wan3_pb6, + drive_gpio_wan2_pb5, drive_gpio_wan1_pb4, + drive_gen1_i2c_scl_pc5, drive_gen1_i2c_sda_pc6, + drive_uart1_cts_pt3, drive_uart1_rts_pt2, + drive_uart1_rx_pt1, drive_uart1_tx_pt0, + drive_directdc1_out3_pq5, drive_directdc1_out2_pq4, + drive_directdc1_out1_pq3, drive_directdc1_out0_pq2, + drive_directdc1_in_pq1, drive_directdc1_clk_pq0, + drive_gpio_pq0_pi0, drive_gpio_pq1_pi1, + drive_gpio_pq2_pi2, drive_gpio_pq3_pi3, + drive_gpio_pq4_pi4, drive_gpio_pq5_pi5, + drive_gpio_pq6_pi6, drive_gpio_pq7_pi7, + drive_gpio_edp2_pp5, drive_gpio_edp3_pp6, + drive_gpio_edp0_pp3, drive_gpio_edp1_pp4, + drive_dp_aux_ch0_hpd_pp0, drive_dp_aux_ch1_hpd_pp1, + drive_hdmi_cec_pp2, drive_pex_l2_clkreq_n_pa6, + drive_pex_wake_n_pa2, drive_pex_l1_clkreq_n_pa4, + drive_pex_l1_rst_n_pa3, drive_pex_l0_clkreq_n_pa1, + drive_pex_l0_rst_n_pa0, drive_pex_l2_rst_n_pa5, + drive_sdmmc1_clk_pd0, drive_sdmmc1_cmd_pd1, + drive_sdmmc1_dat3_pd5, drive_sdmmc1_dat2_pd4, + drive_sdmmc1_dat1_pd3, drive_sdmmc1_dat0_pd2, + drive_eqos_td3_pe4, drive_eqos_td2_pe3, + drive_eqos_td1_pe2, drive_eqos_td0_pe1, + drive_eqos_rd3_pf1, drive_eqos_rd2_pf0, + drive_eqos_rd1_pe7, drive_eqos_mdio_pf4, + drive_eqos_rd0_pe6, drive_eqos_mdc_pf5, + drive_eqos_txc_pe0, drive_eqos_rxc_pf3, + drive_eqos_tx_ctl_pe5, drive_eqos_rx_ctl_pf2, + drive_sdmmc3_dat3_pg5, drive_sdmmc3_dat2_pg4, + drive_sdmmc3_dat1_pg3, drive_sdmmc3_dat0_pg2, + drive_sdmmc3_cmd_pg1, drive_sdmmc3_clk_pg0, + drive_qspi_io3_pr4, drive_qspi_io2_pr3, + drive_qspi_io1_pr2, drive_qspi_io0_pr1, + drive_qspi_sck_pr0, drive_qspi_cs_n_pr5, + drive_gpio_wan8_ph3, drive_gpio_wan7_ph2, + drive_gpio_wan6_ph1, drive_gpio_wan5_ph0, + drive_uart2_tx_px0, drive_uart2_rx_px1, + drive_uart2_rts_px2, drive_uart2_cts_px3, + drive_uart5_rx_px5, drive_uart5_tx_px4, + drive_uart5_rts_px6, drive_uart5_cts_px7, + drive_gpio_mdm1_py0, drive_gpio_mdm2_py1, + drive_gpio_mdm3_py2, drive_gpio_mdm4_py3, + drive_gpio_mdm5_py4, drive_gpio_mdm6_py5, + drive_gpio_mdm7_py6, drive_bcpu_pwr_req_ph4, + drive_mcpu_pwr_req_ph5, drive_gpu_pwr_req_ph6, + drive_gen7_i2c_scl_pl0, drive_gen7_i2c_sda_pl1, + drive_gen9_i2c_sda_pl3, drive_gen9_i2c_scl_pl2, + drive_usb_vbus_en0_pl4, drive_usb_vbus_en1_pl5, + drive_gp_pwm7_pl7, drive_gp_pwm6_pl6, + drive_ufs0_rst_pbb1, drive_ufs0_ref_clk_pbb0, + drive_directdc_comp, drive_sdmmc1_comp, + drive_eqos_comp, drive_sdmmc3_comp, drive_sdmmc4_clk, + drive_sdmmc4_cmd, drive_sdmmc4_dqs, + drive_sdmmc4_dat7, drive_sdmmc4_dat6, + drive_sdmmc4_dat5, drive_sdmmc4_dat4, + drive_sdmmc4_dat3, drive_sdmmc4_dat2, + drive_sdmmc4_dat1, drive_sdmmc4_dat0, + drive_qspi_comp ] + + - if: + properties: + compatible: + const: nvidia,tegra186-pinmux-aon + then: + patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + additionalProperties: + properties: + nvidia,pins: + items: + enum: [ pwr_i2c_scl_ps0, pwr_i2c_sda_ps1, batt_oc_ps2, + safe_state_ps3, vcomp_alert_ps4, gpio_dis0_pu0, + gpio_dis1_pu1, gpio_dis2_pu2, gpio_dis3_pu3, + gpio_dis4_pu4, gpio_dis5_pu5, gpio_sen0_pv0, + gpio_sen1_pv1, gpio_sen2_pv2, gpio_sen3_pv3, + gpio_sen4_pv4, gpio_sen5_pv5, gpio_sen6_pv6, + gpio_sen7_pv7, gen8_i2c_scl_pw0, gen8_i2c_sda_pw1, + uart3_tx_pw2, uart3_rx_pw3, uart3_rts_pw4, + uart3_cts_pw5, uart7_tx_pw6, uart7_rx_pw7, + can1_dout_pz0, can1_din_pz1, can0_dout_pz2, + can0_din_pz3, can_gpio0_paa0, can_gpio1_paa1, + can_gpio2_paa2, can_gpio3_paa3, can_gpio4_paa4, + can_gpio5_paa5, can_gpio6_paa6, can_gpio7_paa7, + gpio_sen8_pee0, gpio_sen9_pee1, touch_clk_pee2, + power_on_pff0, gpio_sw1_pff1, gpio_sw2_pff2, + gpio_sw3_pff3, gpio_sw4_pff4, shutdown, pmu_int, + soc_pwr_req, clk_32k_in, + # drive groups + drive_touch_clk_pee2, drive_uart3_cts_pw5, + drive_uart3_rts_pw4, drive_uart3_rx_pw3, + drive_uart3_tx_pw2, drive_gen8_i2c_sda_pw1, + drive_gen8_i2c_scl_pw0, drive_uart7_rx_pw7, + drive_uart7_tx_pw6, drive_gpio_sen0_pv0, + drive_gpio_sen1_pv1, drive_gpio_sen2_pv2, + drive_gpio_sen3_pv3, drive_gpio_sen4_pv4, + drive_gpio_sen5_pv5, drive_gpio_sen6_pv6, + drive_gpio_sen7_pv7, drive_gpio_sen8_pee0, + drive_gpio_sen9_pee1, drive_can_gpio7_paa7, + drive_can1_dout_pz0, drive_can1_din_pz1, + drive_can0_dout_pz2, drive_can0_din_pz3, + drive_can_gpio0_paa0, drive_can_gpio1_paa1, + drive_can_gpio2_paa2, drive_can_gpio3_paa3, + drive_can_gpio4_paa4, drive_can_gpio5_paa5, + drive_can_gpio6_paa6, drive_gpio_sw1_pff1, + drive_gpio_sw2_pff2, drive_gpio_sw3_pff3, + drive_gpio_sw4_pff4, drive_shutdown, drive_pmu_int, + drive_safe_state_ps3, drive_vcomp_alert_ps4, + drive_soc_pwr_req, drive_batt_oc_ps2, + drive_clk_32k_in, drive_power_on_pff0, + drive_pwr_i2c_scl_ps0, drive_pwr_i2c_sda_ps1, + drive_gpio_dis0_pu0, drive_gpio_dis1_pu1, + drive_gpio_dis2_pu2, drive_gpio_dis3_pu3, + drive_gpio_dis4_pu4, drive_gpio_dis5_pu5 ] + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@2430000 { + compatible = "nvidia,tegra186-pinmux"; + reg = <0x2430000 0x15000>; + + pinctrl-names = "jetson_io"; + pinctrl-0 = <&jetson_io_pinmux>; + + jetson_io_pinmux: pinmux { + hdr40-pin7 { + nvidia,pins = "aud_mclk_pj4"; + nvidia,function = "aud"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml new file mode 100644 index 000000000..87b6f4f42 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra194-pinmux.yaml @@ -0,0 +1,282 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra194-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra194 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra194-pinmux + - nvidia,tegra194-pinmux-aon + + reg: + items: + - description: pinmux registers + +patternProperties: + "^pinmux(-[a-z0-9-_]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + unevaluatedProperties: false + properties: + nvidia,function: + enum: [ aud, can0, can1, ccla, dca, dcb, dgpu, directdc, directdc1, + displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp, + dspk0, dspk1, eqos, extperiph1, extperiph2, extperiph3, + extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c8, + i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, igpu, iqc1, iqc2, mipi, + nv, pe0, pe1, pe2, pe3, pe4, pe5, qspi, qspi0, qspi1, rsvd0, + rsvd1, rsvd2, rsvd3, sata, sce, sdmmc1, sdmmc3, sdmmc4, slvs, + soc, spdif, spi1, spi2, spi3, touch, uarta, uartb, uartc, + uartd, uarte, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5, + vgp6, wdt ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + + required: + - nvidia,pins + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + const: nvidia,tegra194-pinmux + then: + patternProperties: + "^pinmux(-[a-z0-9-_]+)?$": + type: object + additionalProperties: + properties: + nvidia,pins: + description: An array of strings. Each string contains the name + of a pin or group. Valid values for these names are listed + below. + + Note that the pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 pins + are part of PCIE C5 power partition. Client devices must + enable this partition before accessing the configuration for + these pins. + items: + enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2, + dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5, + dap4_din_pa6, dap4_fs_pa7, cpu_pwr_req_0_pb0, + cpu_pwr_req_1_pb1, qspi0_sck_pc0, qspi0_cs_n_pc1, + qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4, + qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7, + qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2, + qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1, + eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4, + eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7, + eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2, + eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5, + soc_gpio00_pg0, soc_gpio01_pg1, soc_gpio02_pg2, + soc_gpio03_pg3, soc_gpio08_pg4, soc_gpio09_pg5, + soc_gpio10_pg6, soc_gpio11_pg7, soc_gpio12_ph0, + soc_gpio13_ph1, soc_gpio14_ph2, uart4_tx_ph3, + uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6, + dap2_sclk_ph7, dap2_dout_pi0, dap2_din_pi1, + dap2_fs_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4, + sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2, + sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5, + pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1, + pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3, + pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5, + pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7, + pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1, + pex_wake_n_pl2, sata_dev_slp_pl3, dp_aux_ch0_hpd_pm0, + dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2, + dp_aux_ch3_hpd_pm3, hdmi_cec_pm4, soc_gpio50_pm5, + soc_gpio51_pm6, soc_gpio52_pm7, soc_gpio53_pn0, + soc_gpio54_pn1, soc_gpio55_pn2, sdmmc3_clk_po0, + sdmmc3_cmd_po1, sdmmc3_dat0_po2, sdmmc3_dat1_po3, + sdmmc3_dat2_po4, sdmmc3_dat3_po5, extperiph1_clk_pp0, + extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3, + soc_gpio04_pp4, soc_gpio05_pp5, soc_gpio06_pp6, + soc_gpio07_pp7, soc_gpio20_pq0, soc_gpio21_pq1, + soc_gpio22_pq2, soc_gpio23_pq3, soc_gpio40_pq4, + soc_gpio41_pq5, soc_gpio42_pq6, soc_gpio43_pq7, + soc_gpio44_pr0, soc_gpio45_pr1, uart1_tx_pr2, + uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5, + dap1_sclk_ps0, dap1_dout_ps1, dap1_din_ps2, + dap1_fs_ps3, aud_mclk_ps4, soc_gpio30_ps5, + soc_gpio31_ps6, soc_gpio32_ps7, soc_gpio33_pt0, + dap3_sclk_pt1, dap3_dout_pt2, dap3_din_pt3, + dap3_fs_pt4, dap5_sclk_pt5, dap5_dout_pt6, + dap5_din_pt7, dap5_fs_pu0, directdc1_clk_pv0, + directdc1_in_pv1, directdc1_out0_pv2, + directdc1_out1_pv3, directdc1_out2_pv4, + directdc1_out3_pv5, directdc1_out4_pv6, + directdc1_out5_pv7, directdc1_out6_pw0, + directdc1_out7_pw1, gpu_pwr_req_px0, cv_pwr_req_px1, + gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, uart2_rx_px5, + uart2_rts_px6, uart2_cts_px7, spi3_sck_py0, + spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3, + spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6, + uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1, + usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4, + spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7, + ufs0_ref_clk_pff0, ufs0_rst_pff1, + pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1, + directdc_comp, sdmmc4_clk, sdmmc4_cmd, sdmmc4_dqs, + sdmmc4_dat7, sdmmc4_dat6, sdmmc4_dat5, sdmmc4_dat4, + sdmmc4_dat3, sdmmc4_dat2, sdmmc4_dat1, sdmmc4_dat0, + sdmmc1_comp, sdmmc1_hv_trim, sdmmc3_comp, + sdmmc3_hv_trim, eqos_comp, qspi_comp, + # drive groups + drive_soc_gpio33_pt0, drive_soc_gpio32_ps7, + drive_soc_gpio31_ps6, drive_soc_gpio30_ps5, + drive_aud_mclk_ps4, drive_dap1_fs_ps3, + drive_dap1_din_ps2, drive_dap1_dout_ps1, + drive_dap1_sclk_ps0, drive_dap3_fs_pt4, + drive_dap3_din_pt3, drive_dap3_dout_pt2, + drive_dap3_sclk_pt1, drive_dap5_fs_pu0, + drive_dap5_din_pt7, drive_dap5_dout_pt6, + drive_dap5_sclk_pt5, drive_dap6_fs_pa3, + drive_dap6_din_pa2, drive_dap6_dout_pa1, + drive_dap6_sclk_pa0, drive_dap4_fs_pa7, + drive_dap4_din_pa6, drive_dap4_dout_pa5, + drive_dap4_sclk_pa4, drive_extperiph2_clk_pp1, + drive_extperiph1_clk_pp0, drive_cam_i2c_sda_pp3, + drive_cam_i2c_scl_pp2, drive_soc_gpio40_pq4, + drive_soc_gpio41_pq5, drive_soc_gpio42_pq6, + drive_soc_gpio43_pq7, drive_soc_gpio44_pr0, + drive_soc_gpio45_pr1, drive_soc_gpio20_pq0, + drive_soc_gpio21_pq1, drive_soc_gpio22_pq2, + drive_soc_gpio23_pq3, drive_soc_gpio04_pp4, + drive_soc_gpio05_pp5, drive_soc_gpio06_pp6, + drive_soc_gpio07_pp7, drive_uart1_cts_pr5, + drive_uart1_rts_pr4, drive_uart1_rx_pr3, + drive_uart1_tx_pr2, drive_dap2_din_pi1, + drive_dap2_dout_pi0, drive_dap2_fs_pi2, + drive_dap2_sclk_ph7, drive_uart4_cts_ph6, + drive_uart4_rts_ph5, drive_uart4_rx_ph4, + drive_uart4_tx_ph3, drive_soc_gpio03_pg3, + drive_soc_gpio02_pg2, drive_soc_gpio01_pg1, + drive_soc_gpio00_pg0, drive_gen1_i2c_scl_pi3, + drive_gen1_i2c_sda_pi4, drive_soc_gpio08_pg4, + drive_soc_gpio09_pg5, drive_soc_gpio10_pg6, + drive_soc_gpio11_pg7, drive_soc_gpio12_ph0, + drive_soc_gpio13_ph1, drive_soc_gpio14_ph2, + drive_soc_gpio50_pm5, drive_soc_gpio51_pm6, + drive_soc_gpio52_pm7, drive_soc_gpio53_pn0, + drive_soc_gpio54_pn1, drive_soc_gpio55_pn2, + drive_dp_aux_ch0_hpd_pm0, drive_dp_aux_ch1_hpd_pm1, + drive_dp_aux_ch2_hpd_pm2, drive_dp_aux_ch3_hpd_pm3, + drive_hdmi_cec_pm4, drive_pex_l2_clkreq_n_pk4, + drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2, + drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0, + drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5, + drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7, + drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1, + drive_sata_dev_slp_pl3, drive_pex_l5_clkreq_n_pgg0, + drive_pex_l5_rst_n_pgg1, drive_cpu_pwr_req_1_pb1, + drive_cpu_pwr_req_0_pb0, drive_sdmmc1_clk_pj0, + drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5, + drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3, + drive_sdmmc1_dat0_pj2, drive_sdmmc3_dat3_po5, + drive_sdmmc3_dat2_po4, drive_sdmmc3_dat1_po3, + drive_sdmmc3_dat0_po2, drive_sdmmc3_cmd_po1, + drive_sdmmc3_clk_po0, drive_gpu_pwr_req_px0, + drive_spi3_miso_py1, drive_spi1_cs0_pz6, + drive_spi3_cs0_py3, drive_spi1_miso_pz4, + drive_spi3_cs1_py4, drive_gp_pwm3_px3, + drive_gp_pwm2_px2, drive_spi1_sck_pz3, + drive_spi3_sck_py0, drive_spi1_cs1_pz7, + drive_spi1_mosi_pz5, drive_spi3_mosi_py2, + drive_cv_pwr_req_px1, drive_uart2_tx_px4, + drive_uart2_rx_px5, drive_uart2_rts_px6, + drive_uart2_cts_px7, drive_uart5_rx_py6, + drive_uart5_tx_py5, drive_uart5_rts_py7, + drive_uart5_cts_pz0, drive_usb_vbus_en0_pz1, + drive_usb_vbus_en1_pz2, drive_ufs0_rst_pff1, + drive_ufs0_ref_clk_pff0 ] + + - if: + properties: + compatible: + const: nvidia,tegra194-pinmux-aon + then: + patternProperties: + "^pinmux(-[a-z0-9-_]+)?$": + type: object + additionalProperties: + properties: + nvidia,pins: + items: + enum: [ can1_dout_paa0, can1_din_paa1, can0_dout_paa2, + can0_din_paa3, can0_stb_paa4, can0_en_paa5, + can0_wake_paa6, can0_err_paa7, can1_stb_pbb0, + can1_en_pbb1, can1_wake_pbb2, can1_err_pbb3, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, + gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, + safe_state_pee0, vcomp_alert_pee1, + ao_retention_n_pee2, batt_oc_pee3, power_on_pee4, + pwr_i2c_scl_pee5, pwr_i2c_sda_pee6, sys_reset_n, + shutdown_n, pmu_int_n, soc_pwr_req, clk_32k_in, + # drive groups + drive_shutdown_n, drive_pmu_int_n, + drive_safe_state_pee0, drive_vcomp_alert_pee1, + drive_soc_pwr_req, drive_batt_oc_pee3, + drive_clk_32k_in, drive_power_on_pee4, + drive_pwr_i2c_scl_pee5, drive_pwr_i2c_sda_pee6, + drive_ao_retention_n_pee2, drive_touch_clk_pcc4, + drive_uart3_rx_pcc6, drive_uart3_tx_pcc5, + drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1, + drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7, + drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0, + drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, + drive_can1_dout_paa0, drive_can1_din_paa1, + drive_can0_dout_paa2, drive_can0_din_paa3, + drive_can0_stb_paa4, drive_can0_en_paa5, + drive_can0_wake_paa6, drive_can0_err_paa7, + drive_can1_stb_pbb0, drive_can1_en_pbb1, + drive_can1_wake_pbb2, drive_can1_err_pbb3 ] + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@2430000 { + compatible = "nvidia,tegra194-pinmux"; + reg = <0x2430000 0x17000>; + + pinctrl-names = "pex_rst"; + pinctrl-0 = <&pex_rst_c5_out_state>; + + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { + pex_rst { + nvidia,pins = "pex_l5_rst_n_pgg1"; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml new file mode 100644 index 000000000..63cd743a3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra20-pinmux.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra20-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra20-pinmux + + reg: + items: + - description: tri-state registers + - description: mux register + - description: pull-up/down registers + - description: pad control registers + +patternProperties: + "^pinmux(-[a-z0-9-_]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + additionalProperties: false + properties: + nvidia,pins: + items: + enum: [ ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, + dap2, dap3, dap4, ddc, dta, dtb, dtc, dtd, dte, dtf, gma, + gmb, gmc, gmd, gme, gpu, gpu7, gpv, hdint, i2cp, irrx, + irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn, ld0, ld1, + ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, + ld13, ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, + lhs, lm0, lm1, lpp, lpw0, lpw1, lpw2, lsc0, lsc1, lsck, + lsda, lsdi, lspi, lvp0, lvp1, lvs, owc, pmc, pta, rm, sdb, + sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi, spdo, spia, + spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, + uad, uca, ucb, uda, + # tristate groups + ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, + lc, ld17_0, ld19_18, ld21_20, ld23_22, + # drive groups + drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, + drive_cdev2, drive_csus, drive_dap1, drive_dap2, + drive_dap3, drive_dap4, drive_dbg, drive_lcd1, drive_lcd2, + drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa, + drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, + drive_xm2a, drive_xm2c, drive_xm2d, drive_xm2clk, + drive_sdio1, drive_crt, drive_ddc, drive_gma, drive_gmb, + drive_gmc, drive_gmd, drive_gme, drive_owr, drive_uda ] + + nvidia,function: + enum: [ ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, + dap5, displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, + gmi_int, hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, + mipi_hs, nand, osc, owr, pcie, plla_out, pllc_out1, + pllm_out1, pllp_out2, pllp_out3, pllp_out4, pwm, pwr_intr, + pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck, sdio1, sdio2, + sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt, spi3, + spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi, + vi, vi_sensor_clk, xio ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,pull-down-strength: true + nvidia,pull-up-strength: true + nvidia,high-speed-mode: true + nvidia,low-power-mode: true + nvidia,slew-rate-rising: true + nvidia,slew-rate-falling: true + + required: + - nvidia,pins + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@70000000 { + compatible = "nvidia,tegra20-pinmux"; + reg = <0x70000014 0x10>, /* Tri-state registers */ + <0x70000080 0x20>, /* Mux registers */ + <0x700000a0 0x14>, /* Pull-up/down registers */ + <0x70000868 0xa8>; /* Pad control registers */ + + pinmux { + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml new file mode 100644 index 000000000..e99387a6d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra210-pinmux.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra210-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra210 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra210-pinmux + + reg: + items: + - description: APB_MISC_GP_*_PADCTRL register (pad control) + - description: PINMUX_AUX_* registers (pinmux) + +patternProperties: + "^pinmux(-[a-z0-9-_]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + additionalProperties: false + properties: + nvidia,pins: + items: + enum: [ als_prox_int_px3, ap_ready_pv5, ap_wake_bt_ph3, + ap_wake_nfc_ph7, aud_mclk_pbb0, batt_bcl, bt_rst_ph4, + bt_wake_ap_ph5, button_home_py1, button_power_on_px5, + button_slide_sw_py0, button_vol_down_px7, + button_vol_up_px6, cam1_mclk_ps0, cam1_pwdn_ps7, + cam1_strobe_pt1, cam2_mclk_ps1, cam2_pwdn_pt0, + cam_af_en_ps5, cam_flash_en_ps6, cam_i2c_scl_ps2, + cam_i2c_sda_ps3, cam_rst_ps4, clk_32k_in, clk_32k_out_py5, + clk_req, core_pwr_req, cpu_pwr_req, dap1_din_pb1, + dap1_dout_pb2, dap1_fs_pb0, dap1_sclk_pb3, dap2_din_paa2, + dap2_dout_paa3, dap2_fs_paa0, dap2_sclk_paa1, dap4_din_pj5, + dap4_dout_pj6, dap4_fs_pj4, dap4_sclk_pj7, dmic1_clk_pe0, + dmic1_dat_pe1, dmic2_clk_pe2, dmic2_dat_pe3, dmic3_clk_pe4, + dmic3_dat_pe5, dp_hpd0_pcc6, dvfs_clk_pbb2, dvfs_pwm_pbb1, + gen1_i2c_scl_pj1, gen1_i2c_sda_pj0, gen2_i2c_scl_pj2, + gen2_i2c_sda_pj3, gen3_i2c_scl_pf0, gen3_i2c_sda_pf1, + gpio_x1_aud_pbb3, gpio_x3_aud_pbb4, gps_en_pi2, + gps_rst_pi3, hdmi_cec_pcc0, hdmi_int_dp_hpd_pcc1, + jtag_rtck, lcd_bl_en_pv1, lcd_bl_pwm_pv0, lcd_gpio1_pv3, + lcd_gpio2_pv4, lcd_rst_pv2, lcd_te_py2, modem_wake_ap_px0, + motion_int_px2, nfc_en_pi0, nfc_int_pi1, pa6, pcc7, pe6, + pe7, pex_l0_clkreq_n_pa1, pex_l0_rst_n_pa0, + pex_l1_clkreq_n_pa4, pex_l1_rst_n_pa3, pex_wake_n_pa2, ph6, + pk0, pk1, pk2, pk3, pk4, pk5, pk6, pk7, pl0, pl1, + pwr_i2c_scl_py3, pwr_i2c_sda_py4, pwr_int_n, pz0, pz1, pz2, + pz3, pz4, pz5, qspi_cs_n_pee1, qspi_io0_pee2, + qspi_io1_pee3, qspi_io2_pee4, qspi_io3_pee5, qspi_sck_pee0, + sata_led_active_pa5, sdmmc1_clk_pm0, sdmmc1_cmd_pm1, + sdmmc1_dat0_pm5, sdmmc1_dat1_pm4, sdmmc1_dat2_pm3, + sdmmc1_dat3_pm2, sdmmc3_clk_pp0, sdmmc3_cmd_pp1, + sdmmc3_dat0_pp5, sdmmc3_dat1_pp4, sdmmc3_dat2_pp3, + sdmmc3_dat3_pp2, shutdown, spdif_in_pcc3, spdif_out_pcc2, + spi1_cs0_pc3, spi1_cs1_pc4, spi1_miso_pc1, spi1_mosi_pc0, + spi1_sck_pc2, spi2_cs0_pb7, spi2_cs1_pdd0, spi2_miso_pb5, + spi2_mosi_pb4, spi2_sck_pb6, spi4_cs0_pc6, spi4_miso_pd0, + spi4_mosi_pc7, spi4_sck_pc5, temp_alert_px4, touch_clk_pv7, + touch_int_px1, touch_rst_pv6, uart1_cts_pu3, uart1_rts_pu2, + uart1_rx_pu1, uart1_tx_pu0, uart2_cts_pg3, uart2_rts_pg2, + uart2_rx_pg1, uart2_tx_pg0, uart3_cts_pd4, uart3_rts_pd3, + uart3_rx_pd2, uart3_tx_pd1, uart4_cts_pi7, uart4_rts_pi6, + uart4_rx_pi5, uart4_tx_pi4, usb_vbus_en0_pcc4, + usb_vbus_en1_pcc5, wifi_en_ph0, wifi_rst_ph1, + wifi_wake_ap_ph2, + # drive groups + drive_pa6, drive_pcc7, drive_pe6, drive_pe7, drive_ph6, + drive_pk0, drive_pk1, drive_pk2, drive_pk3, drive_pk4, + drive_pk5, drive_pk6, drive_pk7, drive_pl0, drive_pl1, + drive_pz0, drive_pz1, drive_pz2, drive_pz3, drive_pz4, + drive_pz5, drive_sdmmc1, drive_sdmmc2, drive_sdmmc3, + drive_sdmmc4 ] + + nvidia,function: + enum: [ aud, bcl, blink, ccla, cec, cldvfs, clk, core, cpu, displaya, + displayb, dmic1, dmic2, dmic3, dp, dtv, extperiph3, i2c1, + i2c2, i2c3, i2cpmu, i2cvi, i2s1, i2s2, i2s3, i2s4a, i2s4b, + i2s5a, i2s5b, iqc0, iqc1, jtag, pe, pe0, pe1, pmi, pwm0, + pwm1, pwm2, pwm3, qspi, rsvd0, rsvd1, rsvd2, rsvd3, sata, + sdmmc1, sdmmc3, shutdown, soc, sor0, sor1, spdif, spi1, spi2, + spi3, spi4, sys, touch, uart, uarta, uartb, uartc, uartd, + usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, vimclk, vimclk2 ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,pull-down-strength: true + nvidia,pull-up-strength: true + nvidia,high-speed-mode: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + nvidia,slew-rate-rising: true + nvidia,slew-rate-falling: true + + required: + - nvidia,pins + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux: pinmux@70000800 { + compatible = "nvidia,tegra210-pinmux"; + reg = <0x700008d4 0x02a8>, /* Pad control registers */ + <0x70003000 0x1000>; /* Mux registers */ + + pinctrl-names = "boot"; + pinctrl-0 = <&state_boot>; + + state_boot: pinmux { + gen1_i2c_scl_pj1 { + nvidia,pins = "gen1_i2c_scl_pj1"; + nvidia,function = "i2c1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml new file mode 100644 index 000000000..db8224dfb --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra234 AON Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra234-pinmux-aon + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra234-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ can0_dout_paa0, can0_din_paa1, can1_dout_paa2, + can1_din_paa3, can0_stb_paa4, can0_en_paa5, + soc_gpio49_paa6, can0_err_paa7, can1_stb_pbb0, + can1_en_pbb1, soc_gpio50_pbb2, can1_err_pbb3, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, touch_clk_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, + gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, + sce_error_pee0, vcomp_alert_pee1, + ao_retention_n_pee2, batt_oc_pee3, power_on_pee4, + soc_gpio26_pee5, soc_gpio27_pee6, bootv_ctl_n_pee7, + hdmi_cec_pgg0, + # drive groups + drive_touch_clk_pcc4, drive_uart3_rx_pcc6, + drive_uart3_tx_pcc5, drive_gen8_i2c_sda_pdd2, + drive_gen8_i2c_scl_pdd1, drive_spi2_mosi_pcc2, + drive_gen2_i2c_scl_pcc7, drive_spi2_cs0_pcc3, + drive_gen2_i2c_sda_pdd0, drive_spi2_sck_pcc0, + drive_spi2_miso_pcc1, drive_can1_dout_paa2, + drive_can1_din_paa3, drive_can0_dout_paa0, + drive_can0_din_paa1, drive_can0_stb_paa4, + drive_can0_en_paa5, drive_soc_gpio49_paa6, + drive_can0_err_paa7, drive_can1_stb_pbb0, + drive_can1_en_pbb1, drive_soc_gpio50_pbb2, + drive_can1_err_pbb3, drive_sce_error_pee0, + drive_batt_oc_pee3, drive_bootv_ctl_n_pee7, + drive_power_on_pee4, drive_soc_gpio26_pee5, + drive_soc_gpio27_pee6, drive_ao_retention_n_pee2, + drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ] + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@c300000 { + compatible = "nvidia,tegra234-pinmux-aon"; + reg = <0xc300000 0x4000>; + + pinctrl-names = "cec"; + pinctrl-0 = <&cec_state>; + + cec_state: pinmux-cec { + cec { + nvidia,pins = "hdmi_cec_pgg0"; + nvidia,function = "gp"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml new file mode 100644 index 000000000..8cf9e4c91 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-common.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra234 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +$ref: nvidia,tegra-pinmux-common.yaml + +properties: + nvidia,function: + enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2, + eth1, dp, eth3, i2c4, i2c7, i2c9, eqos, pe2, pe1, pe0, pe3, + pe4, pe5, pe6, pe7, pe8, pe9, pe10, qspi0, qspi1, qpsi, + sdmmc1, sce, soc, gpio, hdmi, ufs0, spi3, spi1, uartb, uarte, + usb, extperiph2, extperiph1, i2c3, vi0, i2c5, uarta, uartd, + i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc, + dmic3, led, vi0_alt, i2s5, nv, extperiph3, extperiph4, spi4, + ccla, i2s1, i2s2, i2s3, i2s8, rsvd2, dmic5, dca, displayb, + displaya, vi1, dcb, dmic1, dmic4, i2s7, dmic2, dspk0, rsvd3, + tsc_alt, istctrl, vi1_alt, dspk1, igpu ] + + # out of the common properties, only these are allowed for Tegra234 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + +required: + - nvidia,pins + +# We would typically use unevaluatedProperties here but that has the +# downside that all the properties in the common bindings become valid +# for all chip generations. In this case, however, we want the per-SoC +# bindings to be able to override which of the common properties are +# allowed, since not all pinmux generations support the same sets of +# properties. This way, the common bindings define the format of the +# properties but the per-SoC bindings define which of them apply to a +# given chip. +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml new file mode 100644 index 000000000..f5a3a881d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra234 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra234-pinmux + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra234-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ dap6_sclk_pa0, dap6_dout_pa1, dap6_din_pa2, + dap6_fs_pa3, dap4_sclk_pa4, dap4_dout_pa5, + dap4_din_pa6, dap4_fs_pa7, soc_gpio08_pb0, + qspi0_sck_pc0, qspi0_cs_n_pc1, + qspi0_io0_pc2, qspi0_io1_pc3, qspi0_io2_pc4, + qspi0_io3_pc5, qspi1_sck_pc6, qspi1_cs_n_pc7, + qspi1_io0_pd0, qspi1_io1_pd1, qspi1_io2_pd2, + qspi1_io3_pd3, eqos_txc_pe0, eqos_td0_pe1, + eqos_td1_pe2, eqos_td2_pe3, eqos_td3_pe4, + eqos_tx_ctl_pe5, eqos_rd0_pe6, eqos_rd1_pe7, + eqos_rd2_pf0, eqos_rd3_pf1, eqos_rx_ctl_pf2, + eqos_rxc_pf3, eqos_sma_mdio_pf4, eqos_sma_mdc_pf5, + soc_gpio13_pg0, soc_gpio14_pg1, soc_gpio15_pg2, + soc_gpio16_pg3, soc_gpio17_pg4, soc_gpio18_pg5, + soc_gpio19_pg6, soc_gpio20_pg7, soc_gpio21_ph0, + soc_gpio22_ph1, soc_gpio06_ph2, uart4_tx_ph3, + uart4_rx_ph4, uart4_rts_ph5, uart4_cts_ph6, + soc_gpio41_ph7, soc_gpio42_pi0, soc_gpio43_pi1, + soc_gpio44_pi2, gen1_i2c_scl_pi3, gen1_i2c_sda_pi4, + cpu_pwr_req_pi5, soc_gpio07_pi6, + sdmmc1_clk_pj0, sdmmc1_cmd_pj1, sdmmc1_dat0_pj2, + sdmmc1_dat1_pj3, sdmmc1_dat2_pj4, sdmmc1_dat3_pj5, + pex_l0_clkreq_n_pk0, pex_l0_rst_n_pk1, + pex_l1_clkreq_n_pk2, pex_l1_rst_n_pk3, + pex_l2_clkreq_n_pk4, pex_l2_rst_n_pk5, + pex_l3_clkreq_n_pk6, pex_l3_rst_n_pk7, + pex_l4_clkreq_n_pl0, pex_l4_rst_n_pl1, + pex_wake_n_pl2, soc_gpio34_pl3, dp_aux_ch0_hpd_pm0, + dp_aux_ch1_hpd_pm1, dp_aux_ch2_hpd_pm2, + dp_aux_ch3_hpd_pm3, soc_gpio55_pm4, soc_gpio36_pm5, + soc_gpio53_pm6, soc_gpio38_pm7, dp_aux_ch3_n_pn0, + soc_gpio39_pn1, soc_gpio40_pn2, dp_aux_ch1_p_pn3, + dp_aux_ch1_n_pn4, dp_aux_ch2_p_pn5, dp_aux_ch2_n_pn6, + dp_aux_ch3_p_pn7, extperiph1_clk_pp0, + extperiph2_clk_pp1, cam_i2c_scl_pp2, cam_i2c_sda_pp3, + soc_gpio23_pp4, soc_gpio24_pp5, soc_gpio25_pp6, + pwr_i2c_scl_pp7, pwr_i2c_sda_pq0, soc_gpio28_pq1, + soc_gpio29_pq2, soc_gpio30_pq3, soc_gpio31_pq4, + soc_gpio32_pq5, soc_gpio33_pq6, soc_gpio35_pq7, + soc_gpio37_pr0, soc_gpio56_pr1, uart1_tx_pr2, + uart1_rx_pr3, uart1_rts_pr4, uart1_cts_pr5, + soc_gpio61_pw0, soc_gpio62_pw1, gpu_pwr_req_px0, + cv_pwr_req_px1, gp_pwm2_px2, gp_pwm3_px3, uart2_tx_px4, + uart2_rx_px5, uart2_rts_px6, uart2_cts_px7, spi3_sck_py0, + spi3_miso_py1, spi3_mosi_py2, spi3_cs0_py3, + spi3_cs1_py4, uart5_tx_py5, uart5_rx_py6, + uart5_rts_py7, uart5_cts_pz0, usb_vbus_en0_pz1, + usb_vbus_en1_pz2, spi1_sck_pz3, spi1_miso_pz4, + spi1_mosi_pz5, spi1_cs0_pz6, spi1_cs1_pz7, + spi5_sck_pac0, spi5_miso_pac1, spi5_mosi_pac2, + spi5_cs0_pac3, soc_gpio57_pac4, soc_gpio58_pac5, + soc_gpio59_pac6, soc_gpio60_pac7, soc_gpio45_pad0, + soc_gpio46_pad1, soc_gpio47_pad2, soc_gpio48_pad3, + ufs0_ref_clk_pae0, ufs0_rst_n_pae1, + pex_l5_clkreq_n_paf0, pex_l5_rst_n_paf1, + pex_l6_clkreq_n_paf2, pex_l6_rst_n_paf3, + pex_l7_clkreq_n_pag0, pex_l7_rst_n_pag1, + pex_l8_clkreq_n_pag2, pex_l8_rst_n_pag3, + pex_l9_clkreq_n_pag4, pex_l9_rst_n_pag5, + pex_l10_clkreq_n_pag6, pex_l10_rst_n_pag7, + sdmmc1_comp, eqos_comp, qspi_comp, + # drive groups + drive_soc_gpio08_pb0, drive_soc_gpio36_pm5, + drive_soc_gpio53_pm6, drive_soc_gpio55_pm4, + drive_soc_gpio38_pm7, drive_soc_gpio39_pn1, + drive_soc_gpio40_pn2, drive_dp_aux_ch0_hpd_pm0, + drive_dp_aux_ch1_hpd_pm1, drive_dp_aux_ch2_hpd_pm2, + drive_dp_aux_ch3_hpd_pm3, drive_dp_aux_ch1_p_pn3, + drive_dp_aux_ch1_n_pn4, drive_dp_aux_ch2_p_pn5, + drive_dp_aux_ch2_n_pn6, drive_dp_aux_ch3_p_pn7, + drive_dp_aux_ch3_n_pn0, drive_pex_l2_clkreq_n_pk4, + drive_pex_wake_n_pl2, drive_pex_l1_clkreq_n_pk2, + drive_pex_l1_rst_n_pk3, drive_pex_l0_clkreq_n_pk0, + drive_pex_l0_rst_n_pk1, drive_pex_l2_rst_n_pk5, + drive_pex_l3_clkreq_n_pk6, drive_pex_l3_rst_n_pk7, + drive_pex_l4_clkreq_n_pl0, drive_pex_l4_rst_n_pl1, + drive_soc_gpio34_pl3, drive_pex_l5_clkreq_n_paf0, + drive_pex_l5_rst_n_paf1, drive_pex_l6_clkreq_n_paf2, + drive_pex_l6_rst_n_paf3, drive_pex_l10_clkreq_n_pag6, + drive_pex_l10_rst_n_pag7, drive_pex_l7_clkreq_n_pag0, + drive_pex_l7_rst_n_pag1, drive_pex_l8_clkreq_n_pag2, + drive_pex_l8_rst_n_pag3, drive_pex_l9_clkreq_n_pag4, + drive_pex_l9_rst_n_pag5, drive_sdmmc1_clk_pj0, + drive_sdmmc1_cmd_pj1, drive_sdmmc1_dat3_pj5, + drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3, + drive_sdmmc1_dat0_pj2 ] + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@2430000 { + compatible = "nvidia,tegra234-pinmux"; + reg = <0x2430000 0x17000>; + + pinctrl-names = "pex_rst"; + pinctrl-0 = <&pex_rst_c5_out_state>; + + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { + pexrst { + nvidia,pins = "pex_l5_rst_n_paf1"; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,io-hv = <TEGRA_PIN_ENABLE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml new file mode 100644 index 000000000..36c8f3301 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra30-pinmux.yaml @@ -0,0 +1,174 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra30-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra30-pinmux + + reg: + items: + - description: pad control registers + - description: mux registers + +patternProperties: + "^pinmux(-[a-z0-9-_]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + additionalProperties: false + properties: + nvidia,pins: + items: + enum: [ clk_32k_out_pa0, uart3_cts_n_pa1, dap2_fs_pa2, + dap2_sclk_pa3, dap2_din_pa4, dap2_dout_pa5, sdmmc3_clk_pa6, + sdmmc3_cmd_pa7, gmi_a17_pb0, gmi_a18_pb1, lcd_pwr0_pb2, + lcd_pclk_pb3, sdmmc3_dat3_pb4, sdmmc3_dat2_pb5, + sdmmc3_dat1_pb6, sdmmc3_dat0_pb7, uart3_rts_n_pc0, + lcd_pwr1_pc1, uart2_txd_pc2, uart2_rxd_pc3, + gen1_i2c_scl_pc4, gen1_i2c_sda_pc5, lcd_pwr2_pc6, + gmi_wp_n_pc7, sdmmc3_dat5_pd0, sdmmc3_dat4_pd1, + lcd_dc1_pd2, sdmmc3_dat6_pd3, sdmmc3_dat7_pd4, vi_d1_pd5, + vi_vsync_pd6, vi_hsync_pd7, lcd_d0_pe0, lcd_d1_pe1, + lcd_d2_pe2, lcd_d3_pe3, lcd_d4_pe4, lcd_d5_pe5, lcd_d6_pe6, + lcd_d7_pe7, lcd_d8_pf0, lcd_d9_pf1, lcd_d10_pf2, + lcd_d11_pf3, lcd_d12_pf4, lcd_d13_pf5, lcd_d14_pf6, + lcd_d15_pf7, gmi_ad0_pg0, gmi_ad1_pg1, gmi_ad2_pg2, + gmi_ad3_pg3, gmi_ad4_pg4, gmi_ad5_pg5, gmi_ad6_pg6, + gmi_ad7_pg7, gmi_ad8_ph0, gmi_ad9_ph1, gmi_ad10_ph2, + gmi_ad11_ph3, gmi_ad12_ph4, gmi_ad13_ph5, gmi_ad14_ph6, + gmi_ad15_ph7, gmi_wr_n_pi0, gmi_oe_n_pi1, gmi_dqs_pi2, + gmi_cs6_n_pi3, gmi_rst_n_pi4, gmi_iordy_pi5, gmi_cs7_n_pi6, + gmi_wait_pi7, gmi_cs0_n_pj0, lcd_de_pj1, gmi_cs1_n_pj2, + lcd_hsync_pj3, lcd_vsync_pj4, uart2_cts_n_pj5, + uart2_rts_n_pj6, gmi_a16_pj7, gmi_adv_n_pk0, gmi_clk_pk1, + gmi_cs4_n_pk2, gmi_cs2_n_pk3, gmi_cs3_n_pk4, spdif_out_pk5, + spdif_in_pk6, gmi_a19_pk7, vi_d2_pl0, vi_d3_pl1, vi_d4_pl2, + vi_d5_pl3, vi_d6_pl4, vi_d7_pl5, vi_d8_pl6, vi_d9_pl7, + lcd_d16_pm0, lcd_d17_pm1, lcd_d18_pm2, lcd_d19_pm3, + lcd_d20_pm4, lcd_d21_pm5, lcd_d22_pm6, lcd_d23_pm7, + dap1_fs_pn0, dap1_din_pn1, dap1_dout_pn2, dap1_sclk_pn3, + lcd_cs0_n_pn4, lcd_sdout_pn5, lcd_dc0_pn6, hdmi_int_pn7, + ulpi_data7_po0, ulpi_data0_po1, ulpi_data1_po2, + ulpi_data2_po3, ulpi_data3_po4, ulpi_data4_po5, + ulpi_data5_po6, ulpi_data6_po7, dap3_fs_pp0, dap3_din_pp1, + dap3_dout_pp2, dap3_sclk_pp3, dap4_fs_pp4, dap4_din_pp5, + dap4_dout_pp6, dap4_sclk_pp7, kb_col0_pq0, kb_col1_pq1, + kb_col2_pq2, kb_col3_pq3, kb_col4_pq4, kb_col5_pq5, + kb_col6_pq6, kb_col7_pq7, kb_row0_pr0, kb_row1_pr1, + kb_row2_pr2, kb_row3_pr3, kb_row4_pr4, kb_row5_pr5, + kb_row6_pr6, kb_row7_pr7, kb_row8_ps0, kb_row9_ps1, + kb_row10_ps2, kb_row11_ps3, kb_row12_ps4, kb_row13_ps5, + kb_row14_ps6, kb_row15_ps7, vi_pclk_pt0, vi_mclk_pt1, + vi_d10_pt2, vi_d11_pt3, vi_d0_pt4, gen2_i2c_scl_pt5, + gen2_i2c_sda_pt6, sdmmc4_cmd_pt7, pu0, pu1, pu2, pu3, pu4, + pu5, pu6, jtag_rtck_pu7, pv0, pv1, pv2, pv3, ddc_scl_pv4, + ddc_sda_pv5, crt_hsync_pv6, crt_vsync_pv7, lcd_cs1_n_pw0, + lcd_m1_pw1, spi2_cs1_n_pw2, spi2_cs2_n_pw3, clk1_out_pw4, + clk2_out_pw5, uart3_txd_pw6, uart3_rxd_pw7, spi2_mosi_px0, + spi2_miso_px1, spi2_sck_px2, spi2_cs0_n_px3, spi1_mosi_px4, + spi1_sck_px5, spi1_cs0_n_px6, spi1_miso_px7, ulpi_clk_py0, + ulpi_dir_py1, ulpi_nxt_py2, ulpi_stp_py3, sdmmc1_dat3_py4, + sdmmc1_dat2_py5, sdmmc1_dat1_py6, sdmmc1_dat0_py7, + sdmmc1_clk_pz0, sdmmc1_cmd_pz1, lcd_sdin_pz2, lcd_wr_n_pz3, + lcd_sck_pz4, sys_clk_req_pz5, pwr_i2c_scl_pz6, + pwr_i2c_sda_pz7, sdmmc4_dat0_paa0, sdmmc4_dat1_paa1, + sdmmc4_dat2_paa2, sdmmc4_dat3_paa3, sdmmc4_dat4_paa4, + sdmmc4_dat5_paa5, sdmmc4_dat6_paa6, sdmmc4_dat7_paa7, pbb0, + cam_i2c_scl_pbb1, cam_i2c_sda_pbb2, pbb3, pbb4, pbb5, pbb6, + pbb7, cam_mclk_pcc0, pcc1, pcc2, sdmmc4_rst_n_pcc3, + sdmmc4_clk_pcc4, clk2_req_pcc5, pex_l2_rst_n_pcc6, + pex_l2_clkreq_n_pcc7, pex_l0_prsnt_n_pdd0, + pex_l0_rst_n_pdd1, pex_l0_clkreq_n_pdd2, pex_wake_n_pdd3, + pex_l1_prsnt_n_pdd4, pex_l1_rst_n_pdd5, + pex_l1_clkreq_n_pdd6, pex_l2_prsnt_n_pdd7, clk3_out_pee0, + clk3_req_pee1, clk1_req_pee2, hdmi_cec_pee3, clk_32k_in, + core_pwr_req, cpu_pwr_req, owr, pwr_int_n, + # drive groups + drive_ao1, drive_ao2, drive_at1, drive_at2, drive_at3, + drive_at4, drive_at5, drive_cdev1, drive_cdev2, drive_cec, + drive_crt, drive_csus, drive_dap1, drive_dap2, drive_dap3, + drive_dap4, drive_dbg, drive_ddc, drive_dev3, drive_gma, + drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_gmf, + drive_gmg, drive_gmh, drive_gpv, drive_lcd1, drive_lcd2, + drive_owr, drive_sdio1, drive_sdio2, drive_sdio3, + drive_spi, drive_uaa, drive_uab, drive_uart2, drive_uart3, + drive_uda, drive_vi1 ] + + nvidia,function: + enum: [ blink, cec, clk_12m_out, clk_32k_in, core_pwr_req, + cpu_pwr_req, crt, dap, ddr, dev3, displaya, displayb, dtv, + extperiph1, extperiph2, extperiph3, gmi, gmi_alt, hda, hdcp, + hdmi, hsi, i2c1, i2c2, i2c3, i2c4, i2cpwr, i2s0, i2s1, i2s2, + i2s3, i2s4, invalid, kbc, mio, nand, nand_alt, owr, pcie, + pwm0, pwm1, pwm2, pwm3, pwr_int_n, rsvd1, rsvd2, rsvd3, + rsvd4, rtck, sata, sdmmc1, sdmmc2, sdmmc3, sdmmc4, spdif, + spi1, spi2, spi2_alt, spi3, spi4, spi5, spi6, sysclk, test, + trace, uarta, uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2, + vgp3, vgp4, vgp5, vgp6, vi, vi_alt1, vi_alt2, vi_alt3 ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,pull-down-strength: true + nvidia,pull-up-strength: true + nvidia,high-speed-mode: true + nvidia,low-power-mode: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,io-reset: true + nvidia,slew-rate-rising: true + nvidia,slew-rate-falling: true + + required: + - nvidia,pins + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + pinctrl@70000000 { + compatible = "nvidia,tegra30-pinmux"; + reg = <0x70000868 0x0d0>, /* Pad control registers */ + <0x70003000 0x3e0>; /* Mux registers */ + + pinmux { + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4", + "sdmmc4_rst_n_pcc3"; + nvidia,function = "sdmmc4"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + + sdmmc4_dat0_paa0 { + nvidia,pins = "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.yaml new file mode 100644 index 000000000..11f41359b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nxp,lpc1850-scu.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nxp,lpc1850-scu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC18xx/43xx SCU pin controller + +description: + Not all pins support all pin generic node properties so either refer to + the NXP 1850/4350 user manual or the pin table in the pinctrl-lpc18xx + driver for supported pin properties. + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: nxp,lpc1850-scu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '_cfg$': + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + unevaluatedProperties: false + + properties: + nxp,gpio-pin-interrupt: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + description: + Assign pin to gpio pin interrupt controller + irq number 0 to 7. See example below. + +required: + - compatible + - reg + - clocks + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/lpc18xx-ccu.h> + + pinctrl@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + + gpio-joystick-pins { + gpio-joystick-1_cfg { + pins = "p9_0"; + function = "gpio"; + nxp,gpio-pin-interrupt = <0>; + input-enable; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml new file mode 100644 index 000000000..a24286e4d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2 pin controller + +maintainers: + - Ghennadi Procopciuc <Ghennadi.Procopciuc@oss.nxp.com> + - Chester Lin <chester62515@gmail.com> + +description: | + S32G2 pinmux is implemented in SIUL2 (System Integration Unit Lite2), + whose memory map is split into two regions: + SIUL2_0 @ 0x4009c000 + SIUL2_1 @ 0x44010000 + + Every SIUL2 region has multiple register types, and here only MSCR and + IMCR registers need to be revealed for kernel to configure pinmux. + + Please note that some register indexes are reserved in S32G2, such as + MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429. + +properties: + compatible: + enum: + - nxp,s32g2-siul2-pinctrl + + reg: + description: | + A list of MSCR/IMCR register regions to be reserved. + - MSCR (Multiplexed Signal Configuration Register) + An MSCR register can configure the associated pin as either a GPIO pin + or a function output pin depends on the selected signal source. + - IMCR (Input Multiplexed Signal Configuration Register) + An IMCR register can configure the associated pin as function input + pin depends on the selected signal source. + items: + - description: MSCR registers group 0 in SIUL2_0 + - description: MSCR registers group 1 in SIUL2_1 + - description: MSCR registers group 2 in SIUL2_1 + - description: IMCR registers group 0 in SIUL2_0 + - description: IMCR registers group 1 in SIUL2_1 + - description: IMCR registers group 2 in SIUL2_1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '-grp[0-9]$': + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + description: | + Pinctrl node's client devices specify pin muxes using subnodes, + which in turn use the standard properties below. + + properties: + bias-disable: true + bias-high-impedance: true + bias-pull-up: true + bias-pull-down: true + drive-open-drain: true + input-enable: true + output-enable: true + + pinmux: + description: | + An integer array for representing pinmux configurations of + a device. Each integer consists of a PIN_ID and a 4-bit + selected signal source(SSS) as IOMUX setting, which is + calculated as: pinmux = (PIN_ID << 4 | SSS) + + slew-rate: + description: Supported slew rate based on Fmax values (MHz) + enum: [83, 133, 150, 166, 208] + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4009c240 { + compatible = "nxp,s32g2-siul2-pinctrl"; + + /* MSCR0-MSCR101 registers on siul2_0 */ + reg = <0x4009c240 0x198>, + /* MSCR112-MSCR122 registers on siul2_1 */ + <0x44010400 0x2c>, + /* MSCR144-MSCR190 registers on siul2_1 */ + <0x44010480 0xbc>, + /* IMCR0-IMCR83 registers on siul2_0 */ + <0x4009ca40 0x150>, + /* IMCR119-IMCR397 registers on siul2_1 */ + <0x44010c1c 0x45c>, + /* IMCR430-IMCR495 registers on siul2_1 */ + <0x440110f8 0x108>; + + llce-can0-pins { + llce-can0-grp0 { + pinmux = <0x2b0>; + input-enable; + slew-rate = <208>; + }; + + llce-can0-grp1 { + pinmux = <0x2c2>; + output-enable; + slew-rate = <208>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml new file mode 100644 index 000000000..97dbce8a2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml @@ -0,0 +1,266 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pincfg-node.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Pin Configuration Node + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: + Many data items that are represented in a pin configuration node are common + and generic. Pin control bindings should use the properties defined below + where they are applicable; not all of these properties are relevant or useful + for all hardware or binding structures. Each individual binding document + should state which of these generic properties, if any, are used, and the + structure of the DT nodes that contain these properties. + +properties: + bias-disable: + type: boolean + description: disable any pin bias + + bias-high-impedance: + type: boolean + description: high impedance mode ("third-state", "floating") + + bias-bus-hold: + type: boolean + description: latch weakly + + bias-pull-up: + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + description: pull up the pin. Takes as optional argument on hardware + supporting it the pull strength in Ohm. + + bias-pull-down: + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + description: pull down the pin. Takes as optional argument on hardware + supporting it the pull strength in Ohm. + + bias-pull-pin-default: + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + description: use pin-default pull state. Takes as optional argument on + hardware supporting it the pull strength in Ohm. + + drive-push-pull: + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + deprecated: true + description: drive actively high and low + + drive-open-drain: + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + const: 1 # No known cases of 0 + deprecated: true + description: drive with open drain + + drive-open-source: + type: boolean + description: drive with open source + + drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + description: sink or source at most X mA + + drive-strength-microamp: + description: sink or source at most X uA + + input-enable: + type: boolean + description: enable input on pin (no effect on output, such as + enabling an input buffer) + + input-disable: + type: boolean + description: disable input on pin (no effect on output, such as + disabling an input buffer) + + input-schmitt-enable: + type: boolean + description: enable schmitt-trigger mode + + input-schmitt-disable: + type: boolean + description: disable schmitt-trigger mode + + input-schmitt-microvolt: + description: threshold strength for schmitt-trigger + + input-debounce: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Takes the debounce time in usec as argument or 0 to disable + debouncing + + power-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: select between different power supplies + + low-power-enable: + type: boolean + description: enable low power mode + + low-power-disable: + type: boolean + description: disable low power mode + + output-disable: + type: boolean + description: disable output on a pin (such as disable an output buffer) + + output-enable: + type: boolean + description: enable output on a pin without actively driving it + (such as enabling an output buffer) + + output-impedance-ohms: + description: set the output impedance of a pin to at most X ohms + + output-low: + type: boolean + description: set the pin to output mode with low level + + output-high: + type: boolean + description: set the pin to output mode with high level + + sleep-hardware-state: + type: boolean + description: indicate this is sleep related state which will be + programmed into the registers for the sleep state. + + slew-rate: + $ref: /schemas/types.yaml#/definitions/uint32 + description: set the slew rate + + skew-delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + this affects the expected clock skew on input pins + and the delay before latching a value to an output + pin. Typically indicates how many double-inverters are + used to delay the signal. + + skew-delay-input-ps: + description: + this affects the expected clock skew in ps on an input pin. + + skew-delay-output-ps: + description: + this affects the expected delay in ps before latching a value to + an output pin. + + input-threshold-voltage-microvolt: + description: Specifies the input voltage level of the pin in microvolts. + This defines the reference for VIH (Input High Voltage) and VIL + (Input Low Voltage) thresholds for proper signal detection. + +allOf: + - if: + required: + - skew-delay + then: + properties: + skew-delay-input-ps: false + skew-delay-output-ps: false + + - if: + required: + - input-disable + then: + properties: + input-enable: false + input-threshold-voltage-microvolt: false + + - if: + required: + - output-disable + then: + properties: + output-enable: false + output-impedance-ohms: false + + - if: + required: + - output-low + then: + properties: + output-high: false + + - if: + required: + - low-power-enable + then: + properties: + low-power-disable: false + + - if: + required: + - input-schmitt-disable + then: + properties: + input-schmitt-enable: false + input-schmitt-microvolt: false + + - if: + required: + - drive-strength + then: + properties: + drive-strength-microamp: false + + - if: + anyOf: + - required: + - drive-open-source + - required: + - drive-open-drain + - required: + - drive-push-pull + then: + oneOf: + - required: + - drive-open-source + - required: + - drive-open-drain + - required: + - drive-push-pull + + - if: + anyOf: + - required: + - bias-disable + - required: + - bias-bus-hold + - required: + - bias-pull-up + - required: + - bias-pull-down + - required: + - bias-pull-pin-default + then: + oneOf: + - required: + - bias-disable + - required: + - bias-bus-hold + - required: + - bias-pull-up + - required: + - bias-pull-down + - required: + - bias-pull-pin-default + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt new file mode 100644 index 000000000..6904072d3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -0,0 +1,109 @@ +== Introduction == + +Hardware modules that control pin multiplexing or configuration parameters +such as pull-up/down, tri-state, drive-strength etc are designated as pin +controllers. Each pin controller must be represented as a node in device tree, +just like any other hardware module. + +Hardware modules whose signals are affected by pin configuration are +designated client devices. Again, each client device must be represented as a +node in device tree, just like any other hardware module. + +For a client device to operate correctly, certain pin controllers must +set up certain specific pin configurations. Some client devices need a +single static pin configuration, e.g. set up during initialization. Others +need to reconfigure pins at run-time, for example to tri-state pins when the +device is inactive. Hence, each client device can define a set of named +states. The number and names of those states is defined by the client device's +own binding. + +The common pinctrl bindings defined in this file provide an infrastructure +for client device device tree nodes to map those state names to the pin +configuration used by those states. + +Note that pin controllers themselves may also be client devices of themselves. +For example, a pin controller may set up its own "active" state when the +driver loads. This would allow representing a board's static pin configuration +in a single place, rather than splitting it across multiple client device +nodes. The decision to do this or not somewhat rests with the author of +individual board device tree files, and any requirements imposed by the +bindings for the individual client devices in use by that board, i.e. whether +they require certain specific named states for dynamic pin configuration. + +== Pinctrl client devices == + +For each client device individually, every pin state is assigned an integer +ID. These numbers start at 0, and are contiguous. For each state ID, a unique +property exists to define the pin configuration. Each state may also be +assigned a name. When names are used, another property exists to map from +those names to the integer IDs. + +Each client device's own binding determines the set of states that must be +defined in its device tree node, and whether to define the set of state +IDs that must be provided, or whether to define the set of state names that +must be provided. + +Required properties: +pinctrl-0: List of phandles, each pointing at a pin configuration + node. These referenced pin configuration nodes must be child + nodes of the pin controller that they configure. Multiple + entries may exist in this list so that multiple pin + controllers may be configured, or so that a state may be built + from multiple nodes for a single pin controller, each + contributing part of the overall configuration. See the next + section of this document for details of the format of these + pin configuration nodes. + + In some cases, it may be useful to define a state, but for it + to be empty. This may be required when a common IP block is + used in an SoC either without a pin controller, or where the + pin controller does not affect the HW module in question. If + the binding for that IP block requires certain pin states to + exist, they must still be defined, but may be left empty. + +Optional properties: +pinctrl-1: List of phandles, each pointing at a pin configuration + node within a pin controller. +... +pinctrl-n: List of phandles, each pointing at a pin configuration + node within a pin controller. +pinctrl-names: The list of names to assign states. List entry 0 defines the + name for integer state ID 0, list entry 1 for state ID 1, and + so on. + +For example: + + /* For a client device requiring named states */ + device { + pinctrl-names = "active", "idle"; + pinctrl-0 = <&state_0_node_a>; + pinctrl-1 = <&state_1_node_a>, <&state_1_node_b>; + }; + + /* For the same device if using state IDs */ + device { + pinctrl-0 = <&state_0_node_a>; + pinctrl-1 = <&state_1_node_a>, <&state_1_node_b>; + }; + + /* + * For an IP block whose binding supports pin configuration, + * but in use on an SoC that doesn't have any pin control hardware + */ + device { + pinctrl-names = "active", "idle"; + pinctrl-0 = <>; + pinctrl-1 = <>; + }; + +== Pin controller devices == + +See pinctrl.yaml + +== Generic pin multiplexing node content == + +See pinmux-node.yaml + +== Generic pin configuration node content == + +See pincfg-node.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt new file mode 100644 index 000000000..c28d4eb83 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-palmas.txt @@ -0,0 +1,105 @@ +Palmas Pincontrol bindings + +The pins of Palmas device can be set on different option and provides +the configuration for Pull UP/DOWN, open drain etc. + +Required properties: +- compatible: It must be one of following: + - "ti,palmas-pinctrl" for Palma series of the pincontrol. + - "ti,tps65913-pinctrl" for Palma series device TPS65913. + - "ti,tps80036-pinctrl" for Palma series device TPS80036. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Palmas's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +list of pins. This configuration can include the mux function to select on +those pin(s), and various pin configuration parameters, such as pull-up, +open drain. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + +Optional properties: +- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode. + Selection primary or secondary function associated to I2C2_SCL_SCE, + I2C2_SDA_SDO pin/pad for DVFS1 interface +- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode. + Selection primary or secondary function associated to GPADC_START + and SYSEN2 pin/pad for DVFS2 interface +- ti,palmas-override-powerhold: This is applicable for PMICs for which + GPIO7 is configured in POWERHOLD mode which has higher priority + over DEV_ON bit and keeps the PMIC supplies on even after the DEV_ON + bit is turned off. This property enables driver to over ride the + POWERHOLD value to GPIO7 so as to turn off the PMIC in power off + scenarios. So for GPIO7 if ti,palmas-override-powerhold is set + then the GPIO_7 field should never be muxed to anything else. + It should be set to POWERHOLD by default and only in case of + power off scenarios the driver will over ride the mux value. + +This binding uses the following generic properties as defined in +pinctrl-bindings.txt: + +Required: pins +Options: function, bias-disable, bias-pull-up, bias-pull-down, + drive-open-drain. + +Note that many of these properties are only valid for certain specific pins. +See the Palmas device datasheet for complete details regarding which pins +support which functionality. + +Valid values for pin names are: + gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, + gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood, + nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2, + int. + +Valid value of function names are: + gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det, + vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm, + simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start, + reset_in, nsleep, enable. + +There are 4 special functions: opt0, opt1, opt2 and opt3. If any of these +functions is selected then directly pins register will be written with 0, 1, 2 +or 3 respectively if it is valid for that pins or list of pins. + +Example: + palmas: tps65913 { + .... + pinctrl { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_pins_state>; + + palmas_pins_state: pinmux { + gpio0 { + pins = "gpio0"; + function = "id"; + bias-pull-up; + }; + + vac { + pins = "vac"; + function = "vacok"; + bias-pull-down; + }; + + gpio5 { + pins = "gpio5"; + function = "opt0"; + drive-open-drain = <1>; + }; + }; + }; + .... + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt new file mode 100644 index 000000000..6ad49e51c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-rk805.txt @@ -0,0 +1,63 @@ +Pincontrol driver for RK805 Power management IC. + +RK805 has 2 pins which can be configured as GPIO output only. + +Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt> +for details of the common pinctrl bindings used by client devices, +including the meaning of the phrase "pin configuration node". + +Optional Pinmux properties: +-------------------------- +Following properties are required if default setting of pins are required +at boot. +- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>. +- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per + <pinctrl-bindings.txt>. + +The pin configurations are defined as child of the pinctrl states node. Each +sub-node have following properties: + +Required properties: +------------------ +- #gpio-cells: Should be two. The first cell is the pin number and the + second is the GPIO flags. + +- gpio-controller: Marks the device node as a GPIO controller. + +- pins: List of pins. Valid values of pins properties are: gpio0, gpio1. + +First 2 properties must be added in the RK805 PMIC node, documented in +Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml + +Optional properties: +------------------- +Following are optional properties defined as pinmux DT binding document +<pinctrl-bindings.txt>. Absence of properties will leave the configuration +on default. + function, + output-low, + output-high. + +Valid values for function properties are: gpio. + +There are also not customised properties for any GPIO. + +Example: +-------- +rk805: rk805@18 { + compatible = "rockchip,rk805"; + ... + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&rk805_default>; + + rk805_default: pinmux { + gpio01 { + pins = "gpio0", "gpio1"; + function = "gpio"; + output-high; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml new file mode 100644 index 000000000..afe7329a1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml @@ -0,0 +1,224 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Pin Controller with a Single Register for One or More Pins + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: + Some pin controller devices use a single register for one or more pins. The + range of pin control registers can vary from one to many for each controller + instance. Some SoCs from Altera, Broadcom, HiSilicon, Ralink, and TI have this + kind of pin controller instances. + +properties: + compatible: + oneOf: + - enum: + - pinctrl-single + - pinconf-single + - items: + - enum: + - ti,am437-padconf + - ti,am62l-padconf + - ti,am654-padconf + - ti,dra7-padconf + - ti,omap2420-padconf + - ti,omap2430-padconf + - ti,omap3-padconf + - ti,omap4-padconf + - ti,omap5-padconf + - ti,j7200-padconf + - const: pinctrl-single + - items: + - enum: + - marvell,pxa1908-padconf + - const: pinconf-single + - items: + - enum: + - brcm,bcm7038-padconf + - const: pinctrl-single + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pinctrl-cells': + description: + Number of cells. Usually 2, consisting of register offset, pin configuration + value, and pinmux mode. Some controllers may use 1 for just offset and value. + enum: [ 1, 2 ] + + pinctrl-single,bit-per-mux: + description: Optional flag to indicate register controls more than one pin + type: boolean + + pinctrl-single,function-mask: + description: Mask of the allowed register bits + $ref: /schemas/types.yaml#/definitions/uint32 + + pinctrl-single,function-off: + description: Optional function off mode for disabled state + $ref: /schemas/types.yaml#/definitions/uint32 + + pinctrl-single,register-width: + description: Width of pin specific bits in the register + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 8, 16, 32 ] + + pinctrl-single,gpio-range: + description: Optional list of pin base, nr pins & gpio function + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of a gpio-range node + - description: pin base + - description: number of pins + - description: gpio function + + '#gpio-range-cells': + description: No longer needed, may exist in older files for gpio-ranges + deprecated: true + const: 3 + + gpio-range: + description: Optional node for gpio range cells + type: object + additionalProperties: false + properties: + '#pinctrl-single,gpio-range-cells': + description: Number of gpio range cells + const: 3 + $ref: /schemas/types.yaml#/definitions/uint32 + +patternProperties: + '-pins(-[0-9]+)?$|-pin$': + description: + Pin group node name using naming ending in -pins followed by an optional + instance number + type: object + additionalProperties: false + + properties: + pinctrl-single,pins: + description: + Array of pins as described in pinmux-node.yaml for pinctrl-pin-array + $ref: /schemas/types.yaml#/definitions/uint32-array + + pinctrl-single,bits: + description: Register bit configuration for pinctrl-single,bit-per-mux + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: register offset + - description: value + - description: pin bitmask in the register + + pinctrl-single,bias-pullup: + description: Optional bias pull up configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enabled pull up bits + - description: disabled pull up bits + - description: bias pull up mask + + pinctrl-single,bias-pulldown: + description: Optional bias pull down configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enabled pull down bits + - description: disabled pull down bits + - description: bias pull down mask + + pinctrl-single,drive-strength: + description: Optional drive strength configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: drive strength current + - description: drive strength mask + + pinctrl-single,input-schmitt: + description: Optional schmitt strength configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: schmitt strength current + - description: schmitt strength mask + + pinctrl-single,input-schmitt-enable: + description: Optional input schmitt configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: input + - description: enable bits + - description: disable bits + - description: input schmitt mask + + pinctrl-single,low-power-mode: + description: Optional low power mode configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: low power mode value + - description: low power mode mask + + pinctrl-single,slew-rate: + description: Optional slew rate configuration + $ref: /schemas/types.yaml#/definitions/uint32-array + items: + - description: slew rate + - description: slew rate mask + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - pinctrl-single,register-width + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + pinmux@4a100040 { + compatible = "pinctrl-single"; + reg = <0x4a100040 0x0196>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xffff>; + pinctrl-single,gpio-range = <&range 0 3 0>; + range: gpio-range { + #pinctrl-single,gpio-range-cells = <3>; + }; + + uart2-pins { + pinctrl-single,pins = + <0xd8 0x118>, + <0xda 0>, + <0xdc 0x118>, + <0xde 0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt new file mode 100644 index 000000000..f8420520e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-sirf.txt @@ -0,0 +1,47 @@ +CSR SiRFprimaII pinmux controller + +Required properties: +- compatible : "sirf,prima2-pinctrl" +- reg : Address range of the pinctrl registers +- interrupts : Interrupts used by every GPIO group +- gpio-controller : Indicates this device is a GPIO controller +- interrupt-controller : Marks the device node as an interrupt controller +Optional properties: +- sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m +- sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m + +Please refer to pinctrl-bindings.txt in this directory for details of the common +pinctrl bindings used by client devices. + +SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes. +Each of these subnodes represents some desired configuration for a group of pins. + +Required subnode-properties: +- sirf,pins : An array of strings. Each string contains the name of a group. +- sirf,function: A string containing the name of the function to mux to the + group. + + Valid values for group and function names can be found from looking at the + group and function arrays in driver files: + drivers/pinctrl/pinctrl-sirf.c + +For example, pinctrl might have subnodes like the following: + uart2_pins_a: uart2@0 { + uart { + sirf,pins = "uart2grp"; + sirf,function = "uart2"; + }; + }; + uart2_noflow_pins_a: uart2@1 { + uart { + sirf,pins = "uart2_nostreamctrlgrp"; + sirf,function = "uart2_nostreamctrl"; + }; + }; + +For a specific board, if it wants to use uart2 without hardware flow control, +it can add the following to its board-specific .dts file. +uart2: uart@b0070000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_noflow_pins_a>; +} diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt new file mode 100644 index 000000000..48b9be48a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-st.txt @@ -0,0 +1,174 @@ +*ST pin controller. + +Each multi-function pin is controlled, driven and routed through the +PIO multiplexing block. Each pin supports GPIO functionality (ALT0) +and multiple alternate functions(ALT1 - ALTx) that directly connect +the pin to different hardware blocks. + +When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and +Pull Up (PU) are driven by the related PIO block. + +ST pinctrl driver controls PIO multiplexing block and also interacts with +gpio driver to configure a pin. + +GPIO bank can have one of the two possible types of interrupt-wirings. + +First type is via irqmux, single interrupt is used by multiple gpio banks. This +reduces number of overall interrupts numbers required. All these banks belong to +a single pincontroller. + _________ + | |----> [gpio-bank (n) ] + | |----> [gpio-bank (n + 1)] + [irqN]-- | irq-mux |----> [gpio-bank (n + 2)] + | |----> [gpio-bank (... )] + |_________|----> [gpio-bank (n + 7)] + +Second type has a dedicated interrupt per gpio bank. + + [irqN]----> [gpio-bank (n)] + + +Pin controller node: +Required properties: +- compatible : should be "st,stih407-<pio-block>-pinctrl" +- st,syscfg : Should be a phandle of the syscfg node. +- st,retime-pin-mask : Should be mask to specify which pins can be retimed. + If the property is not present, it is assumed that all the pins in the + bank are capable of retiming. Retiming is mainly used to improve the + IO timing margins of external synchronous interfaces. +- ranges : defines mapping between pin controller node (parent) to gpio-bank + node (children). + +Optional properties: +- interrupts : Interrupt number of the irqmux. If the interrupt is shared + with other gpio banks via irqmux. + a irqline and gpio banks. +- reg : irqmux memory resource. If irqmux is present. +- reg-names : irqmux resource should be named as "irqmux". + +GPIO controller/bank node. +Required properties: +- gpio-controller : Indicates this device is a GPIO controller +- #gpio-cells : Must be two. + - First cell: specifies the pin number inside the controller + - Second cell: specifies whether the pin is logically inverted. + - 0 = active high + - 1 = active low +- st,bank-name : Should be a name string for this bank as specified in + datasheet. + +Optional properties: +- interrupts : Interrupt number for this gpio bank. If there is a dedicated + interrupt wired up for this gpio bank. + +- interrupt-controller : Indicates this device is a interrupt controller. GPIO + bank can be an interrupt controller iff one of the interrupt type either via +irqmux or a dedicated interrupt per bank is specified. + +- #interrupt-cells: the value of this property should be 2. + - First Cell: represents the external gpio interrupt number local to the + gpio interrupt space of the controller. + - Second Cell: flags to identify the type of the interrupt + - 1 = rising edge triggered + - 2 = falling edge triggered + - 3 = rising and falling edge triggered + - 4 = high level triggered + - 8 = low level triggered +for related macros look in: +include/dt-bindings/interrupt-controller/irq.h + +Example: + pin-controller-sbc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stih407-sbc-pinctrl"; + st,syscfg = <&syscfg_sbc>; + reg = <0x0961f080 0x4>; + reg-names = "irqmux"; + interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; + interrupt-names = "irqmux"; + ranges = <0 0x09610000 0x6000>; + + pio0: gpio@9610000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO0"; + }; + ... + pin-functions nodes follow... + }; + + +Contents of function subnode node: +---------------------- +Required properties for pin configuration node: +- st,pins : Child node with list of pins with configuration. + +Below is the format of how each pin conf should look like. + +<bank offset mux mode rt_type rt_delay rt_clk> + +Every PIO is represented with 4-7 parameters depending on retime configuration. +Each parameter is explained as below. + +-bank : Should be bank phandle to which this PIO belongs. +-offset : Offset in the PIO bank. +-mux : Should be alternate function number associated this pin. + Use same numbers from datasheet. +-mode :pin configuration is selected from one of the below values. + IN + IN_PU + OUT + BIDIR + BIDIR_PU + +-rt_type Retiming Configuration for the pin. + Possible retime configuration are: + + ------- ------------- + value args + ------- ------------- + NICLK <delay> <clk> + ICLK_IO <delay> <clk> + BYPASS <delay> + DE_IO <delay> <clk> + SE_ICLK_IO <delay> <clk> + SE_NICLK_IO <delay> <clk> + +- delay is retime delay in pico seconds as mentioned in data sheet. + +- rt_clk :clk to be use for retime. + Possible values are: + CLK_A + CLK_B + CLK_C + CLK_D + +Example of mmcclk pin which is a bi-direction pull pu with retime config +as non inverted clock retimed with CLK_B and delay of 0 pico seconds: + +pin-controller { + ... + mmc0 { + pinctrl_mmc: mmc { + st,pins { + mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + ... + }; + }; + ... + }; +}; + +sdhci0:sdhci@fe810000{ + ... + interrupt-parent = <&pio3>; + #interrupt-cells = <2>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */ + interrupt-names = "card-detect"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc>; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt new file mode 100644 index 000000000..b3aa90f0c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt @@ -0,0 +1,57 @@ +VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller + +These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as +either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc). + +Required properties: +- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl", + "wm8750-pinctrl" or "wm,wm8850-pinctrl" +- reg: Should contain the physical address of the module's registers. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Should be two. +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters. + bit 0 - active low + +Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Each pin configuration node lists the pin(s) to which it applies, and one or +more of the mux functions to select on those pin(s), and pull-up/down +configuration. Each subnode only affects those parameters that are explicitly +listed. In other words, a subnode that lists only a mux function implies no +information about any pull configuration. Similarly, a subnode that lists only +a pull parameter implies no information about the mux function. + +Required subnode-properties: +- wm,pins: An array of cells. Each cell contains the ID of a pin. + +Optional subnode-properties: +- wm,function: Integer, containing the function to mux to the pin(s): + 0: GPIO in + 1: GPIO out + 2: alternate + +- wm,pull: Integer, representing the pull-down/up to apply to the pin(s): + 0: none + 1: down + 2: up + +Each of wm,function and wm,pull may contain either a single value which +will be applied to all pins in wm,pins, or one value for each entry in +wm,pins. + +Example: + + pinctrl: pinctrl { + compatible = "wm,wm8505-pinctrl"; + reg = <0xD8110000 0x10000>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml new file mode 100644 index 000000000..290438826 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin controller device + +maintainers: + - Linus Walleij <linusw@kernel.org> + - Rafał Miłecki <rafal@milecki.pl> + +description: | + Pin controller devices should contain the pin configuration nodes that client + devices reference. + + The contents of each of those pin configuration child nodes is defined + entirely by the binding for the individual pin controller device. There + exists no common standard for this content. The pinctrl framework only + provides generic helper bindings that the pin controller driver can use. + + The pin configuration nodes need not be direct children of the pin controller + device; they may be grandchildren, for example. Whether this is legal, and + whether there is any interaction between the child and intermediate parent + nodes, is again defined entirely by the binding for the individual pin + controller device. + +properties: + $nodename: + pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$" + + "#pinctrl-cells": + description: > + Number of pin control cells in addition to the index within the pin + controller device instance. + + pinctrl-use-default: + type: boolean + description: > + Indicates that the OS can use the boot default pin configuration. This + allows using an OS that does not have a driver for the pin controller. + This property can be set either globally for the pin controller or in + child nodes for individual pin group control. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt new file mode 100644 index 000000000..458615596 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl_spear.txt @@ -0,0 +1,155 @@ +ST Microelectronics, SPEAr pinmux controller + +Required properties: +- compatible : "st,spear300-pinmux" + : "st,spear310-pinmux" + : "st,spear320-pinmux" + : "st,spear1310-pinmux" + : "st,spear1340-pinmux" +- reg : Address range of the pinctrl registers +- st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others. + - Its values for SPEAr300: + - NAND_MODE : <0> + - NOR_MODE : <1> + - PHOTO_FRAME_MODE : <2> + - LEND_IP_PHONE_MODE : <3> + - HEND_IP_PHONE_MODE : <4> + - LEND_WIFI_PHONE_MODE : <5> + - HEND_WIFI_PHONE_MODE : <6> + - ATA_PABX_WI2S_MODE : <7> + - ATA_PABX_I2S_MODE : <8> + - CAML_LCDW_MODE : <9> + - CAMU_LCD_MODE : <10> + - CAMU_WLCD_MODE : <11> + - CAML_LCD_MODE : <12> + - Its values for SPEAr320: + - AUTO_NET_SMII_MODE : <0> + - AUTO_NET_MII_MODE : <1> + - AUTO_EXP_MODE : <2> + - SMALL_PRINTERS_MODE : <3> + - EXTENDED_MODE : <4> + +Please refer to pinctrl-bindings.txt in this directory for details of the common +pinctrl bindings used by client devices. + +SPEAr's pinmux nodes act as a container for an arbitrary number of subnodes. Each +of these subnodes represents muxing for a pin, a group, or a list of pins or +groups. + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Required subnode-properties: +- st,pins : An array of strings. Each string contains the name of a pin or + group. +- st,function: A string containing the name of the function to mux to the pin or + group. See the SPEAr's TRM to determine which are valid for each pin or group. + + Valid values for group and function names can be found from looking at the + group and function arrays in driver files: + drivers/pinctrl/spear/pinctrl-spear3*0.c + +Valid values for group names are: +For All SPEAr3xx machines: + "firda_grp", "i2c0_grp", "ssp_cs_grp", "ssp0_grp", "mii0_grp", + "gpio0_pin0_grp", "gpio0_pin1_grp", "gpio0_pin2_grp", "gpio0_pin3_grp", + "gpio0_pin4_grp", "gpio0_pin5_grp", "uart0_ext_grp", "uart0_grp", + "timer_0_1_grp", timer_0_1_pins, "timer_2_3_grp" + +For SPEAr300 machines: + "fsmc_2chips_grp", "fsmc_4chips_grp", "clcd_lcdmode_grp", + "clcd_pfmode_grp", "tdm_grp", "i2c_clk_grp_grp", "caml_grp", "camu_grp", + "dac_grp", "i2s_grp", "sdhci_4bit_grp", "sdhci_8bit_grp", + "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" + +For SPEAr310 machines: + "emi_cs_0_to_5_grp", "uart1_grp", "uart2_grp", "uart3_grp", "uart4_grp", + "uart5_grp", "fsmc_grp", "rs485_0_grp", "rs485_1_grp", "tdm_grp" + +For SPEAr320 machines: + "clcd_grp", "emi_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "spp_grp", + "sdhci_led_grp", "sdhci_cd_12_grp", "sdhci_cd_51_grp", "i2s_grp", + "uart1_grp", "uart1_modem_2_to_7_grp", "uart1_modem_31_to_36_grp", + "uart1_modem_34_to_45_grp", "uart1_modem_80_to_85_grp", "uart2_grp", + "uart3_8_9_grp", "uart3_15_16_grp", "uart3_41_42_grp", + "uart3_52_53_grp", "uart3_73_74_grp", "uart3_94_95_grp", + "uart3_98_99_grp", "uart4_6_7_grp", "uart4_13_14_grp", + "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", + "uart4_100_101_grp", "uart5_4_5_grp", "uart5_37_38_grp", + "uart5_69_70_grp", "uart5_90_91_grp", "uart6_2_3_grp", + "uart6_88_89_grp", "rs485_grp", "touchscreen_grp", "can0_grp", + "can1_grp", "pwm0_1_pin_8_9_grp", "pwm0_1_pin_14_15_grp", + "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", "pwm0_1_pin_42_43_grp", + "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp", "pwm2_pin_7_grp", + "pwm2_pin_13_grp", "pwm2_pin_29_grp", "pwm2_pin_34_grp", + "pwm2_pin_41_grp", "pwm2_pin_58_grp", "pwm2_pin_87_grp", + "pwm3_pin_6_grp", "pwm3_pin_12_grp", "pwm3_pin_28_grp", + "pwm3_pin_40_grp", "pwm3_pin_57_grp", "pwm3_pin_86_grp", + "ssp1_17_20_grp", "ssp1_36_39_grp", "ssp1_48_51_grp", "ssp1_65_68_grp", + "ssp1_94_97_grp", "ssp2_13_16_grp", "ssp2_32_35_grp", "ssp2_44_47_grp", + "ssp2_61_64_grp", "ssp2_90_93_grp", "mii2_grp", "smii0_1_grp", + "rmii0_1_grp", "i2c1_8_9_grp", "i2c1_98_99_grp", "i2c2_0_1_grp", + "i2c2_2_3_grp", "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" + +For SPEAr1310 machines: + "i2c0_grp", "ssp0_grp", "ssp0_cs0_grp", "ssp0_cs1_2_grp", "i2s0_grp", + "i2s1_grp", "clcd_grp", "clcd_high_res_grp", "arm_gpio_grp", + "smi_2_chips_grp", "smi_4_chips_grp", "gmii_grp", "rgmii_grp", + "smii_0_1_2_grp", "ras_mii_txclk_grp", "nand_8bit_grp", + "nand_16bit_grp", "nand_4_chips_grp", "keyboard_6x6_grp", + "keyboard_rowcol6_8_grp", "uart0_grp", "uart0_modem_grp", + "gpt0_tmr0_grp", "gpt0_tmr1_grp", "gpt1_tmr0_grp", "gpt1_tmr1_grp", + "sdhci_grp", "cf_grp", "xd_grp", "touch_xy_grp", + "uart1_disable_i2c_grp", "uart1_disable_sd_grp", "uart2_3_grp", + "uart4_grp", "uart5_grp", "rs485_0_1_tdm_0_1_grp", "i2c_1_2_grp", + "i2c3_dis_smi_clcd_grp", "i2c3_dis_sd_i2s0_grp", "i2c_4_5_dis_smi_grp", + "i2c4_dis_sd_grp", "i2c5_dis_sd_grp", "i2c_6_7_dis_kbd_grp", + "i2c6_dis_sd_grp", "i2c7_dis_sd_grp", "can0_dis_nor_grp", + "can0_dis_sd_grp", "can1_dis_sd_grp", "can1_dis_kbd_grp", "pcie0_grp", + "pcie1_grp", "pcie2_grp", "sata0_grp", "sata1_grp", "sata2_grp", + "ssp1_dis_kbd_grp", "ssp1_dis_sd_grp", "gpt64_grp" + +For SPEAr1340 machines: + "pads_as_gpio_grp", "fsmc_8bit_grp", "fsmc_16bit_grp", "fsmc_pnor_grp", + "keyboard_row_col_grp", "keyboard_col5_grp", "spdif_in_grp", + "spdif_out_grp", "gpt_0_1_grp", "pwm0_grp", "pwm1_grp", "pwm2_grp", + "pwm3_grp", "vip_mux_grp", "vip_mux_cam0_grp", "vip_mux_cam1_grp", + "vip_mux_cam2_grp", "vip_mux_cam3_grp", "cam0_grp", "cam1_grp", + "cam2_grp", "cam3_grp", "smi_grp", "ssp0_grp", "ssp0_cs1_grp", + "ssp0_cs2_grp", "ssp0_cs3_grp", "uart0_grp", "uart0_enh_grp", + "uart1_grp", "i2s_in_grp", "i2s_out_grp", "gmii_grp", "rgmii_grp", + "rmii_grp", "sgmii_grp", "i2c0_grp", "i2c1_grp", "cec0_grp", "cec1_grp", + "sdhci_grp", "cf_grp", "xd_grp", "clcd_grp", "arm_trace_grp", + "miphy_dbg_grp", "pcie_grp", "sata_grp" + +Valid values for function names are: +For All SPEAr3xx machines: + "firda", "i2c0", "ssp_cs", "ssp0", "mii0", "gpio0", "uart0_ext", + "uart0", "timer_0_1", "timer_2_3" + +For SPEAr300 machines: + "fsmc", "clcd", "tdm", "i2c1", "cam", "dac", "i2s", "sdhci", "gpio1" + +For SPEAr310 machines: + "emi", "uart1", "uart2", "uart3", "uart4", "uart5", "fsmc", "rs485_0", + "rs485_1", "tdm" + +For SPEAr320 machines: + "clcd", "emi", "fsmc", "spp", "sdhci", "i2s", "uart1", "uart1_modem", + "uart2", "uart3", "uart4", "uart5", "uart6", "rs485", "touchscreen", + "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2", + "mii0_1", "i2c1", "i2c2" + + +For SPEAr1310 machines: + "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii", + "rgmii", "smii_0_1_2", "ras_mii_txclk", "nand", "keyboard", "uart0", + "gpt0", "gpt1", "sdhci", "cf", "xd", "touchscreen", "uart1", "uart2_3", + "uart4", "uart5", "rs485_0_1_tdm_0_1", "i2c_1_2", "i2c3_i2s1", + "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64" + +For SPEAr1340 machines: + "pads_as_gpio", "fsmc", "keyboard", "spdif_in", "spdif_out", "gpt_0_1", + "pwm", "vip", "cam0", "cam1", "cam2", "cam3", "smi", "ssp0", "uart0", + "uart1", "i2s", "gmac", "i2c0", "i2c1", "cec0", "cec1", "sdhci", "cf", + "xd", "clcd", "arm_trace", "miphy_dbg", "pcie", "sata" diff --git a/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml b/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml new file mode 100644 index 000000000..7ba26271c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Pin Multiplexing Node + +maintainers: + - Linus Walleij <linusw@kernel.org> + +description: | + The contents of the pin configuration child nodes are defined by the binding + for the individual pin controller device. The pin configuration nodes need not + be direct children of the pin controller device; they may be grandchildren, + for example. Whether this is legal, and whether there is any interaction + between the child and intermediate parent nodes, is again defined entirely by + the binding for the individual pin controller device. + + While not required to be used, there are 3 generic forms of pin muxing nodes + which pin controller devices can use. + + pin multiplexing nodes: + + Example: + + state_0_node_a { + uart0 { + function = "uart0"; + groups = "u0rxtx", "u0rtscts"; + }; + }; + state_1_node_a { + spi { + function = "spi0"; + groups = "spi0pins"; + }; + }; + state_2_node_a { + function = "i2c0"; + pins = "mfio29", "mfio30"; + }; + + Optionally an alternative binding can be used if more suitable depending on the + pin controller hardware. For hardware where there is a large number of identical + pin controller instances, naming each pin and function can easily become + unmaintainable. This is especially the case if the same controller is used for + different pins and functions depending on the SoC revision and packaging. + + For cases like this, the pin controller driver may use pinctrl-pin-array helper + binding with a hardware based index and a number of pin configuration values: + + pincontroller { + ... /* Standard DT properties for the device itself elided */ + #pinctrl-cells = <2>; + + state_0_node_a { + pinctrl-pin-array = < + 0 A_DELAY_PS(0) G_DELAY_PS(120) + 4 A_DELAY_PS(0) G_DELAY_PS(360) + ... + >; + }; + ... + }; + + Above #pinctrl-cells specifies the number of value cells in addition to the + index of the registers. This is similar to the interrupts-extended binding with + one exception. There is no need to specify the phandle for each entry as that + is already known as the defined pins are always children of the pin controller + node. Further having the phandle pointing to another pin controller would not + currently work as the pinctrl framework uses named modes to group pins for each + pin control device. + + The index for pinctrl-pin-array must relate to the hardware for the pinctrl + registers, and must not be a virtual index of pin instances. The reason for + this is to avoid mapping of the index in the dts files and the pin controller + driver as it can change. + + For hardware where pin multiplexing configurations have to be specified for + each single pin the number of required sub-nodes containing "pin" and + "function" properties can quickly escalate and become hard to write and + maintain. + + For cases like this, the pin controller driver may use the pinmux helper + property, where the pin identifier is provided with mux configuration settings + in a pinmux group. A pinmux group consists of the pin identifier and mux + settings represented as a single integer or an array of integers. + + The pinmux property accepts an array of pinmux groups, each of them describing + a single pin multiplexing configuration. + + pincontroller { + state_0_node_a { + pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...; + }; + }; + + Each individual pin controller driver bindings documentation shall specify + how pin IDs and pin multiplexing configuration are defined and assembled + together in a pinmux group. + +properties: + function: + $ref: /schemas/types.yaml#/definitions/string + description: The mux function to select + + pins: + oneOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + - $ref: /schemas/types.yaml#/definitions/string-array + description: + The list of pin identifiers that properties in the node apply to. The + specific binding for the hardware defines whether the entries are integers + or strings, and their meaning. + + groups: + $ref: /schemas/types.yaml#/definitions/string-array + description: + the group to apply the properties to, if the driver supports + configuration of whole groups rather than individual pins (either + this, "pins" or "pinmux" has to be specified) + + pinmux: + description: + The list of numeric pin ids and their mux settings that properties in the + node apply to (either this, "pins" or "groups" have to be specified) + $ref: /schemas/types.yaml#/definitions/uint32-array + + pinctrl-pin-array: + $ref: /schemas/types.yaml#/definitions/uint32-array + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml new file mode 100644 index 000000000..f251dcd4b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,apq8064-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. APQ8064 TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm APQ8064 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,apq8064-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-apq8064-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-apq8064-tlmm-state" + additionalProperties: false + +$defs: + qcom-apq8064-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-8][0-9])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd, sdc3_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, + gp_clk_0b, gp_clk_1a, gp_clk_1b, gp_clk_2a, gp_clk_2b, + gpio, gsbi1, gsbi2, gsbi3, gsbi4, gsbi4_cam_i2c, + gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, + gsbi6, gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, + gsbi7, gsbi7_spi_cs1, gsbi7_spi_cs2, gsbi7_spi_cs3, + gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, riva_wlan, + sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, + ps_hold ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@800000 { + compatible = "qcom,apq8064-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 90>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + + uart-state { + rx-pins { + pins = "gpio52"; + function = "gsbi5"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio51"; + function = "gsbi5"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.yaml new file mode 100644 index 000000000..38877d8b9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,apq8084-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,apq8084-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. APQ8084 TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm APQ8084 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,apq8084-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-apq8084-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-apq8084-tlmm-state" + additionalProperties: false + +$defs: + qcom-apq8084-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-6])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, + sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, audio_ref, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, + blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, + blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, + blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6, + blsp_spi7, blsp_spi8, blsp_spi9, blsp_spi10, + blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, + blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, + blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, + blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10, + blsp_uart11, blsp_uart12, blsp_uim1, blsp_uim2, + blsp_uim3, blsp_uim4, blsp_uim5, blsp_uim6, blsp_uim7, + blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11, + blsp_uim12, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, + cci_async, cci_async_in0, cci_i2c0, cci_i2c1, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, edp_hpd, gcc_gp1, gcc_gp2, gcc_gp3, + gcc_obt, gcc_vtt, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, + gp0_clk, gp1_clk, gpio, hdmi_cec, hdmi_ddc, hdmi_dtest, + hdmi_hpd, hdmi_rcv, hsic, ldo_en, ldo_update, + mdp_vsync, pci_e0, pci_e0_n, pci_e0_rst, pci_e1, + pci_e1_rst, pci_e1_rst_n, pci_e1_clkreq_n, pri_mi2s, + qua_mi2s, sata_act, sata_devsleep, sata_devsleep_n, + sd_write, sdc_emmc_mode, sdc3, sdc4, sec_mi2s, slimbus, + spdif_tx, spkr_i2s, spkr_i2s_ws, spss_geni, ter_mi2s, + tsif1, tsif2, uim, uim_batt_alarm ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@fd510000 { + compatible = "qcom,apq8084-pinctrl"; + reg = <0xfd510000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 147>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + uart-state { + rx-pins { + pins = "gpio5"; + function = "blsp_uart2"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio4"; + function = "blsp_uart2"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml new file mode 100644 index 000000000..282650426 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Eliza TLMM block + +maintainers: + - Abel Vesa <abel.vesa@oss.qualcomm.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,eliza-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 93 + + gpio-line-names: + maxItems: 185 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-eliza-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-eliza-tlmm-state" + additionalProperties: false + +$defs: + qcom-eliza-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-4])$" + - enum: [ ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl, + cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx, + coex_uart2_rx, coex_uart2_tx, dbg_out_clk, + ddr_bist_complete, ddr_bist_fail, ddr_bist_start, + ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio, + gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, + hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1, + hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec, + host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out, + mdp_vsync, mdp_vsync0_out, mdp_vsync11_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk, + qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, + qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi_clk, + qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, + qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, + sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, + tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, + uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, + uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, + vsense_trigger_mirnat, wcn_sw_ctrl ] + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f100000 { + compatible = "qcom,eliza-tlmm"; + reg = <0x0f100000 0x300000>; + + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 186>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + qup-uart14-default-state { + pins = "gpio18", "gpio19"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml new file mode 100644 index 000000000..2836a1a10 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,glymur-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Glymur TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Glymur and Mahua SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + enum: + - qcom,glymur-tlmm + - qcom,mahua-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 125 + + gpio-line-names: + maxItems: 250 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-glymur-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-glymur-tlmm-state" + additionalProperties: false + +$defs: + qcom-glymur-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-4][0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, resout_gpio_n, aoss_cti, asc_cci, atest_char, atest_usb, + audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, cam_asc_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, cri_trng, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi, + edp0_hot, edp0_lcd, edp1_lcd, egpio, eusb0_ac_en, eusb1_ac_en, + eusb2_ac_en, eusb3_ac_en, eusb5_ac_en, eusb6_ac_en, gcc_gp1, + gcc_gp2, gcc_gp3, host2wlan_sol, i2c0_s_scl, i2c0_s_sda, + i2s0_data, i2s0_sck, i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws, + ibi_i3c, jitter_bist, mdp_vsync_out, mdp_vsync_e, mdp_vsync_p, + mdp_vsync_s, pcie3a_clk, pcie3a_rst_n, pcie3b_clk, + pcie4_clk_req_n, pcie5_clk_req_n, pcie6_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, pmc_oca_n, pmc_uva_n, prng_rosc, + qdss_cti, qdss_gpio, qspi, qup0_se0, qup0_se1, qup0_se2, + qup0_se3_l0, qup0_se3, qup0_se4, qup0_se5, qup0_se6, qup0_se7, + qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, + qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, + qup2_se4, qup2_se5, qup2_se6, qup2_se7, qup3_se0, qup3_se1, + sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, smb_acok_n, + sys_throttle, tb_trig_sdc2, tb_trig_sdc4, tmess_prng, + tsense_pwm, tsense_therm, usb0_dp, usb0_phy_ps, usb0_sbrx, + usb0_sbtx, usb0_tmu, usb1_dbg, usb1_dp, usb1_phy_ps, usb1_sbrx, + usb1_sbtx, usb1_tmu, usb2_dp, usb2_phy_ps, usb2_sbrx, usb2_sbtx, + usb2_tmu, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,glymur-tlmm"; + reg = <0x0f100000 0xf00000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 249>; + wakeup-parent = <&pdc>; + gpio-reserved-ranges = <4 4>, <10 2>, <33 3>, <44 4>; + qup_uart21_default: qup-uart21-default-state { + tx-pins { + pins = "gpio86"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml new file mode 100644 index 000000000..3b3961789 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Hawi TLMM block + +maintainers: + - Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,hawi-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 113 + + gpio-line-names: + maxItems: 226 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-hawi-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-hawi-tlmm-state" + additionalProperties: false + +$defs: + qcom-hawi-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk, + audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1, + cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi, + coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi, + dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0, + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1, + ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2, + mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3, + nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n, + phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink, + qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, + qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, + qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23, + qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3, + qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01, + qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3, + rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, + sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm, + uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat, + wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f100000 { + compatible = "qcom,hawi-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 227>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml new file mode 100644 index 000000000..cc5de9f77 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq4019-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. IPQ4019 TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ4019 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq4019-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq4019-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq4019-tlmm-state" + additionalProperties: false + + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + +$defs: + qcom-ipq4019-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-9][0-9])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, + blsp_spi1, blsp_uart0, blsp_uart1, chip_rst, gpio, + i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx, + jtag, led0, led1, led2, led3, led4, led5, led6, led7, + led8, led9, led10, led11, mdc, mdio, pcie, pmu, + prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1, + smart2, smart3, tm, wifi0, wifi1 ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq4019-pinctrl"; + reg = <0x01000000 0x300000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 100>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + uart-state { + pins = "gpio16", "gpio17"; + function = "blsp_uart0"; + bias-disable; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml new file mode 100644 index 000000000..96635b2f6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-tlmm.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5018 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC. + +properties: + compatible: + const: qcom,ipq5018-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 24 + + gpio-line-names: + maxItems: 47 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5018-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5018-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5018-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$" + minItems: 1 + maxItems: 8 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd, + audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd, + audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0, + blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1, + blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1, + blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng, + cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio, + gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio, + pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test, + prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, + qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs, + qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd, + wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ] + + required: + - pins + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5018-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 47>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + uart-w-state { + rx-pins { + pins = "gpio33"; + function = "blsp1_uart1"; + bias-pull-down; + }; + + tx-pins { + pins = "gpio34"; + function = "blsp1_uart1"; + bias-pull-down; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml new file mode 100644 index 000000000..12c5e7623 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5210 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5210-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 54 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5210-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5210-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5210-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char_start, atest_char_status0, atest_char_status1, + atest_char_status2, atest_char_status3, atest_tic_en, audio_pri, + audio_pri_mclk_out0, audio_pri_mclk_in0, audio_pri_mclk_out1, + audio_pri_mclk_in1, audio_pri_mclk_out2, audio_pri_mclk_in2, + audio_pri_mclk_out3, audio_pri_mclk_in3, audio_sec, + audio_sec_mclk_out0, audio_sec_mclk_in0, audio_sec_mclk_out1, + audio_sec_mclk_in1, audio_sec_mclk_out2, audio_sec_mclk_in2, + audio_sec_mclk_out3, audio_sec_mclk_in3, core_voltage_0, + cri_trng0, cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out, + gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, led0, + led1, led2, mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst, + mdio_slv0, mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n, + pcie0_wake, pcie1_clk_req_n, pcie1_wake, pll_test, + pon_active_led, pon_mux_sel, pon_rx, pon_rx_los, pon_tx, + pon_tx_burst, pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los, + gpn_tx_burst, gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm0, + pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a, + qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2, + qspi_data, qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, + qup_se3, qup_se4, qup_se5, qup_se5_l1, resout, rx_los0, rx_los1, + rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5210-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <0x2>; + + qup-uart1-default-state { + pins = "gpio38", "gpio39"; + function = "qup_se1"; + drive-strength = <6>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml new file mode 100644 index 000000000..22685c479 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5332 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5332-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 53 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5332-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5332-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5332-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, + audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0, + blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1, + blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1, + blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0, + cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, + gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1, + mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, + pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3, + qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0, + rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd, + wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5332-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 53>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <0x2>; + + serial0-state { + pins = "gpio18", "gpio19"; + function = "blsp0_uart0"; + drive-strength = <8>; + bias-pull-up; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml new file mode 100644 index 000000000..df284d364 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5424-tlmm.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5424-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ5424 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ5424 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq5424-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 25 + + gpio-line-names: + maxItems: 50 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq5424-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq5424-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq5424-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9])$" + minItems: 1 + maxItems: 50 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec, + audio_sec0, audio_sec1, core_voltage, cri_trng0, cri_trng1, + cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out, gcc_plltest, + gcc_tlmm, gpio, i2c0_scl, i2c0_sda, i2c1_scl, i2c1_sda, i2c11, + mac0, mac1, mdc_mst, mdc_slv, mdio_mst, mdio_slv, pcie0_clk, + pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, + pcie3_clk, pcie3_wake, pll_test, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, PTA0_0, PTA0_1, PTA0_2, PTA10, PTA11, + pwm0, pwm1, pwm2, qdss_cti_trig_in_a0, qdss_cti_trig_out_a0, + qdss_cti_trig_in_a1, qdss_cti_trig_out_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk, + qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd, + sdc_data, spi0_cs, spi0_clk, spi0_miso, spi0_mosi, spi1, spi10, + spi11, tsens_max, uart0, uart1, wci_txd, wci_rxd, wsi_clk, wsi_data ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5424-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 50>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <0x2>; + + uart1_pins: uart1-state { + pins = "gpio43", "gpio44"; + function = "uart1"; + drive-strength = <8>; + bias-pull-up; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml new file mode 100644 index 000000000..ed00fbaec --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq6018-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. IPQ6018 TLMM block + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ6018 SoC. + +properties: + compatible: + const: qcom,ipq6018-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq6018-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq6018-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq6018-tlmm-state: + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([1-9]|[1-7][0-9]|80)$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, + sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, + qdsd_data3 ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, + atest_char0, atest_char1, atest_char2, atest_char3, atest_combodac, + atest_gpsadc0, atest_gpsadc1, atest_tsens, atest_wlan0, + atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, blsp0_i2c, blsp1_i2c, + blsp2_i2c, blsp3_i2c, blsp4_i2c, blsp5_i2c, blsp0_spi, blsp1_spi, + blsp1_spi_cs1, blsp1_spi_cs2, blsp1_spi_cs3, blsp2_spi, + blsp2_spi_cs1, blsp2_spi_cs2, blsp2_spi_cs3, blsp3_spi, + blsp3_spi_cs1, blsp3_spi_cs2, blsp3_spi_cs3, blsp4_spi, blsp5_spi, + blsp0_uart, blsp1_uart, blsp2_uart, blsp1_uim, blsp2_uim, cam1_rst, + cam1_standby, cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, display_5v, + dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, euro_us, ext_lpass, + flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, + gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gpio, gsm0_tx0, + gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, kpsns1, kpsns2, + ldo_en, ldo_update, mag_int, mdp_vsync, modem_tsync, m_voc, + nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, + pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a, + pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, + qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, + qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, + qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, qpic_pad, reset_n, sd_card, + sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, uim1, uim2, + uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan, webcam1_rst ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq6018-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 80>; + + serial3-state { + pins = "gpio44", "gpio45"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.yaml new file mode 100644 index 000000000..58f11e1bd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8064-pinctrl.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. IPQ8064 TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq8064-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq8064-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq8064-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq8064-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-8])$" + - enum: [ sdc3_clk, sdc3_cmd, sdc3_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5, + gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1, + spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata, + pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt, + pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren, + pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n, + pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@800000 { + compatible = "qcom,ipq8064-pinctrl"; + reg = <0x00800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 69>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + + uart-state { + rx-pins { + pins = "gpio19"; + function = "gsbi5"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio18"; + function = "gsbi5"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml new file mode 100644 index 000000000..40def3ac3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ8074 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC. + +properties: + compatible: + const: qcom,ipq8074-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 35 + + gpio-line-names: + maxItems: 70 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq8074-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq8074-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq8074-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-6][0-9]|70)$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync, + audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, + audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c, + blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart, + blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2, + blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0, + blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi, + blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0, + cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0, + led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2, + mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst, + pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, + pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, + pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3, + qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write, + tsens_max, wci2a, wci2b, wci2c, wci2d ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq8074-pinctrl"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <0x2>; + gpio-ranges = <&tlmm 0 0 70>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <0x2>; + + serial4-state { + pins = "gpio23", "gpio24"; + function = "blsp4_uart1"; + drive-strength = <8>; + bias-disable; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml new file mode 100644 index 000000000..7afec315b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. IPQ9574 TLMM block + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ9574 SoC. + +properties: + compatible: + const: qcom,ipq9574-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 33 + + gpio-line-names: + maxItems: 65 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq9574-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq9574-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq9574-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$" + minItems: 1 + maxItems: 8 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + audio_pdm0, audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart, + blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, + blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c, + blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0, + cri_trng1, cri_trng2, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy, + gcc_plltest, gcc_tlmm, gpio, mac, mdc, mdio, pcie0_clk, pcie0_wake, + pcie1_clk, pcie1_wake, pcie2_clk, pcie2_wake, pcie3_clk, pcie3_wake, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, pta, pwm, + qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data, + rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max, + wci20, wci21, wsa_swrm ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9574-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 65>; + + uart2-state { + pins = "gpio34", "gpio35"; + function = "blsp2_uart"; + drive-strength = <8>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml new file mode 100644 index 000000000..53534a07a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,kaanapali-tlmm.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,kaanapali-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Kaanapali TLMM block + +maintainers: + - Jingyi Wang <jingyi.wang@oss.qualcomm.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Kaanapali SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,kaanapali-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 109 + + gpio-line-names: + maxItems: 217 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-kaanapali-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-kaanapali-tlmm-state" + additionalProperties: false + +$defs: + qcom-kaanapali-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-6])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_asc_mclk2, cam_asc_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, + coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, + ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2, + ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, + gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3, + i2chub0_se4, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, + mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio_traceclk, qdss_gpio_tracectl, qdss_gpio_tracedata, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup3_se0, qup3_se1, qup3_se2, + qup3_se3, qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, + qup4_se3, qup4_se4, sd_write_protect, sdc40, sdc41, sdc42, sdc43, + sdc4_clk, sdc4_cmd, sys_throttle, tb_trig_sdc2, tb_trig_sdc4, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, tsense_pwm5, tsense_pwm6, + tsense_pwm7, uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, + vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f100000 { + compatible = "qcom,kaanapali-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 218>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio62", "gpio63"; + function = "qup1_se7"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml new file mode 100644 index 000000000..30f93b815 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,lpass-lpi-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoC LPASS LPI TLMM Common Properties + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Common properties for the Top Level Mode Multiplexer pin controllers in the + Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm SoCs. + +properties: + gpio-controller: true + + "#gpio-cells": + description: + Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 30 + description: + Pins can be reserved for trusted applications or for LPASS, thereby + inaccessible from the OS. This property can be used to mark the pins + which resources should not be accessed by the OS. + +required: + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: true + +$defs: + qcom-tlmm-state: + properties: + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + slew-rate: + enum: [0, 1, 2, 3] + default: 0 + description: | + 0: No adjustments + 1: Higher Slew rate (faster edges) + 2: Lower Slew rate (slower edges) + 3: Reserved (No adjustments) + + bias-bus-hold: true + bias-pull-down: true + bias-pull-up: true + bias-disable: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + additionalProperties: true + diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml new file mode 100644 index 000000000..e75393b3d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9607-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MDM9607 TLMM block + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MDM9607 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,mdm9607-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-mdm9607-tlmm-state" + - additionalProperties: false + patternProperties: + ".*": + $ref: "#/$defs/qcom-mdm9607-tlmm-state" + +$defs: + qcom-mdm9607-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([1-9]|[1-7][0-9]|80)$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, + sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, + qdsd_data3 ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, + atest_combodac_to_gpio_native, atest_gpsadc_dtest0_native, + atest_gpsadc_dtest1_native, atest_tsens, backlight_en_b, + bimc_dte0, bimc_dte1, blsp1_spi, blsp2_spi, blsp3_spi, + blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, + blsp_i2c6, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, + blsp_spi5, blsp_spi6, blsp_uart1, blsp_uart2, blsp_uart3, + blsp_uart4, blsp_uart5, blsp_uart6, blsp_uim1, blsp_uim2, + codec_int, codec_rst, coex_uart, cri_trng, cri_trng0, + cri_trng1, dbg_out, ebi0_wrcdc, ebi2_a, ebi2_a_d_8_b, + ebi2_lcd, ebi2_lcd_cs_n_b, ebi2_lcd_te_b, eth_irq, eth_rst, + gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, + gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gmac_mdio, + gpio, gsm0_tx, lcd_rst, ldo_en, ldo_update, m_voc, modem_tsync, + nav_ptp_pps_in_a, nav_ptp_pps_in_b, nav_tsync_out_a, + nav_tsync_out_b, pa_indicator, pbs0, pbs1, pbs2, + pri_mi2s_data0_a, pri_mi2s_data1_a, pri_mi2s_mclk_a, + pri_mi2s_sck_a, pri_mi2s_ws_a, prng_rosc, ptp_pps_out_a, + ptp_pps_out_b, pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a, + pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, + qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, rcm_marker1, + rcm_marker2, sd_write, sec_mi2s, sensor_en, sensor_int2, + sensor_int3, sensor_rst, ssbi1, ssbi2, touch_rst, ts_int, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, + uim2_data, uim2_present, uim2_reset, uim_batt, wlan_en1, ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1000000 { + compatible = "qcom,mdm9607-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 80>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml new file mode 100644 index 000000000..299e0b4b0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MDM9615 TLMM block + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC. + +$ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,mdm9615-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-mdm9615-pinctrl-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-mdm9615-pinctrl-state" + additionalProperties: false + +$defs: + qcom-mdm9615-pinctrl-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$" + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart, + sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1000000 { + compatible = "qcom,mdm9615-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 88>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + gsbi3-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + + gsbi5-i2c-state { + sda-pins { + pins = "gpio16"; + function = "gsbi5_i2c"; + drive-strength = <8>; + bias-disable; + }; + + scl-pins { + pins = "gpio17"; + function = "gsbi5_i2c"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..73e84f188 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos SoC LPASS LPI TLMM + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm Milos SoC. + +properties: + compatible: + const: qcom,milos-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-milos-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-milos-lpass-state" + additionalProperties: false + +$defs: + qcom-milos-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, qca_swr_clk, + qca_swr_data, slimbus_clk, slimbus_data, swr_rx_clk, + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> + + pinctrl@3440000 { + compatible = "qcom,milos-lpass-lpi-pinctrl"; + reg = <0x03440000 0x20000>, + <0x034d0000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + tx-swr-active-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <4>; + slew-rate = <1>; + bias-disable; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,milos-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,milos-tlmm.yaml new file mode 100644 index 000000000..0091204df --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,milos-tlmm.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,milos-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Milos TLMM block + +maintainers: + - Luca Weiss <luca.weiss@fairphone.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Milos SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,milos-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 84 + + gpio-line-names: + maxItems: 167 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-milos-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-milos-tlmm-state" + additionalProperties: false + +$defs: + qcom-milos-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-7])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_mclk, cci_async_in0, + cci_i2c_scl, cci_i2c_sda, cci_timer, coex_uart1_rx, + coex_uart1_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, + ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, + egpio, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync, + mdp_vsync0_out, mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk_req_n, + pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio, qlink0_enable, qlink0_request, qlink0_wmss, + qlink1_enable, qlink1_request, qlink1_wmss, qspi0, qup0_se0, + qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, qup0_se6, + qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, + qup1_se6, resout_gpio_n, sd_write_protect, sdc1_clk, sdc1_cmd, + sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data, + sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tgu_ch0_trigout, + tgu_ch1_trigout, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, + uim0_present, uim0_reset, uim1_clk_mira, uim1_clk_mirb, + uim1_data_mira, uim1_data_mirb, uim1_present_mira, + uim1_present_mirb, uim1_reset_mira, uim1_reset_mirb, usb0_hs, + usb0_phy_ps, vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw, + wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,milos-tlmm"; + reg = <0x0f100000 0x300000>; + + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 168>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + qup-uart5-default-state { + pins = "gpio25", "gpio26"; + function = "qup0_se5"; + drive-strength = <2>; + bias-disable; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml new file mode 100644 index 000000000..68d3fa210 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM8226 TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8226 SoC. + +properties: + compatible: + const: qcom,msm8226-pinctrl + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8226-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8226-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8226-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5, + blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_i2c6, + blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2, + blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, + gp0_clk, gp1_clk, sdc3, wlan ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8226-pinctrl"; + reg = <0xfd510000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&msmgpio 0 0 117>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + serial-state { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + drive-strength = <8>; + bias-disable; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml new file mode 100644 index 000000000..203ad69e9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8660-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8660 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8660 SoC. + +properties: + compatible: + const: qcom,msm8660-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 86 + + gpio-line-names: + maxItems: 173 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8660-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8660-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8660-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-2])$" + - enum: [ sdc3_clk, sdc3_cmd, sdc3_data, sdc4_clk, sdc4_cmd, sdc4_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, cam_mclk, dsub, ext_gps, gp_clk_0a, gp_clk_0b, gp_clk_1a, + gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gsbi1, gsbi1_spi_cs1_n, + gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, gsbi1_spi_cs3_n, gsbi2, + gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, gsbi2_spi_cs3_n, gsbi3, + gsbi3_spi_cs1_n, gsbi3_spi_cs2_n, gsbi3_spi_cs3_n, gsbi4, + gsbi5, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, gsbi12, + hdmi, i2s, lcdc, mdp_vsync, mi2s, pcm, ps_hold, sdc1, sdc2, + sdc5, tsif1, tsif2, usb_fs1, usb_fs1_oe_n, usb_fs2, + usb_fs2_oe_n, vfe, vsens_alarm, ebi2, ebi2cs ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@800000 { + compatible = "qcom,msm8660-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + gpio-ranges = <&tlmm 0 0 173>; + #gpio-cells = <2>; + interrupts = <0 16 0x4>; + interrupt-controller; + #interrupt-cells = <2>; + + gsbi3-i2c-state { + pins = "gpio43", "gpio44"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml new file mode 100644 index 000000000..295dd5fcf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM8909 TLMM block + +maintainers: + - Stephan Gerhold <stephan@gerhold.net> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm MSM8909 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,msm8909-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8909-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8909-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8909-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, + sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, + qdsd_data2, qdsd_data3 ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, atest_bbrx0, atest_bbrx1, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, atest_combodac, + atest_gpsadc0, atest_gpsadc1, atest_wlan0, atest_wlan1, + bimc_dte0, bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_spi1, blsp_spi1_cs1, + blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, + blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1, + blsp_spi3_cs2, blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6, + blsp_uart1, blsp_uart2, blsp_uim1, blsp_uim2, cam_mclk, + cci_async, cci_timer0, cci_timer1, cci_timer2, cdc_pdm0, + dbg_out, dmic0_clk, dmic0_data, ebi0_wrcdc, ebi2_a, ebi2_lcd, + ext_lpass, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, + gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gpio, + gsm0_tx, ldo_en, ldo_update, m_voc, mdp_vsync, modem_tsync, + nav_pps, nav_tsync, pa_indicator, pbs0, pbs1, pbs2, + pri_mi2s_data0_a, pri_mi2s_data0_b, pri_mi2s_data1_a, + pri_mi2s_data1_b, pri_mi2s_mclk_a, pri_mi2s_mclk_b, + pri_mi2s_sck_a, pri_mi2s_sck_b, pri_mi2s_ws_a, pri_mi2s_ws_b, + prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a, + pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a, + qdss_tracedata_a, qdss_tracedata_b, sd_write, sec_mi2s, + smb_int, ssbi0, ssbi1, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, + uim3_clk, uim3_data, uim3_present, uim3_reset, uim_batt, + wcss_bt, wcss_fm, wcss_wlan ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@1000000 { + compatible = "qcom,msm8909-tlmm"; + reg = <0x1000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 113>; + interrupt-controller; + #interrupt-cells = <2>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio4"; + function = "blsp_uart1"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio5"; + function = "blsp_uart1"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml new file mode 100644 index 000000000..9bf098cf1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8916-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8916 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8916 SoC. + +properties: + compatible: + const: qcom,msm8916-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 61 + + gpio-line-names: + maxItems: 122 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8916-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8916-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8916-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[01])$" + - enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, + qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, + sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, atest_char, + atest_char0, atest_char1, atest_char2, atest_char3, + atest_combodac, atest_gpsadc0, atest_gpsadc1, atest_tsens, + atest_wlan0, atest_wlan1, backlight_en, bimc_dte0, bimc_dte1, + blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, + blsp_i2c6, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, + blsp_spi1_cs3, blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, + blsp_spi2_cs3, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, + blsp_spi3_cs3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_uart1, + blsp_uart2, blsp_uim1, blsp_uim2, cam1_rst, cam1_standby, + cam_mclk0, cam_mclk1, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cdc_pdm0, codec_mad, dbg_out, + display_5v, dmic0_clk, dmic0_data, dsi_rst, ebi0_wrcdc, + euro_us, ext_lpass, flash_strobe, gcc_gp1_clk_a, gcc_gp1_clk_b, + gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, + gsm0_tx0, gsm0_tx1, gsm1_tx0, gsm1_tx1, gyro_accl, kpsns0, + kpsns1, kpsns2, ldo_en, ldo_update, mag_int, mdp_vsync, + modem_tsync, m_voc, nav_pps, nav_tsync, pa_indicator, pbs0, + pbs1, pbs2, pri_mi2s, pri_mi2s_ws, prng_rosc, + pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a, + pwr_nav_enabled_b, qdss_ctitrig_in_a0, qdss_ctitrig_in_a1, + qdss_ctitrig_in_b0, qdss_ctitrig_in_b1, qdss_ctitrig_out_a0, + qdss_ctitrig_out_a1, qdss_ctitrig_out_b0, qdss_ctitrig_out_b1, + qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, + qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, reset_n, + sd_card, sd_write, sec_mi2s, smb_int, ssbi_wtr0, ssbi_wtr1, + uim1, uim2, uim3, uim_batt, wcss_bt, wcss_fm, wcss_wlan, + webcam1_rst ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + msmgpio: pinctrl@1000000 { + compatible = "qcom,msm8916-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 122>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl.yaml new file mode 100644 index 000000000..16d0c010e --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8917-pinctrl.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8917-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8917 TLMM pin controller + +maintainers: + - Barnabas Czeman <barnabas.czeman@mainlining.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8917 SoC. + +properties: + compatible: + const: qcom,msm8917-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 66 + + gpio-line-names: + maxItems: 134 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8917-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8917-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8917-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-3])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, + qdsd_data1, qdsd_data2, qdsd_data3 ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, + atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_combodac_to_gpio_native, + atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, + atest_tsens, atest_wlan0, atest_wlan1, audio_ref, + audio_reset, bimc_dte0, bimc_dte1, blsp6_spi, blsp8_spi, + blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, + blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, blsp_spi2, + blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, + blsp_spi8, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, + blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, cam0_ldo, + cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam_mclk, + cci_async, cci_i2c, cci_timer0, cci_timer1, cdc_pdm0, + codec_int1, codec_int2, codec_mad, coex_uart, cri_trng, + cri_trng0, cri_trng1, dbg_out, dmic0_clk, dmic0_data, + ebi_cdc, ebi_ch0, ext_lpass, forced_usb, fp_gpio, fp_int, + gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, + gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, + gsm0_tx, key_focus, key_snapshot, key_volp, ldo_en, + ldo_update, lpass_slimbus, lpass_slimbus0, lpass_slimbus1, + m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, nav_pps, + nav_pps_in_a, nav_pps_in_b, nav_tsync, nfc_pwr, ov_ldo, + pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_mclk_a, + pri_mi2s_mclk_b, pri_mi2s_ws, prng_rosc, + pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a, + pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, sd_write, sdcard_det, + sec_mi2s, sec_mi2s_mclk_a, sec_mi2s_mclk_b, sensor_rst, + smb_int, ssbi_wtr1, ts_resout, ts_sample, uim1_clk, + uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, uim_batt, us_emitter, us_euro, + wcss_bt, wcss_fm, wcss_wlan, wcss_wlan0, wcss_wlan1, + wcss_wlan2, webcam_rst, webcam_standby, wsa_io, wsa_irq ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8917-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart2-sleep-state { + pins = "gpio4", "gpio5"; + function = "gpio"; + + drive-strength = <2>; + bias-pull-down; + }; + + spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml new file mode 100644 index 000000000..8a3a962f6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8953-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM8953 TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8953 SoC. + +properties: + compatible: + const: qcom,msm8953-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8953-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8953-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8953-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[01])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, + qdsd_data1, qdsd_data2, qdsd_data3 ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1, + atest_char, atest_char0, atest_char1, atest_char2, atest_char3, + atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native, atest_tsens, + atest_wlan0, atest_wlan1, bimc_dte0, bimc_dte1, blsp1_spi, + blsp3_spi, blsp6_spi, blsp7_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, + blsp_spi2, blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, + blsp_spi8, blsp_uart2, blsp_uart4, blsp_uart5, blsp_uart6, cam0_ldo, + cam1_ldo, cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam3_rst, + cam3_standby, cam_irq, cam_mclk, cap_int, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cdc_pdm0, codec_int1, codec_int2, codec_reset, cri_trng, cri_trng0, + cri_trng1, dac_calib0, dac_calib1, dac_calib10, dac_calib11, + dac_calib12, dac_calib13, dac_calib14, dac_calib15, dac_calib16, + dac_calib17, dac_calib18, dac_calib19, dac_calib2, dac_calib20, + dac_calib21, dac_calib22, dac_calib23, dac_calib24, dac_calib25, + dac_calib3, dac_calib4, dac_calib5, dac_calib6, dac_calib7, + dac_calib8, dac_calib9, dbg_out, ddr_bist, dmic0_clk, dmic0_data, + ebi_cdc, ebi_ch0, ext_lpass, flash_strobe, fp_int, gcc_gp1_clk_a, + gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, + gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio, gsm0_tx, gsm1_tx, + gyro_int, hall_int, hdmi_int, key_focus, key_home, key_snapshot, + key_volp, ldo_en, ldo_update, lpass_slimbus, lpass_slimbus0, + lpass_slimbus1, m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, + mss_lte, nav_pps, nav_pps_in_a, nav_pps_in_b, nav_tsync, + nfc_disable, nfc_dwl, nfc_irq, ois_sync, pa_indicator, pbs0, pbs1, + pbs2, pressure_int, pri_mi2s, pri_mi2s_mclk_a, pri_mi2s_mclk_b, + pri_mi2s_ws, prng_rosc, pwr_crypto_enabled_a, pwr_crypto_enabled_b, + pwr_down, pwr_modem_enabled_a, pwr_modem_enabled_b, + pwr_nav_enabled_a, pwr_nav_enabled_b, qdss_cti_trig_in_a0, + qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, sd_write, sdcard_det, sec_mi2s, sec_mi2s_mclk_a, + sec_mi2s_mclk_b, smb_int, ss_switch, ssbi_wtr1, ts_resout, + ts_sample, ts_xvdd, tsens_max, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, + uim_batt, us_emitter, us_euro, wcss_bt, wcss_fm, wcss_wlan, + wcss_wlan0, wcss_wlan1, wcss_wlan2, wsa_en, wsa_io, wsa_irq ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8953-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 142>; + + serial_default: serial-state { + pins = "gpio4", "gpio5"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-disable; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml new file mode 100644 index 000000000..730131809 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8960-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8960 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8960 SoC. + +properties: + compatible: + const: qcom,msm8960-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 76 + + gpio-line-names: + maxItems: 152 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8960-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8960-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8960-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-1])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc3_clk, sdc3_cmd, + sdc3_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, audio_pcm, bt, cam_mclk0, cam_mclk1, cam_mclk2, + codec_mic_i2s, codec_spkr_i2s, ext_gps, fm, gps_blanking, + gps_pps_in, gps_pps_out, gp_clk_0a, gp_clk_0b, gp_clk_1a, + gp_clk_1b, gp_clk_2a, gp_clk_2b, gp_mn, gp_pdm_0a, gp_pdm_0b, + gp_pdm_1a, gp_pdm_1b, gp_pdm_2a, gp_pdm_2b, gsbi1, + gsbi1_spi_cs1_n, gsbi1_spi_cs2a_n, gsbi1_spi_cs2b_n, + gsbi1_spi_cs3_n, gsbi2, gsbi2_spi_cs1_n, gsbi2_spi_cs2_n, + gsbi2_spi_cs3_n, gsbi3, gsbi4, gsbi4_3d_cam_i2c_l, + gsbi4_3d_cam_i2c_r, gsbi5, gsbi5_3d_cam_i2c_l, + gsbi5_3d_cam_i2c_r, gsbi6, gsbi7, gsbi8, gsbi9, gsbi10, gsbi11, + gsbi11_spi_cs1a_n, gsbi11_spi_cs1b_n, gsbi11_spi_cs2a_n, + gsbi11_spi_cs2b_n, gsbi11_spi_cs3_n, gsbi12, hdmi_cec, + hdmi_ddc_clock, hdmi_ddc_data, hdmi_hot_plug_detect, hsic, + mdp_vsync, mi2s, mic_i2s, pmb_clk, pmb_ext_ctrl, ps_hold, + rpm_wdog, sdc2, sdc4, sdc5, slimbus1, slimbus2, spkr_i2s, + ssbi1, ssbi2, ssbi_ext_gps, ssbi_pmic2, ssbi_qpa1, ssbi_ts, + tsif1, tsif2, ts_eoc, usb_fs1, usb_fs1_oe, usb_fs1_oe_n, + usb_fs2, usb_fs2_oe, usb_fs2_oe_n, vfe_camif_timer1_a, + vfe_camif_timer1_b, vfe_camif_timer2, vfe_camif_timer3_a, + vfe_camif_timer3_b, vfe_camif_timer4_a, vfe_camif_timer4_b, + vfe_camif_timer4_c, vfe_camif_timer5_a, vfe_camif_timer5_b, + vfe_camif_timer6_a, vfe_camif_timer6_b, vfe_camif_timer6_c, + vfe_camif_timer7_a, vfe_camif_timer7_b, vfe_camif_timer7_c, + wlan ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@800000 { + compatible = "qcom,msm8960-pinctrl"; + reg = <0x800000 0x4000>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 152>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + spi1-default-state { + mosi-pins { + pins = "gpio6"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + miso-pins { + pins = "gpio7"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio8"; + function = "gpio"; + drive-strength = <12>; + bias-disable; + output-low; + }; + + clk-pins { + pins = "gpio9"; + function = "gsbi1"; + drive-strength = <12>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml new file mode 100644 index 000000000..a9aff4428 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8974-pinctrl.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8974 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8974 SoC. + +properties: + compatible: + const: qcom,msm8974-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 73 + + gpio-line-names: + maxItems: 146 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8974-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8974-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8974-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$" + - enum: [ hsic_data, hsic_strobe, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, cci_i2c0, cci_i2c1, uim1, uim2, uim_batt_alarm, + blsp_uim1, blsp_uart1, blsp_i2c1, blsp_spi1, blsp_uim2, + blsp_uart2, blsp_i2c2, blsp_spi2, blsp_uim3, blsp_uart3, + blsp_i2c3, blsp_spi3, blsp_uim4, blsp_uart4, blsp_i2c4, + blsp_spi4, blsp_uim5, blsp_uart5, blsp_i2c5, blsp_spi5, + blsp_uim6, blsp_uart6, blsp_i2c6, blsp_spi6, blsp_uim7, + blsp_uart7, blsp_i2c7, blsp_spi7, blsp_uim8, blsp_uart8, + blsp_i2c8, blsp_spi8, blsp_uim9, blsp_uart9, blsp_i2c9, + blsp_spi9, blsp_uim10, blsp_uart10, blsp_i2c10, blsp_spi10, + blsp_uim11, blsp_uart11, blsp_i2c11, blsp_spi11, blsp_uim12, + blsp_uart12, blsp_i2c12, blsp_spi12, blsp_spi1_cs1, + blsp_spi2_cs2, blsp_spi_cs3, blsp_spi2_cs1, blsp_spi2_cs2 + blsp_spi2_cs3, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, + sdc3, sdc4, gcc_gp_clk1, gcc_gp_clk2, gcc_gp_clk3, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_async_in0, + cci_async_in1, cci_async_in2, cam_mckl0, cam_mclk1, cam_mclk2, + cam_mclk3, mdp_vsync, hdmi_cec, hdmi_ddc, hdmi_hpd, edp_hpd, + gp_pdm0, gp_pdm1, gp_pdm2, gp_pdm3, gp0_clk, gp1_clk, gp_mn, + tsif1, tsif2, hsic, grfc, audio_ref_clk, qua_mi2s, pri_mi2s, + spkr_mi2s, ter_mi2s, sec_mi2s, bt, fm, wlan, slimbus, hsic_ctl ] + + required: + - pins + + allOf: + - if: + properties: + pins: + contains: + enum: + - hsic_data + - hsic_strobe + required: + - pins + then: + properties: + bias-pull-down: false + bias-pull-up: false + bias-disable: false + drive-strength: false + input-enable: false + output-high: false + output-low: false + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8974-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd-pins { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data-pins { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + blsp2-uart1-sleep-state { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + hsic-state { + pins = "hsic_data", "hsic_strobe"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml new file mode 100644 index 000000000..501329bff --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8976-pinctrl.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8976-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8976 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8976 SoC. + +properties: + compatible: + const: qcom,msm8976-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 73 + + gpio-line-names: + maxItems: 145 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8976-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8976-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8976-tlmm-state: + type: object + description: + Desired pin configuration for a device or its specific state (like sleep + or active). + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this state. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-4])$" + - enum: [ qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2, + qdsd_data3, sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2, + blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3, + qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b, + blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5, + qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a, + qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b, + blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a, + sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi, + blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a, + uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset, + uim1_present, uim2_data, uim2_clk, uim2_reset, uim2_present, + ts_xvdd, mipi_dsi0, us_euro, ts_resout, ts_sample, + sec_mi2s_mclk_b, pri_mi2s, codec_reset, cdc_pdm0, us_emitter, + pri_mi2s_mclk_b, pri_mi2s_mclk_c, lpass_slimbus, + lpass_slimbus0, lpass_slimbus1, codec_int1, codec_int2, + wcss_bt, sdc3, wcss_wlan2, wcss_wlan1, wcss_wlan0, wcss_wlan, + wcss_fm, key_volp, key_snapshot, key_focus, key_home, pwr_down, + dmic0_clk, hdmi_int, dmic0_data, wsa_vi, wsa_en, blsp_spi8, + wsa_irq, blsp_i2c8, pa_indicator, modem_tsync, ssbi_wtr1, + gsm1_tx, gsm0_tx, sdcard_det, sec_mi2s, ss_switch ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,msm8976-pinctrl"; + reg = <0x1000000 0x300000>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 145>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart2-active-state { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "blsp_uart2"; + drive-strength = <2>; + bias-disable; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml new file mode 100644 index 000000000..2ec10908d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8994 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC. + +properties: + compatible: + enum: + - qcom,msm8992-pinctrl + - qcom,msm8994-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 73 + + gpio-line-names: + maxItems: 146 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8994-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8994-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8994-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, + blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, + blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, + blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, + blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, + blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, + blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, + blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, + blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, + blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, + blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, + blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1, + cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1, + cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a, + gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, + gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, + gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, + hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync, + qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c, + qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b, + qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1, + pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1, + tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8994-pinctrl"; + reg = <0xfd510000 0x4000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart2-default-state { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + + blsp1-spi1-default-state { + default-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <10>; + bias-pull-down; + }; + + cs-pins { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml new file mode 100644 index 000000000..496f38009 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8996-pinctrl.yaml @@ -0,0 +1,168 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8996-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8996 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8996 SoC. + +properties: + compatible: + const: qcom,msm8996-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 75 + + gpio-line-names: + maxItems: 150 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8996-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8996-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8996-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, + atest_char, cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, + qdss_tracedata_b, pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, + atest_usb2, cci_i2c, qdss_stm3, dac_calib3, atest_usb23, + atest_char3, dac_calib4, qdss_stm2, atest_usb22, atest_char2, + qdss_stm1, dac_calib5, atest_usb21, atest_char1, dbg_out, + qdss_stm0, dac_calib6, atest_usb20, atest_char0, dac_calib10, + qdss_stm10, qdss_cti_trig_in_a, cci_timer4, blsp_spi6, + blsp_uart6, blsp_uim6, blsp2_spi, qdss_stm9, + qdss_cti_trig_out_a, dac_calib11, qdss_stm8, cci_timer0, + qdss_stm13, dac_calib7, cci_timer1, qdss_stm12, dac_calib8, + cci_timer2, blsp1_spi, qdss_stm11, dac_calib9, cci_timer3, + cci_async, dac_calib12, blsp_i2c6, qdss_tracectl_a, + dac_calib13, qdss_traceclk_a, dac_calib14, dac_calib15, + hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, dac_calib17, + hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, dac_calib19, + hdmi_hot, dac_calib20, dac_calib21, pci_e0, dac_calib22, + dac_calib23, dac_calib24, tsif1_sync, dac_calib25, sd_write, + tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, qdss_cti, + blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, uim3, + blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, + blsp_uart11, blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, + blsp_i2c11, cri_trng0, cri_trng1, cri_trng, qdss_stm18, + pri_mi2s, qdss_stm17, blsp_spi4, blsp_uart4, blsp_uim4, + qdss_stm16, qdss_stm15, blsp_i2c4, qdss_stm14, dac_calib26, + spkr_i2s, audio_ref, lpass_slimbus, isense_dbg, tsense_pwm1, + tsense_pwm2, btfm_slimbus, ter_mi2s, qdss_stm22, qdss_stm21, + qdss_stm20, qdss_stm19, gcc_gp1_clk_b, sec_mi2s, blsp_spi5, + blsp_uart5, blsp_uim5, gcc_gp2_clk_b, gcc_gp3_clk_b, blsp_i2c5, + blsp_spi12, blsp_uart12, blsp_uim12, qdss_stm25, qdss_stm31, + blsp_i2c12, qdss_stm30, qdss_stm29, tsif1_clk, qdss_stm28, + tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, qdss_traceclk_b, + tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, sdc4_clk, + qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, + blsp11_uart_rx_b, blsp11_i2c_sda_b, prng_rosc, + blsp11_i2c_scl_b, uim2, uim1, uim_batt, pci_e2, pa_indicator, + adsp_ext, ddr_bist, qdss_tracedata_11, qdss_tracedata_12, + modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, qspi_cs, ssbi2, + ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3 ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1010000 { + compatible = "qcom,msm8996-pinctrl"; + reg = <0x01010000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 150>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-spi1-default-state { + spi-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <12>; + bias-disable; + }; + + cs-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + output-high; + }; + }; + + blsp1-spi1-sleep-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml new file mode 100644 index 000000000..3b098a226 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8998-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8998 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8998 SoC. + +properties: + compatible: + const: qcom,msm8998-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 75 + + gpio-line-names: + maxItems: 150 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8998-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8998-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8998-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, adsp_ext, agera_pll, atest_char, atest_gpsadc0, + atest_gpsadc1, atest_tsens, atest_tsens2, atest_usb1, + atest_usb10, atest_usb11, atest_usb12, atest_usb13, audio_ref, + bimc_dte0, bimc_dte1, blsp10_spi, blsp10_spi_a, blsp10_spi_b, + blsp11_i2c, blsp1_spi, blsp1_spi_a, blsp1_spi_b, blsp2_spi, + blsp9_spi, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, + blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, + blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, blsp_spi2, + blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, + blsp_spi8, blsp_spi9, blsp_spi10, blsp_spi11, blsp_spi12, + blsp_uart1_a, blsp_uart1_b, blsp_uart2_a, blsp_uart2_b, + blsp_uart3_a, blsp_uart3_b, blsp_uart7_a, blsp_uart7_b, + blsp_uart8, blsp_uart8_a, blsp_uart8_b, blsp_uart9_a, + blsp_uart9_b, blsp_uim1_a, blsp_uim1_b, blsp_uim2_a, + blsp_uim2_b, blsp_uim3_a, blsp_uim3_b, blsp_uim7_a, + blsp_uim7_b, blsp_uim8_a, blsp_uim8_b, blsp_uim9_a, + blsp_uim9_b, bt_reset, btfm_slimbus, cam_mclk, cci_async, + cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, + edp_hot, edp_lcd, gcc_gp1_a, gcc_gp1_b, gcc_gp2_a, gcc_gp2_b, + gcc_gp3_a, gcc_gp3_b, hdmi_cec, hdmi_ddc, hdmi_hot, hdmi_rcv, + isense_dbg, jitter_bist, ldo_en, ldo_update, lpass_slimbus, + m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, + mdp_vsync3, mdp_vsync_a, mdp_vsync_b, modem_tsync, mss_lte, + nav_dr, nav_pps, pa_indicator, pci_e0, phase_flag, + pll_bypassnl, pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, + pwr_crypto, pwr_modem, pwr_nav, qdss_cti0_a, qdss_cti0_b, + qdss_cti1_a, qdss_cti1_b, qdss, qlink_enable, qlink_request, + qua_mi2s, sd_card, sd_write, sdc40, sdc41, sdc42, sdc43, + sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ssbi1, ssc_irq, + ter_mi2s, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, tsif0, + tsif1, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, + uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1, + vsense_clkout, vsense_data0, vsense_data1, vsense_mode, + wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1 ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@3400000 { + compatible = "qcom,msm8998-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&tlmm 0 0 150>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-reserved-ranges = <0 4>, <81 4>; + + sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2-cd-state { + pins = "gpio95"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml new file mode 100644 index 000000000..386c31e9c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -0,0 +1,632 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PMIC GPIO block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: + This binding describes the GPIO block(s) found in the 8xxx series of + PMIC's from Qualcomm. + +properties: + compatible: + items: + - enum: + - qcom,pm2250-gpio + - qcom,pm660-gpio + - qcom,pm660l-gpio + - qcom,pm6125-gpio + - qcom,pm6150-gpio + - qcom,pm6150l-gpio + - qcom,pm6350-gpio + - qcom,pm6450-gpio + - qcom,pm7250b-gpio + - qcom,pm7325-gpio + - qcom,pm7550-gpio + - qcom,pm7550ba-gpio + - qcom,pm8005-gpio + - qcom,pm8018-gpio + - qcom,pm8019-gpio + - qcom,pm8038-gpio + - qcom,pm8058-gpio + - qcom,pm8150-gpio + - qcom,pm8150b-gpio + - qcom,pm8150l-gpio + - qcom,pm8226-gpio + - qcom,pm8350-gpio + - qcom,pm8350b-gpio + - qcom,pm8350c-gpio + - qcom,pm8450-gpio + - qcom,pm8550-gpio + - qcom,pm8550b-gpio + - qcom,pm8550ve-gpio + - qcom,pm8550vs-gpio + - qcom,pm8916-gpio + - qcom,pm8917-gpio + - qcom,pm8921-gpio + - qcom,pm8937-gpio + - qcom,pm8941-gpio + - qcom,pm8950-gpio + - qcom,pm8953-gpio + - qcom,pm8994-gpio + - qcom,pm8998-gpio + - qcom,pma8084-gpio + - qcom,pmc8180-gpio + - qcom,pmc8180c-gpio + - qcom,pmc8380-gpio + - qcom,pmcx0102-gpio + - qcom,pmd8028-gpio + - qcom,pmh0101-gpio + - qcom,pmh0104-gpio + - qcom,pmh0110-gpio + - qcom,pmi632-gpio + - qcom,pmi8950-gpio + - qcom,pmi8994-gpio + - qcom,pmi8998-gpio + - qcom,pmih0108-gpio + - qcom,pmiv0104-gpio + - qcom,pmk8350-gpio + - qcom,pmk8550-gpio + - qcom,pmk8850-gpio + - qcom,pmm8155au-gpio + - qcom,pmm8654au-gpio + - qcom,pmp8074-gpio + - qcom,pmr735a-gpio + - qcom,pmr735b-gpio + - qcom,pmr735d-gpio + - qcom,pms405-gpio + - qcom,pmx55-gpio + - qcom,pmx65-gpio + - qcom,pmx75-gpio + - qcom,pmxr2230-gpio + + - enum: + - qcom,spmi-gpio + - qcom,ssbi-gpio + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + gpio-line-names: + minItems: 2 + maxItems: 44 + + gpio-reserved-ranges: + minItems: 1 + # maxItems as half of total number of GPIOs, as there has to be at + # least one usable GPIO between each reserved range. + maxItems: 22 + + '#gpio-cells': + const: 2 + description: + The first cell will be used to define gpio number and the + second denotes the flags for this gpio + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupt-controller + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,pmi8950-gpio + - qcom,pmr735d-gpio + then: + properties: + gpio-line-names: + minItems: 2 + maxItems: 2 + gpio-reserved-ranges: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8005-gpio + - qcom,pm8450-gpio + - qcom,pm8916-gpio + - qcom,pmd8028-gpio + - qcom,pmk8350-gpio + - qcom,pmr735a-gpio + - qcom,pmr735b-gpio + then: + properties: + gpio-line-names: + minItems: 4 + maxItems: 4 + gpio-reserved-ranges: + minItems: 1 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8018-gpio + - qcom,pm8019-gpio + - qcom,pm8550vs-gpio + - qcom,pmk8550-gpio + then: + properties: + gpio-line-names: + minItems: 6 + maxItems: 6 + gpio-reserved-ranges: + minItems: 1 + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm7550ba-gpio + - qcom,pm8226-gpio + - qcom,pm8350b-gpio + - qcom,pm8550ve-gpio + - qcom,pm8937-gpio + - qcom,pm8950-gpio + - qcom,pm8953-gpio + - qcom,pmi632-gpio + - qcom,pmh0104-gpio + - qcom,pmk8850-gpio + then: + properties: + gpio-line-names: + minItems: 8 + maxItems: 8 + gpio-reserved-ranges: + minItems: 1 + maxItems: 4 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm6350-gpio + - qcom,pm6450-gpio + - qcom,pm8350c-gpio + then: + properties: + gpio-line-names: + minItems: 9 + maxItems: 9 + gpio-reserved-ranges: + minItems: 1 + maxItems: 5 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm2250-gpio + - qcom,pm6150-gpio + - qcom,pm7325-gpio + - qcom,pm8150-gpio + - qcom,pm8350-gpio + - qcom,pmc8180-gpio + - qcom,pmc8380-gpio + - qcom,pmi8994-gpio + - qcom,pmiv0104-gpio + - qcom,pmm8155au-gpio + then: + properties: + gpio-line-names: + minItems: 10 + maxItems: 10 + gpio-reserved-ranges: + minItems: 1 + maxItems: 5 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pmx55-gpio + then: + properties: + gpio-line-names: + minItems: 11 + maxItems: 11 + gpio-reserved-ranges: + minItems: 1 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm660l-gpio + - qcom,pm6150l-gpio + - qcom,pm7250b-gpio + - qcom,pm7550-gpio + - qcom,pm8038-gpio + - qcom,pm8150b-gpio + - qcom,pm8150l-gpio + - qcom,pm8550-gpio + - qcom,pm8550b-gpio + - qcom,pmc8180c-gpio + - qcom,pmp8074-gpio + - qcom,pms405-gpio + - qcom,pmxr2230-gpio + then: + properties: + gpio-line-names: + minItems: 12 + maxItems: 12 + gpio-reserved-ranges: + minItems: 1 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm660-gpio + then: + properties: + gpio-line-names: + minItems: 13 + maxItems: 13 + gpio-reserved-ranges: + minItems: 1 + maxItems: 7 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pmcx0102-gpio + - qcom,pmh0110-gpio + - qcom,pmi8998-gpio + then: + properties: + gpio-line-names: + minItems: 14 + maxItems: 14 + gpio-reserved-ranges: + minItems: 1 + maxItems: 7 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pmh0101-gpio + - qcom,pmih0108-gpio + then: + properties: + gpio-line-names: + minItems: 18 + maxItems: 18 + gpio-reserved-ranges: + minItems: 1 + maxItems: 9 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pmx65-gpio + - qcom,pmx75-gpio + then: + properties: + gpio-line-names: + minItems: 16 + maxItems: 16 + gpio-reserved-ranges: + minItems: 1 + maxItems: 8 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8994-gpio + - qcom,pma8084-gpio + then: + properties: + gpio-line-names: + minItems: 22 + maxItems: 22 + gpio-reserved-ranges: + minItems: 1 + maxItems: 11 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8998-gpio + then: + properties: + gpio-line-names: + minItems: 26 + maxItems: 26 + gpio-reserved-ranges: + minItems: 1 + maxItems: 13 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8941-gpio + then: + properties: + gpio-line-names: + minItems: 36 + maxItems: 36 + gpio-reserved-ranges: + minItems: 1 + maxItems: 18 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8917-gpio + then: + properties: + gpio-line-names: + minItems: 38 + maxItems: 38 + gpio-reserved-ranges: + minItems: 1 + maxItems: 19 + + - if: + properties: + compatible: + contains: + enum: + - qcom,pm8058-gpio + - qcom,pm8921-gpio + then: + properties: + gpio-line-names: + minItems: 44 + maxItems: 44 + gpio-reserved-ranges: + minItems: 1 + maxItems: 22 + +patternProperties: + '-state$': + oneOf: + - $ref: '#/$defs/qcom-pmic-gpio-state' + - patternProperties: + '(pinconf|-pins)$': + $ref: '#/$defs/qcom-pmic-gpio-state' + additionalProperties: false + + '-hog(-[0-9]+)?$': + type: object + required: + - gpio-hog + +$defs: + qcom-pmic-gpio-state: + type: object + allOf: + - $ref: pinmux-node.yaml + - $ref: pincfg-node.yaml + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. Valid pins are + - gpio1-gpio9 for pm6125 + - gpio1-gpio10 for pm6150 + - gpio1-gpio12 for pm6150l + - gpio1-gpio9 for pm6350 + - gpio1-gpio9 for pm6450 + - gpio1-gpio12 for pm7250b + - gpio1-gpio10 for pm7325 + - gpio1-gpio8 for pm7550ba + - gpio1-gpio4 for pm8005 + - gpio1-gpio6 for pm8018 + - gpio1-gpio12 for pm8038 + - gpio1-gpio40 for pm8058 + - gpio1-gpio10 for pm8150 (holes on gpio2, gpio5, + gpio7 and gpio8) + - gpio1-gpio12 for pm8150b (holes on gpio3, gpio4 + and gpio7) + - gpio1-gpio12 for pm8150l (hole on gpio7) + - gpio1-gpio4 for pm8916 + - gpio1-gpio10 for pm8350 + - gpio1-gpio8 for pm8350b + - gpio1-gpio9 for pm8350c + - gpio1-gpio4 for pm8450 + - gpio1-gpio12 for pm8550 + - gpio1-gpio12 for pm8550b + - gpio1-gpio8 for pm8550ve + - gpio1-gpio6 for pm8550vs + - gpio1-gpio38 for pm8917 + - gpio1-gpio44 for pm8921 + - gpio1-gpio8 for pm8937 (hole on gpio3, gpio4 and gpio6) + - gpio1-gpio36 for pm8941 + - gpio1-gpio8 for pm8950 (hole on gpio3) + - gpio1-gpio8 for pm8953 (hole on gpio3 and gpio6) + - gpio1-gpio22 for pm8994 + - gpio1-gpio26 for pm8998 + - gpio1-gpio22 for pma8084 + - gpio1-gpio14 for pmcx0102 + - gpio1-gpio4 for pmd8028 + - gpio1-gpio18 for pmh0101 + - gpio1-gpio8 for pmh0104 + - gpio1-gpio14 for pmh0110 + - gpio1-gpio8 for pmi632 + - gpio1-gpio2 for pmi8950 + - gpio1-gpio10 for pmi8994 + - gpio1-gpio18 for pmih0108 + - gpio1-gpio4 for pmk8350 + - gpio1-gpio6 for pmk8550 + - gpio1-gpio8 for pmk8850 + - gpio1-gpio10 for pmm8155au + - gpio1-gpio12 for pmm8654au + - gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12) + - gpio1-gpio4 for pmr735a + - gpio1-gpio4 for pmr735b + - gpio1-gpio2 for pmr735d + - gpio1-gpio12 for pms405 (holes on gpio1, gpio9 + and gpio10) + - gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10 + and gpio11) + - gpio1-gpio16 for pmx65 + - gpio1-gpio16 for pmx75 + - gpio1-gpio12 for pmxr2230 + + items: + pattern: '^gpio([0-9]+)$' + + function: + items: + - enum: + - normal + - paired + - func1 + - func2 + - dtest1 + - dtest2 + - dtest3 + - dtest4 + - func3 # supported by LV/MV GPIO subtypes + - func4 # supported by LV/MV GPIO subtypes + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + qcom,pull-up-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Specifies the strength to use for pull up, if selected. + Valid values are defined in + <dt-bindings/pinctrl/qcom,pmic-gpio.h> + If this property is omitted 30uA strength will be used + if pull up is selected + enum: [0, 1, 2, 3] + + bias-high-impedance: true + input-enable: true + input-disable: true + output-high: true + output-low: true + output-enable: true + output-disable: true + power-source: true + + qcom,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the drive strength for the specified pins + Valid drive strength values are defined in + <dt-bindings/pinctrl/qcom,pmic-gpio.h> + enum: [0, 1, 2, 3] + + drive-push-pull: true + drive-open-drain: true + drive-open-source: true + + qcom,analog-pass: + $ref: /schemas/types.yaml#/definitions/flag + description: + The specified pins are configured in + analog-pass-through mode. + + qcom,atest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects ATEST rail to route to GPIO when it's + configured in analog-pass-through mode. + enum: [1, 2, 3, 4] + + qcom,dtest-buffer: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects DTEST rail to route to GPIO when it's + configured as digital input. + enum: [1, 2, 3, 4] + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + + pm8921_gpio: gpio@150 { + compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio"; + reg = <0x150 0x160>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + gpio-ranges = <&pm8921_gpio 0 0 44>; + #gpio-cells = <2>; + + pm8921_gpio_keys: gpio-keys-state { + volume-keys-pins { + pins = "gpio20", "gpio21"; + function = "normal"; + + input-enable; + bias-pull-up; + drive-push-pull; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>; + power-source = <PM8921_GPIO_S4>; + }; + }; + + otg-hog { + gpio-hog; + gpios = <35 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "otg-gpio"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml new file mode 100644 index 000000000..daf4c1c03 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.yaml @@ -0,0 +1,200 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,pmic-mpp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PMIC Multi-Purpose Pin (MPP) block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: + This binding describes the MPP block(s) found in the 8xxx series of + PMIC's from Qualcomm. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,pm8019-mpp + - qcom,pm8226-mpp + - qcom,pm8841-mpp + - qcom,pm8916-mpp + - qcom,pm8937-mpp + - qcom,pm8941-mpp + - qcom,pm8950-mpp + - qcom,pmi8950-mpp + - qcom,pm8994-mpp + - qcom,pma8084-mpp + - qcom,pmi8994-mpp + - const: qcom,spmi-mpp + - items: + - enum: + - qcom,pm8018-mpp + - qcom,pm8038-mpp + - qcom,pm8058-mpp + - qcom,pm8821-mpp + - qcom,pm8901-mpp + - qcom,pm8917-mpp + - qcom,pm8921-mpp + - const: qcom,ssbi-mpp + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + gpio-line-names: true + + gpio-ranges: + maxItems: 1 + + '#gpio-cells': + const: 2 + description: + The first cell will be used to define gpio number and the + second denotes the flags for this gpio + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupt-controller + +patternProperties: + '-state$': + oneOf: + - $ref: '#/$defs/qcom-pmic-mpp-state' + - patternProperties: + '-pins$': + $ref: '#/$defs/qcom-pmic-mpp-state' + additionalProperties: false + +$defs: + qcom-pmic-mpp-state: + type: object + allOf: + - $ref: pinmux-node.yaml + - $ref: pincfg-node.yaml + properties: + pins: + description: + List of gpio pins affected by the properties specified in + this subnode. Valid pins are + - mpp1-mpp4 for pm8841 + - mpp1-mpp4 for pm8916 + - mpp1-mpp4 for pm8937 + - mpp1-mpp8 for pm8941 + - mpp1-mpp4 for pm8950 + - mpp1-mpp4 for pmi8950 + - mpp1-mpp4 for pma8084 + + items: + pattern: '^mpp([0-9]+)$' + + function: + items: + - enum: + - digital + - analog + - sink + + bias-disable: true + bias-pull-up: true + bias-high-impedance: true + input-enable: true + output-high: true + output-low: true + power-source: true + + qcom,analog-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog output. Valued values are defined in + <dt-binding/pinctrl/qcom,pmic-mpp.h> PMIC_MPP_AOUT_LVL_* + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,atest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects ATEST rail to route to GPIO when it's + configured in analog-pass-through mode. + enum: [1, 2, 3, 4] + + qcom,dtest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects DTEST rail to route to GPIO when it's + configured as digital input. + enum: [1, 2, 3, 4] + + qcom,amux-route: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects the source for analog input. Valid values are defined in + <dt-bindings/pinctrl/qcom,pmic-mpp.h> PMIC_MPP_AMUX_ROUTE_CH5, + PMIC_MPP_AMUX_ROUTE_CH6... + enum: [0, 1, 2, 3, 4, 5, 6, 7] + + qcom,paired: + type: boolean + description: + Indicates that the pin should be operating in paired mode. + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/qcom,pmic-mpp.h> + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + pm8841_mpp: mpps@a000 { + compatible = "qcom,pm8841-mpp", "qcom,spmi-mpp"; + reg = <0xa000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pm8841_mpp 0 0 4>; + gpio-line-names = "VDD_PX_BIAS", "WLAN_LED_CTRL", + "BT_LED_CTRL", "GPIO-F"; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pm8841_default>; + + mpp1-state { + pins = "mpp1"; + function = "digital"; + input-enable; + power-source = <PM8841_MPP_S3>; + }; + + default-state { + gpio-pins { + pins = "mpp1", "mpp2", "mpp3", "mpp4"; + function = "digital"; + input-enable; + power-source = <PM8841_MPP_S3>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml new file mode 100644 index 000000000..e123beb33 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcm2290-tlmm.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcm2290-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCM2290 TLMM block + +maintainers: + - Shawn Guo <shawn.guo@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm QCM2290 SoC. + +properties: + compatible: + const: qcom,qcm2290-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcm2290-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcm2290-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcm2290-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-6])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, char_exec, + cri_trng, cri_trng0, cri_trng1, dac_calib, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, + gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, + jitter_bist, mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, + mpm_pwr, mss_lte, m_voc, nav_gpio, pa_indicator, pbs0, pbs1, + pbs2, pbs3, pbs4, pbs5, pbs6, pbs7, pbs8, pbs9, pbs10, pbs11, + pbs12, pbs13, pbs14, pbs15, pbs_out, phase_flag, pll_bist, + pll_bypassnl, pll_reset, prng_rosc, pwm_0, pwm_1, pwm_2, pwm_3, + pwm_4, pwm_5, pwm_6, pwm_7, pwm_8, pwm_9, qdss_cti, qdss_gpio, + qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, sdc2_tb, sd_write, + ssbi_wtr1, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, + uim2_data, uim2_present, uim2_reset, usb_phy, vfr_1, + vsense_trigger, wlan1_adc0, wlan1_adc1 ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@500000 { + compatible = "qcom,qcm2290-tlmm"; + reg = <0x500000 0x300000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 127>; + + sdc2_on_state: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml new file mode 100644 index 000000000..91b8dcec3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs404-pinctrl.yaml @@ -0,0 +1,161 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs404-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS404 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm QCS404 SoC. + +properties: + compatible: + const: qcom,qcs404-pinctrl + + reg: + maxItems: 3 + + reg-names: + items: + - const: south + - const: north + - const: east + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 60 + + gpio-line-names: + maxItems: 120 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs404-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs404-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcs404-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, adsp_ext, atest_char, atest_char0, atest_char1, + atest_char2, atest_char3, aud_cdc, audio_ts, bimc_dte0, + bimc_dte1, blsp_i2c0, blsp_i2c1, blsp_i2c3, blsp_i2c4, + blsp_i2c5, blsp_i2c_scl_a2, blsp_i2c_scl_b2, blsp_i2c_sda_a2, + blsp_i2c_sda_b2, blsp_spi0, blsp_spi2, blsp_spi3, blsp_spi4, + blsp_spi5, blsp_spi_clk_a1, blsp_spi_clk_b1, blsp_spi_cs_n_a1, + blsp_spi_cs_n_b1, blsp_spi_miso_a1, blsp_spi_miso_b1, + blsp_spi_mosi_a1, blsp_spi_mosi_b1, blsp_uart0, blsp_uart1, + blsp_uart2, blsp_uart3, blsp_uart5, blsp_uart_rx_a2, + blsp_uart_rx_b2, blsp_uart_tx_a2, blsp_uart_tx_b2, cri_trng, + cri_trng0, cri_trng1, dbg_out, dsd_clk_a, dsd_clk_b, ebi2_a, + ebi2_lcd, ebi_cdc, ebi_ch0, ext_lpass, ext_mclk0, ext_mclk1_a, + ext_mclk1_b, gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, + gcc_gp2_clk_b, gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, + gcc_tlmm, hdmi_ddc, hdmi_dtest, hdmi_lbk0, hdmi_lbk1, + hdmi_lbk2, hdmi_lbk3, hdmi_lbk4, hdmi_lbk5, hdmi_lbk6, + hdmi_lbk7, hdmi_lbk8, hdmi_lbk9, hdmi_pixel, hdmi_rcv, hdmi_tx, + i2s_1, i2s_2, i2s_3_data0_a, i2s_3_data0_b, i2s_3_data1_a, + i2s_3_data1_b, i2s_3_data2_a, i2s_3_data2_b, i2s_3_data3_a, + i2s_3_data3_b, i2s_3_sck_a, i2s_3_sck_b, i2s_3_ws_a, + i2s_3_ws_b, i2s_4, ir_in, ldo_en, ldo_update, mclk_in1, + mclk_in2, m_voc, nfc_dwl, nfc_irq, pcie_clk, pll_bist, + prng_rosc, pwm_led1, pwm_led10, pwm_led11, pwm_led12, + pwm_led13, pwm_led14, pwm_led15, pwm_led16, pwm_led17, + pwm_led18, pwm_led19, pwm_led2, pwm_led20, pwm_led21, + pwm_led22, pwm_led23, pwm_led24, pwm_led3, pwm_led4, pwm_led5, + pwm_led6, pwm_led7, pwm_led8, pwm_led9, qdss_cti_trig_in_a0, + qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, rgb_clk, rgb_data0, + rgb_data1, rgb_data2, rgb_data3, rgb_data4, rgb_data5, + rgb_data6, rgb_data7, rgb_data_b0, rgb_data_b1, rgb_data_b2, + rgb_data_b3, rgb_data_b4, rgb_data_b5, rgb_data_b6, + rgb_data_b7, rgb_de, rgb_hsync, rgb_mdp, rgb_vsync, rgmi_dll1, + rgmi_dll2, rgmii_ck, rgmii_ctl, rgmii_int, rgmii_mdc, + rgmii_mdio, rgmii_rx, rgmii_tx, rgmii_wol, sd_write, + spdifrx_opt, spi_lcd, spkr_dac0, wlan1_adc0, wlan1_adc1, + wlan2_adc0, wlan2_adc1, wsa_en ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@1000000 { + compatible = "qcom,qcs404-pinctrl"; + reg = <0x01000000 0x200000>, + <0x01300000 0x200000>, + <0x07b00000 0x200000>; + reg-names = "south", "north", "east"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&tlmm 0 0 120>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-i2c1-default-state { + pins = "gpio24", "gpio25"; + function = "blsp_i2c1"; + }; + + blsp1-i2c2-default-state { + sda-pins { + pins = "gpio19"; + function = "blsp_i2c_sda_a2"; + }; + + scl-pins { + pins = "gpio20"; + function = "blsp_i2c_scl_a2"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml new file mode 100644 index 000000000..2791e578c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs615-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS615 TLMM block + +maintainers: + - Lijuan Gao <quic_lijuang@quicinc.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm QCS615 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qcs615-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: east + - const: west + - const: south + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 62 + + gpio-line-names: + maxItems: 123 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs615-tlmm-state" + - type: object + patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs615-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcs615-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, + sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens, + atest_usb, cam_mclk, cci_async, cci_i2c, cci_timer, copy_gp, + copy_phase, cri_trng, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot, + edp_hot, edp_lcd, emac_gcc, emac_phy_intr, forced_usb, gcc_gp, + gp_pdm, gps_tx, hs0_mi2s, hs1_mi2s, jitter_bist, ldo_en, + ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4_out, + mdp_vsync5_out, mi2s_1, mss_lte, nav_pps_in, nav_pps_out, + pa_indicator_or, pcie_clk_req, pcie_ep_rst, phase_flag, pll_bist, + pll_bypassnl, pll_reset_n, prng_rosc, qdss_cti, qdss_gpio, + qlink_enable, qlink_request, qspi, qup0, qup1, rgmii, + sd_write_protect, sp_cmu, ter_mi2s, tgu_ch, uim1, uim2, usb0_hs, + usb1_hs, usb_phy_ps, vfr_1, vsense_trigger_mirnat, wlan, wsa_clk, + wsa_data ] + + required: + - pins + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@3000000 { + compatible = "qcom,qcs615-tlmm"; + reg = <0x03100000 0x300000>, + <0x03500000 0x300000>, + <0x03c00000 0x300000>; + reg-names = "east", "west", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&tlmm 0 0 124>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + qup3-uart2-state { + pins ="gpio16", "gpio17"; + function = "qup0"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml new file mode 100644 index 000000000..489b41dcc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qcs8300-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QCS8300 TLMM block + +maintainers: + - Jingyi Wang <quic_jingyw@quicinc.com> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm QCS8300 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qcs8300-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 67 + + gpio-line-names: + maxItems: 133 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qcs8300-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qcs8300-tlmm-state" + additionalProperties: false + +$defs: + qcom-qcs8300-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$" + - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest_char, atest_usb2, audio_ref, cam_mclk, + cci_async, cci_i2c_scl, cci_i2c_sda, cci_timer, cri_trng, + dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, + edp0_hot, edp0_lcd, edp1_lcd, egpio, emac0_mcg0, emac0_mcg1, + emac0_mcg2, emac0_mcg3, emac0_mdc, emac0_mdio, emac0_ptp_aux, + emac0_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, gcc_gp5, + gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, jitter_bist, + mdp0_vsync0, mdp0_vsync1, mdp0_vsync3, mdp0_vsync6, mdp0_vsync7, + mdp_vsync, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, + mi2s_mclk1, pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, + pll_clk, prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, + qdss_cti, qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, + qup0_se4, qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, + qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, + qup2_se0, sailss_emac0, sailss_ospi, sail_top, sgmii_phy, + tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, tsense_pwm3, tsense_pwm4, usb2phy_ac, + vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f100000 { + compatible = "qcom,qcs8300-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 134>; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart7-state { + pins = "gpio43", "gpio44"; + function = "qup0_se7"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml new file mode 100644 index 000000000..88afeae53 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,qdu1000-tlmm.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block + +maintainers: + - Melody Olvera <quic_molvera@quicinc.com> + +description: | + Top Level Mode Multiplexer pin controller found in the QDU1000 and + QRU1000 SoCs. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,qdu1000-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 76 + + gpio-line-names: + maxItems: 151 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-qdu1000-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-qdu1000-tlmm-state" + additionalProperties: false + +$defs: + qcom-qdu1000-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng, + dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, + ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in, + intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist, + pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, + qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, + qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, + qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable, + qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request, + qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss, + qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs, + qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04, + qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14, + qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert, + smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2, + usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1, + vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@f000000 { + compatible = "qcom,qdu1000-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; + + uart0-default-state { + pins = "gpio6", "gpio7", "gpio8", "gpio9"; + function = "qup00"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml new file mode 100644 index 000000000..7a156b9bf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sa8775p-tlmm.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA8775P TLMM block + +maintainers: + - Bartosz Golaszewski <bartosz.golaszewski@linaro.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,sa8255p-tlmm + - const: qcom,sa8775p-tlmm + - items: + - const: qcom,sa8775p-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 74 + + gpio-line-names: + maxItems: 148 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sa8775p-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sa8775p-tlmm-state" + additionalProperties: false + +$defs: + qcom-sa8775p-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot, + edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, + edp3_lcd, egpio, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, + emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0, + emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, + emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, + gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c, + jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3, + mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, + mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, + mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, + mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, + mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1, + pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, + qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, + qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0, + sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1, + tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2, + tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@f000000 { + compatible = "qcom,sa8775p-tlmm"; + reg = <0xf000000 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 148>; + + qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml new file mode 100644 index 000000000..b388380b1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SAR2130P TLMM block + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sar2130p-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 78 + + gpio-line-names: + maxItems: 156 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sar2130p-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sar2130p-tlmm-state" + additionalProperties: false + +$defs: + qcom-sar2130p-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aoss_cti, atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02, + atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp0_hot, ext_mclk0, ext_mclk1, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, host2wlan_sol, i2s0_data0, + i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync, + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, pcie0_clkreqn, + pcie1_clkreqn, phase_flag0, phase_flag1, phase_flag10, + phase_flag11, phase_flag12, phase_flag13, phase_flag14, + phase_flag15, phase_flag16, phase_flag17, phase_flag18, + phase_flag19, phase_flag2, phase_flag20, phase_flag21, + phase_flag22, phase_flag23, phase_flag24, phase_flag25, + phase_flag26, phase_flag27, phase_flag28, phase_flag29, + phase_flag3, phase_flag30, phase_flag31, phase_flag4, + phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist, pll_clk, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs0, qspi_cs1, qup0, + qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup10, + qup11, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, usb0_phy, vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sar2130p-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 156>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml new file mode 100644 index 000000000..ec0bf4fdf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7180 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC. + +properties: + compatible: + const: qcom,sc7180-pinctrl + + reg: + maxItems: 3 + + reg-names: + items: + - const: west + - const: north + - const: south + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 60 + + gpio-line-names: + maxItems: 119 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sc7180-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sc7180-tlmm-state" + additionalProperties: false + +$defs: + qcom-sc7180-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, + sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, atest_tsens, + atest_tsens2, atest_usb1, atest_usb10, atest_usb11, + atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, + atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk, + cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, + cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1, + gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx, + jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync, + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, + mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST, + pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti, + qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data, + qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c, + qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12, + qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb, + sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1, + _V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0, + wlan1_adc1, wlan2_adc0, wlan2_adc1 ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@3500000 { + compatible = "qcom,sc7180-pinctrl"; + reg = <0x03500000 0x300000>, + <0x03900000 0x300000>, + <0x03d00000 0x300000>; + reg-names = "west", "north", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 120>; + wakeup-parent = <&pdc>; + + dp_hot_plug_det: dp-hot-plug-det-state { + pins = "gpio117"; + function = "dp_hot"; + }; + + qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { + spi-pins { + pins = "gpio53", "gpio54", "gpio55"; + function = "qup15"; + }; + + cs-pins { + pins = "gpio56"; + function = "gpio"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..bc7b8dda8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 SoC LPASS LPI TLMM + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SC7280 SoC. + +properties: + compatible: + const: qcom,sc7280-lpass-lpi-pinctrl + + reg: + maxItems: 2 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sc7280-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sc7280-lpass-state" + additionalProperties: false + +$defs: + qcom-sc7280-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|1[0-4])$" + minItems: 1 + maxItems: 15 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, + dmic3_data, i2s2_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +required: + - compatible + - reg + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sc7280-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + dmic01-state { + dmic01-clk-pins { + pins = "gpio6"; + function = "dmic1_clk"; + }; + + dmic01-clk-sleep-pins { + pins = "gpio6"; + function = "dmic1_clk"; + }; + }; + + tx-swr-data-sleep-state { + pins = "gpio1", "gpio2", "gpio14"; + function = "swr_tx_data"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml new file mode 100644 index 000000000..5329fe2a4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC7280 TLMM block + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SC7280 SoC. + +properties: + compatible: + const: qcom,sc7280-pinctrl + + reg: + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 88 + + gpio-line-names: + maxItems: 175 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sc7280-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sc7280-tlmm-state" + additionalProperties: false + +$defs: + qcom-sc7280-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, + sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_usb0, atest_usb00, atest_usb01, + atest_usb02, atest_usb03, atest_usb1, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, audio_ref, + cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1, + cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0, + cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot, + dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus, + mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, + mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck, + mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0, + mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2, + mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, + mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2, + pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag, + pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc, + qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss, + qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs, + qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07, + qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, + sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write, + sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1, + tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, + usb_phy, vfr_0, vfr_1, vsense_trigger ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f000000 { + compatible = "qcom,sc7280-pinctrl"; + reg = <0xf000000 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 175>; + wakeup-parent = <&pdc>; + + qup_uart5_default: qup-uart5-state { + pins = "gpio46", "gpio47"; + function = "qup13"; + drive-strength = <2>; + bias-disable; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml new file mode 100644 index 000000000..c122bb849 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC8180X TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SC8180X SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sc8180x-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: west + - const: east + - const: south + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sc8180x-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sc8180x-tlmm-state" + additionalProperties: false + +$defs: + qcom-sc8180x-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-8][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens, + atest_tsens2, atest_usb0, atest_usb1, atest_usb2, atest_usb3, + atest_usb4, audio_ref, btfm_slimbus, cam_mclk, cci_async, + cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, cci_timer5, cci_timer6, cci_timer7, cci_timer8, + cci_timer9, cri_trng, dbg_out, ddr_bist, ddr_pxi, debug_hot, + dp_hot, edp_hot, edp_lcd, emac_phy, emac_pps, gcc_gp1, gcc_gp2, + gcc_gp3, gcc_gp4, gcc_gp5, gpio, gps, grfc, hs1_mi2s, hs2_mi2s, + hs3_mi2s, jitter_bist, lpass_slimbus, m_voc, mdp_vsync, + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, + mdp_vsync5, mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, + pci_e2, pci_e3, phase_flag, pll_bist, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss_gpio, qlink, + qspi0, qspi0_clk, qspi0_cs, qspi1, qspi1_clk, qspi1_cs, + qua_mi2s, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, + qup18, qup19, qup_l4, qup_l5, qup_l6, rgmii, sd_write, sdc4, + sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu, + tsense_pwm1, tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, + usb0_phy, usb1_phy, usb2phy_ac, vfr_1, vsense_trigger, + wlan1_adc, wlan2_adc, wmss_reset ] + + required: + - pins + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@3100000 { + compatible = "qcom,sc8180x-tlmm"; + reg = <0x03100000 0x300000>, + <0x03500000 0x700000>, + <0x03d00000 0x300000>; + reg-names = "west", "east", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 190>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio4"; + function = "qup6"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio5"; + function = "qup6"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..240e6d45c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml @@ -0,0 +1,114 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8280XP SoC LPASS LPI TLMM + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SC8280XP SoC. + +properties: + compatible: + const: qcom,sc8280xp-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sc8280xp-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sc8280xp-lpass-state" + additionalProperties: false + +$defs: + qcom-sc8280xp-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-8])$" + + function: + enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, + dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk, + dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data, + qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws, + i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, + wsa2_swr_data, i2s2_data, i2s3_clk, i2s3_ws, i2s3_data, + ext_mclk1_c, ext_mclk1_b, ext_mclk1_a ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + pinctrl@33c0000 { + compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 19>; + + dmic01-state { + dmic01-clk-pins { + pins = "gpio16"; + function = "dmic1_clk"; + }; + + dmic01-clk-sleep-pins { + pins = "gpio16"; + function = "dmic1_clk"; + }; + }; + + tx-swr-data-sleep-state { + pins = "gpio0", "gpio1"; + function = "swr_tx_data"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml new file mode 100644 index 000000000..ed344deaf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-tlmm.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC8280XP TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm SC8280XP SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sc8280xp-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + additionalProperties: false + +$defs: + qcom-sc8280xp-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, + cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, + ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd, + edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1, + emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0, + emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3, + emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, + gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c, + jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1, + mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5, + mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0, + mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, + mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, + mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0, + mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1, + mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq, + pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq, + phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk, + qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, + qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1, + sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig, + tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp, + usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac, + vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sc8280xp-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 230>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio4"; + function = "qup14"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio5"; + function = "qup14"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml new file mode 100644 index 000000000..80627a1ad --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm630-pinctrl.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm630-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM630 and SDM660 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SDM630 and SDM660 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + enum: + - qcom,sdm630-pinctrl + - qcom,sdm660-pinctrl + + reg: + maxItems: 3 + + reg-names: + items: + - const: south + - const: center + - const: north + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 57 + + gpio-line-names: + maxItems: 114 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm630-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm630-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdm630-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-3])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, + atest_char2, atest_char3, atest_gpsadc0, atest_gpsadc1, + atest_tsens, atest_tsens2, atest_usb1, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, + atest_usb21, atest_usb22, atest_usb23, audio_ref, bimc_dte0, + bimc_dte1, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, + blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8_a, blsp_i2c8_b, + blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi3_cs1, blsp_spi3_cs2, + blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8_a, + blsp_spi8_b, blsp_spi8_cs1, blsp_spi8_cs2, blsp_uart1, + blsp_uart2, blsp_uart5, blsp_uart6_a, blsp_uart6_b, blsp_uim1, + blsp_uim2, blsp_uim5, blsp_uim6, cam_mclk, cci_async, cci_i2c, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, gcc_gp1, + gcc_gp2, gcc_gp3, gpio, gps_tx_a, gps_tx_b, gps_tx_c, + isense_dbg, jitter_bist, ldo_en, ldo_update, m_voc, mdp_vsync, + mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, mss_lte, + nav_pps_a, nav_pps_b, nav_pps_c, pa_indicator, phase_flag0, + phase_flag1, phase_flag10, phase_flag11, phase_flag12, + phase_flag13, phase_flag14, phase_flag15, phase_flag16, + phase_flag17, phase_flag18, phase_flag19, phase_flag2, + phase_flag20, phase_flag21, phase_flag22, phase_flag23, + phase_flag24, phase_flag25, phase_flag26, phase_flag27, + phase_flag28, phase_flag29, phase_flag3, phase_flag30, + phase_flag31, phase_flag4, phase_flag5, phase_flag6, + phase_flag7, phase_flag8, phase_flag9, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, pwr_crypto, pwr_modem, + pwr_nav, qdss_cti0_a, qdss_cti0_b, qdss_cti1_a, qdss_cti1_b, + qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, + qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, qdss_gpio2, + qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, qdss_gpio7, + qdss_gpio8, qdss_gpio9, qlink_enable, qlink_request, qspi_clk, + qspi_cs, qspi_data0, qspi_data1, qspi_data2, qspi_data3, + qspi_resetn, sec_mi2s, sndwire_clk, sndwire_data, sp_cmu, + ssc_irq, tgu_ch0, tgu_ch1, tsense_pwm1, tsense_pwm2, uim1_clk, + uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, uim_batt, vfr_1, vsense_clkout, + vsense_data0, vsense_data1, vsense_mode, wlan1_adc0, + wlan1_adc1, wlan2_adc0, wlan2_adc1 ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@3100000 { + compatible = "qcom,sdm630-pinctrl"; + reg = <0x03100000 0x400000>, + <0x03500000 0x400000>, + <0x03900000 0x400000>; + reg-names = "south", "center", "north"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 114>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart1-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + blsp2_uart1_default: blsp2-uart1-active-state { + tx-rts-pins { + pins = "gpio16", "gpio19"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio17"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-pull-up; + }; + + cts-pins { + pins = "gpio18"; + function = "blsp_uart5"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..409e5a4d4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660 SoC LPASS LPI TLMM + +maintainers: + - Nickolay Goppen <setotau@mainlining.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC. + +properties: + compatible: + const: qcom,sdm660-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm660-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm660-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm660-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-2][0-9]|3[0-1])$" + + function: + enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, + mclk0, pdm_tx, pdm_clk, pdm_rx, pdm_sync ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@15070000 { + compatible = "qcom,sdm660-lpass-lpi-pinctrl"; + reg = <0x15070000 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_pdm_default: cdc-pdm-default-state { + clk-pins { + pins = "gpio18"; + function = "pdm_clk"; + drive-strength = <8>; + output-high; + }; + + sync-pins{ + pins = "gpio19"; + function = "pdm_sync"; + drive-strength = <4>; + output-high; + }; + + tx-pins { + pins = "gpio20"; + function = "pdm_tx"; + drive-strength = <8>; + }; + + rx-pins { + pins = "gpio21", "gpio23", "gpio25"; + function = "pdm_rx"; + drive-strength = <4>; + output-high; + }; + }; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <8>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..c76ad70e6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 SoC LPASS LPI TLMM + +maintainers: + - Richard Acayan <mailingradian@gmail.com> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC. + +properties: + compatible: + const: qcom,sdm670-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm670-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm670-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm670-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-9]|3[0-1])$" + + function: + enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, + i2s1_clk, i2s_data, i2s_ws, lpi_cdc_rst, mclk0, pdm_rx, + pdm_sync, pdm_tx, slimbus_clk ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@62b40000 { + compatible = "qcom,sdm670-lpass-lpi-pinctrl"; + reg = <0x62b40000 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml new file mode 100644 index 000000000..b56e717aa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm670-tlmm.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDM670 TLMM block + +maintainers: + - Richard Acayan <mailingradian@gmail.com> + +description: | + The Top Level Mode Multiplexer (TLMM) block found in the SDM670 platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sdm670-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 75 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm670-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm670-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdm670-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - enum: [ ufs_reset, sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, + atest_usb11, atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, + atest_usb22, atest_usb23, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, ldo_update, + lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, + mss_lte, nav_pps, pa_indicator, pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, + pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, qdss, qlink_enable, + qlink_request, qua_mi2s, qup0, qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, + qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sdc4_clk, + sdc4_cmd, sdc4_data, sd_write, sec_mi2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, + tgu_ch3, tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, + tsif2_data, tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1, + vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data, ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@3400000 { + compatible = "qcom,sdm670-tlmm"; + reg = <0x03400000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + + qup-i2c9-state { + pins = "gpio6", "gpio7"; + function = "qup9"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml new file mode 100644 index 000000000..4fcac2e55 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm845-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM845 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SDM845 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sdm845-pinctrl + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 75 + + gpio-line-names: + maxItems: 150 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm845-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm845-tlmm-state" + additionalProperties: false + + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + +$defs: + qcom-sdm845-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, agera_pll, atest_char, atest_tsens, atest_tsens2, + atest_usb1, atest_usb10, atest_usb11, atest_usb12, atest_usb13, + atest_usb2, atest_usb20, atest_usb21, atest_usb22, atest_usb23, + audio_ref, btfm_slimbus, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, + gcc_gp2, gcc_gp3, gpio, jitter_bist, ldo_en, ldo_update, + lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, + mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, pci_e0, + pci_e1, phase_flag, pll_bist, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable, + qlink_request, qspi_clk, qspi_cs, qspi_data, qua_mi2s, qup0, + qup1, qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, + qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, + sdc4_clk, sdc4_cmd, sdc4_data, sd_write, sec_mi2s, sp_cmu, + spkr_i2s, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, + tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en, + tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en, + tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, + uim_batt, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, + wlan1_adc1, wlan2_adc0, wlan2_adc1] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@3400000 { + compatible = "qcom,sdm845-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc_intc>; + + ap-suspend-l-hog { + gpio-hog; + gpios = <126 GPIO_ACTIVE_LOW>; + output-low; + }; + + cci0-default-state { + pins = "gpio17", "gpio18"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; + }; + + cam0-default-state { + rst-pins { + pins = "gpio9"; + function = "gpio"; + + drive-strength = <16>; + bias-disable; + }; + + mclk0-pins { + pins = "gpio13"; + function = "cam_mclk"; + + drive-strength = <16>; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml new file mode 100644 index 000000000..edbcff92b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx55-pinctrl.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx55-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX55 TLMM block + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SDX55 SoC. + +properties: + compatible: + const: qcom,sdx55-pinctrl + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdx55-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdx55-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdx55-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ adsp_ext, atest, audio_ref, bimc_dte0, bimc_dte1, blsp_i2c1, + blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_spi1, blsp_spi2, + blsp_spi3, blsp_spi4, blsp_uart1, blsp_uart2, blsp_uart3, + blsp_uart4, char_exec, coex_uart, coex_uart2, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ebi0_wrcdc, ebi2_a, ebi2_lcd, emac_gcc0, emac_gcc1, + emac_pps0, emac_pps1, ext_dbg, gcc_gp1, gcc_gp2, gcc_gp3, + gcc_plltest, gpio, i2s_mclk, jitter_bist, ldo_en, ldo_update, + mgpi_clk, m_voc, native_char, native_char0, native_char1, + native_char2, native_char3, native_tsens, native_tsense, + nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref, + pll_test, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, + qdss_gpio0, qdss_gpio1, qdss_gpio2, qdss_gpio3, qdss_gpio4, + qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, + qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, + qdss_gpio14, qdss_gpio15, qdss_stm0, qdss_stm1, qdss_stm2, + qdss_stm3, qdss_stm4, qdss_stm5, qdss_stm6, qdss_stm7, + qdss_stm8, qdss_stm9, qdss_stm10, qdss_stm11, qdss_stm12, + qdss_stm13, qdss_stm14, qdss_stm15, qdss_stm16, qdss_stm17, + qdss_stm18, qdss_stm19, qdss_stm20, qdss_stm21, qdss_stm22, + qdss_stm23, qdss_stm24, qdss_stm25, qdss_stm26, qdss_stm27, + qdss_stm28, qdss_stm29, qdss_stm30, qdss_stm31, qlink0_en, + qlink0_req, qlink0_wmss, qlink1_en, qlink1_req, qlink1_wmss, + spmi_coex, sec_mi2s, spmi_vgi, tgu_ch0, uim1_clk, uim1_data, + uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, + uim2_reset, usb2phy_ac, vsense_trigger ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@1f00000 { + compatible = "qcom,sdx55-pinctrl"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 108>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + + serial-state { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + drive-strength = <8>; + bias-disable; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml new file mode 100644 index 000000000..a31b638c4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-tlmm.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX65 TLMM block + +maintainers: + - Vamsi krishna Lanka <quic_vamslank@quicinc.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SDX65 SoC. + +properties: + compatible: + const: qcom,sdx65-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdx65-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdx65-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdx65-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$" + - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ] + minItems: 1 + maxItems: 150 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, pcie_clkreq, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx65-tlmm"; + reg = <0x03000000 0xdc2000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 109>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio4"; + function = "blsp_uart1"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio5"; + function = "blsp_uart1"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx75-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx75-tlmm.yaml new file mode 100644 index 000000000..cb1d978d0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx75-tlmm.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SDX75 TLMM block + +maintainers: + - Rohit Agarwal <quic_rohiagar@quicinc.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SDX75 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sdx75-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 67 + + gpio-line-names: + maxItems: 133 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdx75-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdx75-tlmm-state" + additionalProperties: false + +$defs: + qcom-sdx75-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ adsp_ext, atest_char, audio_ref_clk, bimc_dte, char_exec, coex_uart2, + coex_uart, cri_trng, cri_trng0, cri_trng1, dbg_out_clk, ddr_bist, + ddr_pxi0, ebi0_wrcdc, ebi2_a, ebi2_lcd, ebi2_lcd_te, emac0_mcg, + emac0_ptp, emac1_mcg, emac1_ptp, emac_cdc, emac_pps_in, eth0_mdc, + eth0_mdio, eth1_mdc, eth1_mdio, ext_dbg, gcc_125_clk, gcc_gp1_clk, + gcc_gp2_clk, gcc_gp3_clk, gcc_plltest, gpio, i2s_mclk, jitter_bist, + ldo_en, ldo_update, m_voc, mgpi_clk, native_char, native_tsens, + native_tsense, nav_dr_sync, nav_gpio, pa_indicator, pci_e, + pcie0_clkreq_n, pcie1_clkreq_n, pcie2_clkreq_n, pll_bist_sync, + pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, + qlink0_b_en, qlink0_b_req, qlink0_l_en, qlink0_l_req, qlink0_wmss, + qlink1_l_en, qlink1_l_req, qlink1_wmss, qup_se0, qup_se1_l2_mira, + qup_se1_l2_mirb, qup_se1_l3_mira, qup_se1_l3_mirb, qup_se2, qup_se3, + qup_se4, qup_se5, qup_se6, qup_se7, qup_se8, rgmii_rx_ctl, rgmii_rxc, + rgmii_rxd, rgmii_tx_ctl, rgmii_txc, rgmii_txd, sd_card, sdc1_tb, + sdc2_tb_trig, sec_mi2s, sgmii_phy_intr0_n, sgmii_phy_intr1_n, + spmi_coex, spmi_vgi, tgu_ch0_trigout, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tri_mi2s, uim1_clk, uim1_data, uim1_present, + uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, + usb2phy_ac_en, vsense_trigger_mirnat] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sdx75-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 133>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio12"; + function = "qup_se1_l2_mira"; + bias-disable; + }; + + tx-pins { + pins = "gpio13"; + function = "qup_se1_l3_mira"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..9612e2118 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm4250-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM4250 SoC LPASS LPI TLMM + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM4250 SoC. + +properties: + compatible: + const: qcom,sm4250-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Audio voting clock + + clock-names: + items: + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm4250-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm4250-lpass-state" + additionalProperties: false + +$defs: + qcom-sm4250-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-6])$" + + function: + enum: [ gpio, dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, + dmic4_clk, dmic4_data, ext_mclk0_a, ext_mclk0_b, ext_mclk1_a, + ext_mclk1_b, ext_mclk1_c, i2s1_clk, i2s1_data, i2s1_ws, + i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, + qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, slim_clk, slim_data, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, swr_wsa_clk, + swr_wsa_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + lpi_tlmm: pinctrl@a7c0000 { + compatible = "qcom,sm4250-lpass-lpi-pinctrl"; + reg = <0xa7c0000 0x20000>, + <0xa950000 0x10000>; + clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 19>; + + i2s2-active-state { + clk-pins { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio12"; + function = "i2s2_data"; + drive-strength = <2>; + slew-rate = <1>; + }; + }; + + i2s2-sleep-clk-state { + pins = "gpio10"; + function = "i2s2_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml new file mode 100644 index 000000000..1b941b276 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm4450-tlmm.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm4450-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM4450 TLMM block + +maintainers: + - Tengfei Fan <quic_tengfan@quicinc.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM4450 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm4450-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 68 + + gpio-line-names: + maxItems: 136 + + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm4450-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm4450-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm4450-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-5])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, atest_char, atest_usb0, audio_ref_clk, cam_mclk, + cci_async_in0, cci_i2c, cci, cmu_rng, coex_uart1_rx, + coex_uart1_tx, cri_trng, dbg_out_clk, ddr_bist, + ddr_pxi0_test, ddr_pxi1_test, gcc_gp1_clk, gcc_gp2_clk, + gcc_gp3_clk, host2wlan_sol, ibi_i3c_qup0, ibi_i3c_qup1, + jitter_bist_ref, mdp_vsync0_out, mdp_vsync1_out, + mdp_vsync2_out, mdp_vsync3_out, mdp_vsync, nav, + pcie0_clk_req, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc, qdss_cti_trig0, qdss_cti_trig1, qdss_gpio, + qlink0_enable, qlink0_request, qlink0_wmss_reset, + qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, + qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2, qup1_se3, + qup1_se4, sd_write_protect, tb_trig_sdc1, tb_trig_sdc2, + tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, + tgu_ch3_trigout, tmess_prng, tsense_pwm1_out, + tsense_pwm2_out, uim0, uim1, usb0_hs_ac, usb0_phy_ps, + vfr_0_mira, vfr_0_mirb, vfr_1, vsense_trigger_mirnat, + wlan1_adc_dtest0, wlan1_adc_dtest1 ] + + required: + - pins + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sm4450-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 137>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio23"; + function = "qup1_se2"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio22"; + function = "qup1_se2"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..d2a036ead --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 SoC LPASS LPI TLMM + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM6115 SoC. + +properties: + compatible: + oneOf: + - enum: + - qcom,sm6115-lpass-lpi-pinctrl + - items: + - enum: + - qcom,qcm2290-lpass-lpi-pinctrl + - const: qcom,sm6115-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Audio voting clock + + clock-names: + items: + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6115-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6115-lpass-state" + additionalProperties: false + +$defs: + qcom-sm6115-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-8])$" + + function: + enum: [ dmic01_clk, dmic01_data, dmic23_clk, dmic23_data, gpio, i2s1_clk, + i2s1_data, i2s1_ws, i2s2_clk, i2s2_data, i2s2_ws, i2s3_clk, + i2s3_data, i2s3_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_mclk ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + + lpass_tlmm: pinctrl@a7c0000 { + compatible = "qcom,sm6115-lpass-lpi-pinctrl"; + reg = <0x0a7c0000 0x20000>, + <0x0a950000 0x10000>; + clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 19>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml new file mode 100644 index 000000000..7f36f9b93 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6115-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block + +maintainers: + - Iskren Chernev <iskren.chernev@gmail.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM4250 and SM6115 + SoCs. + +properties: + compatible: + const: qcom,sm6115-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: west + - const: south + - const: east + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6115-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6115-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm6115-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c, + cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio, + gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist, + mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte, + m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag, + pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, + qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb, + sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk, + uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, + wlan1_adc0, elan1_adc1 ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@500000 { + compatible = "qcom,sm6115-tlmm"; + reg = <0x500000 0x400000>, + <0x900000 0x400000>, + <0xd00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 114>; + + sdc2_on_state: sdc2-on-state { + clk-pins { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd-pins { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data-pins { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd-pins { + pins = "gpio88"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml new file mode 100644 index 000000000..5a57a59cc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-tlmm.yaml @@ -0,0 +1,136 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: Qualcomm Technologies, Inc. SM6125 TLMM block + +maintainers: + - Martin Botka <martin.botka@somainline.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM6125 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm6125-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: west + - const: south + - const: east + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6125-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6125-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm6125-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, + atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1, + atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2, + atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb, + audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk, + dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, + ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte, + nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable, + qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04, + qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx, + swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger, + wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ] + + required: + - pins + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@500000 { + compatible = "qcom,sm6125-tlmm"; + reg = <0x00500000 0x400000>, + <0x00900000 0x400000>, + <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + sdc2-off-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml new file mode 100644 index 000000000..b262af6be --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-tlmm.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM6350 TLMM block + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM6350 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm6350-tlmm + + reg: + maxItems: 1 + + interrupts: + minItems: 9 + maxItems: 9 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 78 + + gpio-line-names: + maxItems: 156 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6350-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6350-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm6350-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, atest_tsens, atest_tsens2, atest_usb1, atest_usb10, atest_usb11, + atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21, atest_usb22, + atest_usb23, audio_ref, btfm_slimbus, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, + cam_mclk4, cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, + dp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio, + gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, m_voc, mclk, + mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, + mss_lte, nav_gpio, nav_pps, pa_indicator, pcie0_clk, phase_flag0, phase_flag1, + phase_flag10, phase_flag11, phase_flag12, phase_flag13, phase_flag14, phase_flag15, + phase_flag16, phase_flag17, phase_flag18, phase_flag19, phase_flag2, phase_flag20, + phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25, phase_flag26, + phase_flag27, phase_flag28, phase_flag29, phase_flag3, phase_flag30, phase_flag31, + phase_flag4, phase_flag5, phase_flag6, phase_flag7, phase_flag8, phase_flag9, + pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti, qdss_gpio, qdss_gpio0, + qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, + qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, + qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, qlink0_request, qlink0_wmss, + qlink1_enable, qlink1_request, qlink1_wmss, qup00, qup01, qup02, qup10, qup11, + qup12, qup13_f1, qup13_f2, qup14, rffe0_clk, rffe0_data, rffe1_clk, rffe1_data, + rffe2_clk, rffe2_data, rffe3_clk, rffe3_data, rffe4_clk, rffe4_data, sd_write, + sdc1_tb, sdc2_tb, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, + wlan2_adc0, wlan2_adc1, ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sm6350-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 157>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio25"; + function = "qup13_f2"; + bias-disable; + }; + + tx-pins { + pins = "gpio26"; + function = "qup13_f2"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml new file mode 100644 index 000000000..c11af09c3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6375-tlmm.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM6375 TLMM block + +maintainers: + - Konrad Dybcio <konradybcio@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM6375 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm6375-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: true + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6375-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6375-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm6375-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$" + - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, + sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, + atest_char2, atest_char3, atest_tsens, atest_tsens2, + atest_usb1, atest_usb10, atest_usb11, atest_usb12, + atest_usb13, atest_usb2, atest_usb20, atest_usb21, + atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk, + cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2, + cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, + gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, gp_pdm1, gp_pdm2, gpio, + gps_tx, ibi_i3c, jitter_bist, ldo_en, ldo_update, lpass_ext, + m_voc, mclk, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, + mdp_vsync3, mi2s_0, mi2s_1, mi2s_2, mss_lte, nav_gpio, + nav_pps, pa_indicator, phase_flag0, phase_flag1, phase_flag10, + phase_flag11, phase_flag12, phase_flag13, phase_flag14, + phase_flag15, phase_flag16, phase_flag17, phase_flag18, + phase_flag19, phase_flag2, phase_flag20, phase_flag21, + phase_flag22, phase_flag23, phase_flag24, phase_flag25, + phase_flag26, phase_flag27, phase_flag28, phase_flag29, + phase_flag3, phase_flag30, phase_flag31, phase_flag4, + phase_flag5, phase_flag6, phase_flag7, phase_flag8, + phase_flag9, pll_bist, pll_bypassnl, pll_clk, pll_reset, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, qdss_gpio11, + qdss_gpio12, qdss_gpio13, qdss_gpio14, qdss_gpio15, + qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, qdss_gpio6, + qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable, + qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, + qlink1_wmss, qup00, qup01, qup02, qup10, qup11_f1, qup11_f2, + qup12, qup13_f1, qup13_f2, qup14, sd_write, sdc1_tb, sdc2_tb, + sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, uim1_clk, uim1_data, uim1_present, uim1_reset, + uim2_clk, uim2_data, uim2_present, uim2_reset, usb2phy_ac, + usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, + wlan2_adc0, wlan2_adc1 ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@500000 { + compatible = "qcom,sm6375-tlmm"; + reg = <0x00500000 0x800000>; + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */ + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio18"; + function = "qup13_f2"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio19"; + function = "qup13_f2"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm7150-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm7150-tlmm.yaml new file mode 100644 index 000000000..7f23f939a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm7150-tlmm.yaml @@ -0,0 +1,146 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm7150-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM7150 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Danila Tikhonov <danila@jiaxyga.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM7150 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm7150-tlmm + + reg: + maxItems: 3 + + reg-names: + items: + - const: west + - const: north + - const: south + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 60 + + gpio-line-names: + maxItems: 119 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm7150-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm7150-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm7150-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, + sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens, + atest_tsens2, atest_usb1, atest_usb2, cam_mclk, cci_async, + cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, + ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gp_pdm0, + gp_pdm1, gp_pdm2, gps_tx, jitter_bist, ldo_en, ldo_update, + m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, + mdp_vsync3, mss_lte, nav_pps_in, nav_pps_out, pa_indicator, + pci_e, phase_flag, pll_bist, pll_bypassnl, pll_reset, pri_mi2s, + pri_mi2s_ws, prng_rosc, qdss, qdss_cti, qlink_enable, + qlink_request, qua_mi2s, qup00, qup01, qup02, qup03, qup04, + qup10, qup11, qup12, qup13, qup14, qup15, sd_write, sdc40, + sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, ter_mi2s, + tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsif1_clk, tsif1_data, + tsif1_en, tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, + tsif2_en, tsif2_error, tsif2_sync, uim1_clk, uim1_data, + uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, + uim2_reset, uim_batt, usb_phy, vfr_1, vsense_trigger, + wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, + wsa_data ] + + required: + - pins + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@3500000 { + compatible = "qcom,sm7150-tlmm"; + reg = <0x03500000 0x300000>, + <0x03900000 0x300000>, + <0x03d00000 0x300000>; + reg-names = "west", "north", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&tlmm 0 0 120>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio44"; + function = "qup12"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio45"; + function = "qup12"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml new file mode 100644 index 000000000..c4542e2d7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8150-pinctrl.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8150-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8150 TLMM pin controller + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + - Krzysztof Kozlowski <krzk@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8150 SoC. + +properties: + compatible: + const: qcom,sm8150-pinctrl + + reg: + maxItems: 4 + + reg-names: + items: + - const: west + - const: east + - const: north + - const: south + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 88 + + gpio-line-names: + maxItems: 175 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8150-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8150-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8150-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-6][0-9]|17[0-4])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, aoss_cti, ddr_pxi2, atest_char, + atest_char0, atest_char1, atest_char2, atest_char3, audio_ref, + atest_usb1, atest_usb2, atest_usb10, atest_usb11, atest_usb12, + atest_usb13, atest_usb20, atest_usb21, atest_usb22, + atest_usb23, btfm_slimbus, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, + ddr_pxi1, ddr_pxi3, edp_hot, edp_lcd, emac_phy, emac_pps, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, + jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mss_lte, m_voc, nav_pps, pa_indicator, + pci_e0, phase_flag, pll_bypassnl, pll_bist, pci_e1, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, qdss, qdss_cti, + qlink_request, qlink_enable, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qua_mi2s, qup0, qup1, qup2, qup3, qup4, + qup5, qup6, qup7, qup8, qup9, qup10, qup11, qup12, qup13, + qup14, qup15, qup16, qup17, qup18, qup19, qup_l4, qup_l5, + qup_l6, rgmii, sdc4, sd_write, sec_mi2s, spkr_i2s, sp_cmu, + ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, + tsense_pwm2, tsif1, tsif2, uim1, uim2, uim_batt, usb2phy_ac, + usb_phy, vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, + wlan2_adc0, wlan2_adc1, wmss_reset ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + tlmm: pinctrl@3100000 { + compatible = "qcom,sm8150-pinctrl"; + reg = <0x03100000 0x300000>, + <0x03500000 0x300000>, + <0x03900000 0x300000>, + <0x03d00000 0x300000>; + reg-names = "west", "east", "north", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&tlmm 0 0 176>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + wakeup-parent = <&pdc>; + + qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup0"; + drive-strength = <6>; + bias-disable; + }; + + pcie1-default-state { + perst-pins { + pins = "gpio102"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio103"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio104"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..750c996c1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8250 SoC LPASS LPI TLMM + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM8250 SoC. + +properties: + compatible: + const: qcom,sm8250-lpass-lpi-pinctrl + + reg: + maxItems: 2 + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8250-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8250-lpass-state" + additionalProperties: false + +$defs: + qcom-sm8250-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|1[0-3])$" + minItems: 1 + maxItems: 14 + + function: + enum: [ gpio, swr_tx_clk, qua_mi2s_sclk, swr_tx_data, qua_mi2s_ws, + qua_mi2s_data, swr_rx_clk, swr_rx_data, dmic1_clk, i2s1_clk, + dmic1_data, i2s1_ws, dmic2_clk, dmic2_data, i2s1_data, + i2s2_clk, wsa_swr_clk, i2s2_ws, wsa_swr_data, dmic3_clk, + dmic3_data, i2s2_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + lpi_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8250-lpass-lpi-pinctrl"; + reg = <0x33c0000 0x20000>, + <0x3550000 0x10000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 14>; + + wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + }; + }; + + tx-swr-sleep-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml new file mode 100644 index 000000000..b5d04347c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8250 TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Qualcomm SM8250 SoC. + +properties: + compatible: + const: qcom,sm8250-pinctrl + + reg: + maxItems: 3 + + reg-names: + items: + - const: west + - const: south + - const: north + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 90 + + gpio-line-names: + maxItems: 180 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8250-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8250-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8250-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio, + ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1, + pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, + qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6, + qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, + sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1, + tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data, + tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en, + tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ] + + required: + - pins + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + - reg-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@1f00000 { + compatible = "qcom,sm8250-pinctrl"; + reg = <0x0f100000 0x300000>, + <0x0f500000 0x300000>, + <0x0f900000 0x300000>; + reg-names = "west", "south", "north"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */ + wakeup-parent = <&pdc>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..46aec0713 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8350 SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM8350 SoC. + +properties: + compatible: + const: qcom,sm8350-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8350-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8350-lpass-state" + additionalProperties: false + +$defs: + qcom-sm8350-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk, + i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk, + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8350-lpass-lpi-pinctrl"; + reg = <0x033c0000 0x20000>, + <0x03550000 0x10000>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml new file mode 100644 index 000000000..ec5e09611 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8350-tlmm.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8350 TLMM block + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8350 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8350-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 102 + + gpio-line-names: + maxItems: 203 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8350-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8350-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8350-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, + cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, + mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, + mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, + mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, + mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator, + pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, + qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, + qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, + qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, + qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, + qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, + qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, + tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, + uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present, + uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sm8350-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */ + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx-pins { + pins = "gpio18"; + function = "qup3"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio19"; + function = "qup3"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..541c1c54d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8450 SoC LPASS LPI TLMM + +maintainers: + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM8450 SoC. + +properties: + compatible: + oneOf: + - const: qcom,sm8450-lpass-lpi-pinctrl + - items: + - enum: + - qcom,qcs8300-lpass-lpi-pinctrl + - qcom,sa8775p-lpass-lpi-pinctrl + - const: qcom,sm8450-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8450-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8450-lpass-state" + additionalProperties: false + +$defs: + qcom-sm8450-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data, + dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic4_clk, + dmic4_data, i2s2_clk, i2s2_ws, dmic3_clk, dmic3_data, + qua_mi2s_sclk, qua_mi2s_ws, qua_mi2s_data, i2s1_clk, i2s1_ws, + i2s1_data, wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, + wsa2_swr_data, i2s2_data, i2s4_ws, i2s4_clk, i2s4_data, + slimbus_clk, i2s3_clk, i2s3_ws, i2s3_data, slimbus_data, + ext_mclk1_c, ext_mclk1_b, ext_mclk1_a, ext_mclk1_d, + ext_mclk1_e ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + pinctrl@3440000 { + compatible = "qcom,sm8450-lpass-lpi-pinctrl"; + reg = <0x3440000 0x20000>, + <0x34d0000 0x10000>; + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 23>; + + wsa-swr-active-state { + clk-pins { + pins = "gpio10"; + function = "wsa_swr_clk"; + drive-strength = <2>; + slew-rate = <1>; + bias-disable; + }; + + data-pins { + pins = "gpio11"; + function = "wsa_swr_data"; + drive-strength = <2>; + slew-rate = <1>; + }; + }; + + tx-swr-sleep-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml new file mode 100644 index 000000000..16fd2c5e2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8450-tlmm.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8450 TLMM block + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8450 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8450-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 105 + + gpio-line-names: + maxItems: 210 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8450-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8450-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8450-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async, + cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3, + gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, + mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, + mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, + mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, + mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn, + pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s, + prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request, + qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss, + qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1, + qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, + qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2, + qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, + qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, + tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present, + uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset, + usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + pinctrl@f100000 { + compatible = "qcom,sm8450-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..89821871c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC. + +properties: + compatible: + oneOf: + - const: qcom,sm8550-lpass-lpi-pinctrl + - items: + - const: qcom,x1e80100-lpass-lpi-pinctrl + - const: qcom,sm8550-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8550-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8550-lpass-state" + additionalProperties: false + +$defs: + qcom-sm8550-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk, + i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk, + swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> + + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,sm8550-lpass-lpi-pinctrl"; + reg = <0x06e80000 0x20000>, + <0x0725a000 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx-swr-sleep-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml new file mode 100644 index 000000000..c2ae79df4 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8550-tlmm.yaml @@ -0,0 +1,148 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8550 TLMM block + +maintainers: + - Abel Vesa <abel.vesa@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8550-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 105 + + gpio-line-names: + maxItems: 210 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8550-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8550-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8550-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aon_cci, aoss_cti, atest_char, atest_usb, + audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, + cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl, + cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx, + coex_uart1_tx, coex_uart2_rx, coex_uart2_tx, + cri_trng, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, + gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0, + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, + i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, + i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, + ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, + pcie0_clk_req_n, pcie1_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, + qlink0_enable, qlink0_request, qlink0_wmss, + qlink1_enable, qlink1_request, qlink1_wmss, + qlink2_enable, qlink2_request, qlink2_wmss, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, + qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, + qup1_se5, qup1_se6, qup1_se7, qup2_se0, + qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira, + qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb, + qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, + qup2_se7, sd_write_protect, sdc40, sdc41, sdc42, + sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, + tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, + tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, + uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, + usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8550-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup2_se7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup2_se7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000..1bf08860a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8650 SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM8650 SoC. + +properties: + compatible: + oneOf: + - const: qcom,sm8650-lpass-lpi-pinctrl + - items: + - enum: + - qcom,glymur-lpass-lpi-pinctrl + - qcom,sm8750-lpass-lpi-pinctrl + - const: qcom,sm8650-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8650-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8650-lpass-state" + additionalProperties: false + +$defs: + qcom-sm8650-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk, + i2s4_data, i2s4_ws, qca_swr_clk, qca_swr_data, slimbus_clk, + slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, + wsa_swr_clk, wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> + + lpass_tlmm: pinctrl@6e80000 { + compatible = "qcom,sm8650-lpass-lpi-pinctrl"; + reg = <0x06e80000 0x20000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + + tx-swr-sleep-clk-state { + pins = "gpio0"; + function = "swr_tx_clk"; + drive-strength = <2>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-tlmm.yaml new file mode 100644 index 000000000..c0a06abf8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8650-tlmm.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8650-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8650 TLMM block + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8650 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8650-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 105 + + gpio-line-names: + maxItems: 210 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8650-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8650-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8650-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, + coex_uart2_tx, cri_trng, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi0, + ddr_pxi1, ddr_pxi2, ddr_pxi3, do_not, dp_hot, gcc_gp1, + gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1, i2chub0_se0, + i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, + i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, + jitter_bist, mdp_vsync, mdp_vsync0_out, mdp_vsync1_out, + mdp_vsync2_out, mdp_vsync3_out, mdp_vsync_e, nav_gpio0, + nav_gpio1, nav_gpio2, nav_gpio3, pcie0_clk_req_n, + pcie1_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio, qlink_big_enable, qlink_big_request, + qlink_little_enable, qlink_little_request, qlink_wmss, + qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup1_se0, + qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, qup1_se6, + qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4, + qup2_se5, qup2_se6, qup2_se7, sd_write_protect, sdc40, sdc41, + sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, + tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout, + tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2, + tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, uim0_clk, + uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, + uim1_present, uim1_reset, usb1_hs, usb_phy, vfr_0, vfr_1, + vsense_trigger_mirnat ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8650-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 211>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio60"; + function = "qup1_se7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio61"; + function = "qup1_se7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml new file mode 100644 index 000000000..7aecc9774 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8750-tlmm.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8750-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8750 TLMM block + +maintainers: + - Melody Olvera <quic_molvera@quicinc.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SM8750 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm8750-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 108 + + gpio-line-names: + maxItems: 215 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm8750-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm8750-tlmm-state" + additionalProperties: false + +$defs: + qcom-sm8750-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-4])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0, + audio_ext_mclk1, audio_ref_clk, cam_aon_mclk2, cam_aon_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, coex_uart1_rx, coex_uart1_tx, coex_uart2_rx, + coex_uart2_tx, dbg_out_clk, ddr_bist_complete, ddr_bist_fail, + ddr_bist_start, ddr_bist_stop, ddr_pxi0, ddr_pxi1, ddr_pxi2, + ddr_pxi3, dp_hot, egpio, gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, + gnss_adc1, i2chub0_se0, i2chub0_se1, i2chub0_se2, i2chub0_se3, + i2chub0_se4, i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8, + i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, + i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, + mdp_esync0_out, mdp_esync1_out, mdp_vsync, mdp_vsync0_out, + mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out, + mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3, + pcie0_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qlink_big_enable, qlink_big_request, qlink_little_enable, + qlink_little_request, qlink_wmss, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, + sd_write_protect, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4, tmess_prng0, tmess_prng1, + tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3, + tsense_pwm4, uim0_clk, uim0_data, uim0_present, uim0_reset, + uim1_clk, uim1_data, uim1_present, uim1_reset, usb1_hs, usb_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8750-tlmm"; + reg = <0x0f100000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 216>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio60"; + function = "qup1_se7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio61"; + function = "qup1_se7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml new file mode 100644 index 000000000..aae3dcf6c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,tlmm-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Top Level Mode Multiplexer (TLMM) definitions + +maintainers: + - Bjorn Andersson <bjorn.andersson@linaro.org> + +description: + This defines the common properties used to describe all Qualcomm Top Level + Mode Multiplexer bindings and pinconf/pinmux states for these. + +properties: + interrupts: + description: + TLMM summary IRQ and dirconn interrupts. + minItems: 1 + maxItems: 9 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: + Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-parent: + description: + Specifying the interrupt-controller used to wake up the system when the + TLMM block has been powered down. + + gpio-reserved-ranges: + description: + Pins can be reserved for trusted applications and thereby unaccessible + from the OS. This property can be used to mark the pins which resources + should not be accessed by the OS. Please see the ../gpio/gpio.txt for more + information. + +allOf: + - $ref: pinctrl.yaml# + +required: + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: true + +$defs: + qcom-tlmm-state: + properties: + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + input-enable: false + output-disable: true + output-enable: true + output-high: true + output-low: true + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + - if: + properties: + pins: + items: + pattern: "^gpio" + then: + required: + - function + else: + properties: + function: false + + additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml new file mode 100644 index 000000000..a1333e074 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,x1e80100-tlmm.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,x1e80100-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. X1E80100 TLMM block + +maintainers: + - Rajendra Nayak <quic_rjendra@quicinc.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm X1E80100 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,x1e80100-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 119 + + gpio-line-names: + maxItems: 238 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-x1e80100-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-x1e80100-tlmm-state" + additionalProperties: false + +$defs: + qcom-x1e80100-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-2][0-9]|23[0-7])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ aon_cci, aoss_cti, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, atest_usb, + audio_ext, audio_ref, cam_aon, cam_mclk, cci_async, + cci_i2c, cci_timer0, cci_timer1, cci_timer2, cci_timer3, + cci_timer4, cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, + cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, ddr_pxi6, ddr_pxi7, + edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, eusb0_ac, eusb1_ac, + eusb2_ac, eusb3_ac, eusb5_ac, eusb6_ac, gcc_gp1, gcc_gp2, + gcc_gp3, gpio, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws, i2s1_data0, + i2s1_data1, i2s1_sck, i2s1_ws, ibi_i3c, jitter_bist, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, + mdp_vsync6, mdp_vsync7, mdp_vsync8, pcie3_clk, pcie4_clk, + pcie5_clk, pcie6a_clk, pcie6b_clk, phase_flag, pll_bist, pll_clk, + prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti, + qdss_gpio, qspi00, qspi01, qspi02, qspi03, qspi0_clk, qspi0_cs0, + qspi0_cs1, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, + qup0_se5, qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3, + qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, + qup2_se3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, sd_write, sdc4_clk, + sdc4_cmd, sdc4_data0, sdc4_data1, sdc4_data2, sdc4_data3, sys_throttle, + tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, + tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, sense_pwm3, tsense_pwm4, usb0_dp, usb0_phy, + usb0_sbrx, usb0_sbtx, usb1_dp, usb1_phy, usb1_sbrx, usb1_sbtx, + usb2_dp, usb2_phy, usb2_sbrx, usb2_sbtx, vsense_trigger ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,x1e80100-tlmm"; + reg = <0x0f100000 0xf00000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 239>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-wo-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-state { + rx-pins { + pins = "gpio26"; + function = "qup2_se7"; + bias-pull-up; + }; + + tx-pins { + pins = "gpio27"; + function = "qup2_se7"; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml new file mode 100644 index 000000000..43b33dbf1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinctrl.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT2880 Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + Ralink RT2880 pin controller for RT2880 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt2880-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: sdram + then: + properties: + groups: + enum: [sdram] + + - if: + properties: + function: + const: pci + then: + properties: + groups: + enum: [pci] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,rt2880-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml new file mode 100644 index 000000000..95a904273 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt305x-pinctrl.yaml @@ -0,0 +1,206 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt305x-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT305X Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + Ralink RT305X pin controller for RT3050, RT3052, and RT3350 SoCs. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt305x-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio, + pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf, + uartlite] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: rgmii + then: + properties: + groups: + enum: [rgmii] + + - if: + properties: + function: + const: sdram + then: + properties: + groups: + enum: [sdram] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,rt305x-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml new file mode 100644 index 000000000..c9bc6cfd8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3352-pinctrl.yaml @@ -0,0 +1,243 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt3352-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT3352 Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + Ralink RT3352 pin controller for RT3352 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt3352-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, lna, + mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, + uartf, uartlite, wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1, + uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: lna + then: + properties: + groups: + enum: [lna] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pa + then: + properties: + groups: + enum: [pa] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: rgmii + then: + properties: + groups: + enum: [rgmii] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,rt3352-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml new file mode 100644 index 000000000..8d14e525b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt3883-pinctrl.yaml @@ -0,0 +1,261 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt3883-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT3883 Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + Ralink RT3883 pin controller for RT3883 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt3883-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, + lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2, + pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: ge1 + then: + properties: + groups: + enum: [ge1] + + - if: + properties: + function: + const: ge2 + then: + properties: + groups: + enum: [ge2] + + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, + uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: lna a + then: + properties: + groups: + enum: [lna a] + + - if: + properties: + function: + const: lna g + then: + properties: + groups: + enum: [lna g] + + - if: + properties: + function: + const: mdio + then: + properties: + groups: + enum: [mdio] + + - if: + properties: + function: + const: pci-dev + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-fnc + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-host1 + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pci-host2 + then: + properties: + groups: + enum: [pci] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,rt3883-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml new file mode 100644 index 000000000..f248202ce --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ralink,rt5350-pinctrl.yaml @@ -0,0 +1,206 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ralink,rt5350-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ralink RT5350 Pin Controller + +maintainers: + - Arınç ÜNAL <arinc.unal@arinc9.com> + - Sergio Paracuellos <sergio.paracuellos@gmail.com> + +description: | + Ralink RT5350 pin controller for RT5350 SoC. + The pin controller can only set the muxing of pin groups. Muxing individual + pins is not supported. There is no pinconf support. + +properties: + compatible: + const: ralink,rt5350-pinctrl + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '^(.*-)?pinmux$': + type: object + description: node for pinctrl. + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + function: + description: + A string containing the name of the function to mux to the group. + enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, + pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf, uartlite, + wdg_cs1] + + groups: + description: + An array of strings. Each string contains the name of a group. + maxItems: 1 + + required: + - groups + - function + + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + groups: + enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite] + + - if: + properties: + function: + const: gpio i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: gpio uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: i2c + then: + properties: + groups: + enum: [i2c] + + - if: + properties: + function: + const: i2s uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: jtag + then: + properties: + groups: + enum: [jtag] + + - if: + properties: + function: + const: led + then: + properties: + groups: + enum: [led] + + - if: + properties: + function: + const: pcm gpio + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm i2s + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: pcm uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: spi + then: + properties: + groups: + enum: [spi] + + - if: + properties: + function: + const: spi_cs1 + then: + properties: + groups: + enum: [spi_cs1] + + - if: + properties: + function: + const: uartf + then: + properties: + groups: + enum: [uartf] + + - if: + properties: + function: + const: uartlite + then: + properties: + groups: + enum: [uartlite] + + - if: + properties: + function: + const: wdg_cs1 + then: + properties: + groups: + enum: [spi_cs1] + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + pinctrl { + compatible = "ralink,rt5350-pinctrl"; + + i2c_pins: i2c0-pins { + pinmux { + groups = "i2c"; + function = "i2c"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml new file mode 100644 index 000000000..af6fbbd4f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml @@ -0,0 +1,231 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/raspberrypi,rp1-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RaspberryPi RP1 GPIO/Pinconf/Pinmux Controller submodule + +maintainers: + - A. della Porta <andrea.porta@suse.com> + +description: + The RP1 chipset is a Multi Function Device containing, among other + sub-peripherals, a gpio/pinconf/mux controller whose 54 pins are grouped + into 3 banks. + It works also as an interrupt controller for those gpios. + +properties: + compatible: + const: raspberrypi,rp1-gpio + + reg: + maxItems: 3 + description: One reg specifier for each one of the 3 pin banks. + + '#gpio-cells': + description: The first cell is the pin number and the second cell is used + to specify the flags (see include/dt-bindings/gpio/gpio.h). + const: 2 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + gpio-line-names: + maxItems: 54 + + interrupts: + maxItems: 3 + description: One interrupt specifier for each one of the 3 pin banks. + + '#interrupt-cells': + description: + Specifies the Bank number [0, 1, 2] and Flags as defined in + include/dt-bindings/interrupt-controller/irq.h. + const: 2 + + interrupt-controller: true + +patternProperties: + '-state$': + oneOf: + - $ref: '#/$defs/raspberrypi-rp1-state' + - patternProperties: + '-pins$': + $ref: '#/$defs/raspberrypi-rp1-state' + additionalProperties: false + +$defs: + raspberrypi-rp1-state: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode (either this or "groups" must be specified). + items: + pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$' + + groups: + description: + List of groups affected by the properties specified in this + subnode (either this or "pins" must be specified). + items: + anyOf: + - pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$' + - enum: [ uart0, uart0_ctrl, uart1, uart1_ctrl, uart2, uart2_ctrl, + uart3, uart3_ctrl, uart4, uart4_ctrl, uart5_0, + uart5_0_ctrl, uart5_1, uart5_1_ctrl, uart5_2, + uart5_2_ctrl, uart5_3, + sd0, sd1, + i2s0, i2s0_dual, i2s0_quad, i2s1, i2s1_dual, i2s1_quad, + i2s2_0, i2s2_0_dual, i2s2_1, i2s2_1_dual, + i2c4_0, i2c4_1, i2c4_2, i2c4_3, i2c6_0, i2c6_1, i2c5_0, + i2c5_1, i2c5_2, i2c5_3, i2c0_0, i2c0_1, i2c1_0, i2c1_1, + i2c2_0, i2c2_1, i2c3_0, i2c3_1, i2c3_2, + dpi_16bit, dpi_16bit_cpadhi, dpi_16bit_pad666, + dpi_18bit, dpi_18bit_cpadhi, dpi_24bit, + spi0, spi0_quad, spi1, spi2, spi3, spi4, spi5, spi6_0, + spi6_1, spi7_0, spi7_1, spi8_0, spi8_1, + aaud_0, aaud_1, aaud_2, aaud_3, aaud_4, + vbus0_0, vbus0_1, vbus1, vbus2, vbus3, + mic_0, mic_1, mic_2, mic_3, + ir ] + + function: + enum: [ alt0, alt1, alt2, alt3, alt4, gpio, alt6, alt7, alt8, none, + aaud, dcd0, dpi, dsi0_te_ext, dsi1_te_ext, dsr0, dtr0, gpclk0, + gpclk1, gpclk2, gpclk3, gpclk4, gpclk5, i2c0, i2c1, i2c2, i2c3, + i2c4, i2c5, i2c6, i2s0, i2s1, i2s2, ir, mic, pcie_clkreq_n, + pio, proc_rio, pwm0, pwm1, ri0, sd0, sd1, spi0, spi1, spi2, + spi3, spi4, spi5, spi6, spi7, spi8, uart0, uart1, uart2, uart3, + uart4, uart5, vbus0, vbus1, vbus2, vbus3 ] + + description: + Specify the alternative function to be configured for the specified + pins. + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-enable: true + input-schmitt-enable: true + output-enable: true + output-high: true + output-low: true + slew-rate: + description: 0 is slow slew rate, 1 is fast slew rate + enum: [ 0, 1 ] + drive-strength: + enum: [ 2, 4, 8, 12 ] + + required: + - function + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - reg + - compatible + - '#gpio-cells' + - gpio-controller + - interrupts + - '#interrupt-cells' + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + rp1 { + #address-cells = <2>; + #size-cells = <2>; + + rp1_gpio: pinctrl@c0400d0000 { + reg = <0xc0 0x400d0000 0x0 0xc000>, + <0xc0 0x400e0000 0x0 0xc000>, + <0xc0 0x400f0000 0x0 0xc000>; + compatible = "raspberrypi,rp1-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <1 IRQ_TYPE_LEVEL_HIGH>, + <2 IRQ_TYPE_LEVEL_HIGH>; + gpio-line-names = + "ID_SDA", // GPIO0 + "ID_SCL", // GPIO1 + "GPIO2", "GPIO3", "GPIO4", "GPIO5", "GPIO6", + "GPIO7", "GPIO8", "GPIO9", "GPIO10", "GPIO11", + "GPIO12", "GPIO13", "GPIO14", "GPIO15", "GPIO16", + "GPIO17", "GPIO18", "GPIO19", "GPIO20", "GPIO21", + "GPIO22", "GPIO23", "GPIO24", "GPIO25", "GPIO26", + "GPIO27", + "PCIE_RP1_WAKE", // GPIO28 + "FAN_TACH", // GPIO29 + "HOST_SDA", // GPIO30 + "HOST_SCL", // GPIO31 + "ETH_RST_N", // GPIO32 + "", // GPIO33 + "CD0_IO0_MICCLK", // GPIO34 + "CD0_IO0_MICDAT0", // GPIO35 + "RP1_PCIE_CLKREQ_N", // GPIO36 + "", // GPIO37 + "CD0_SDA", // GPIO38 + "CD0_SCL", // GPIO39 + "CD1_SDA", // GPIO40 + "CD1_SCL", // GPIO41 + "USB_VBUS_EN", // GPIO42 + "USB_OC_N", // GPIO43 + "RP1_STAT_LED", // GPIO44 + "FAN_PWM", // GPIO45 + "CD1_IO0_MICCLK", // GPIO46 + "2712_WAKE", // GPIO47 + "CD1_IO1_MICDAT1", // GPIO48 + "EN_MAX_USB_CUR", // GPIO49 + "", // GPIO50 + "", // GPIO51 + "", // GPIO52 + ""; // GPIO53 + + rp1-i2s0-default-state { + function = "i2s0"; + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + bias-disable; + }; + + rp1-uart0-default-state { + txd-pins { + function = "uart0"; + pins = "gpio14"; + bias-disable; + }; + + rxd-pins { + function = "uart0"; + pins = "gpio15"; + bias-pull-up; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml new file mode 100644 index 000000000..2a640e495 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1315e-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1315E Pin Controller + +maintainers: + - TY Chang <tychang@realtek.com> + +description: + The Realtek DHC RTD1315E is a high-definition media processor SoC. The + RTD1315E pin controller is used to control pin function, pull up/down + resistor, drive strength, schmitt trigger and power source. + +properties: + compatible: + const: realtek,rtd1315e-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + items: + enum: [ gpio_0, gpio_1, emmc_rst_n, emmc_dd_sb, emmc_clk, emmc_cmd, + gpio_6, gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, + gpio_13, gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, + gpio_20, emmc_data_0, emmc_data_1, emmc_data_2, usb_cc2, gpio_25, + gpio_26, gpio_27, gpio_28, gpio_29, gpio_30, gpio_31, gpio_32, + gpio_33, gpio_34, gpio_35, hif_data, hif_en, hif_rdy, hif_clk, + gpio_dummy_40, gpio_dummy_41, gpio_dummy_42, gpio_dummy_43, + gpio_dummy_44, gpio_dummy_45, gpio_46, gpio_47, gpio_48, gpio_49, + gpio_50, usb_cc1, emmc_data_3, emmc_data_4, ir_rx, ur0_rx, ur0_tx, + gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_dummy_63, + gpio_dummy_64, gpio_dummy_65, gpio_66, gpio_67, gpio_68, gpio_69, + gpio_70, gpio_71, gpio_72, gpio_dummy_73, emmc_data_5, emmc_data_6, + emmc_data_7, gpio_dummy_77, gpio_78, gpio_79, gpio_80, gpio_81, + ur2_loc, gspi_loc, hi_width, sf_en, arm_trace_dbg_en, + ejtag_aucpu_loc, ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc, + dmic_loc, vtc_dmic_loc, vtc_tdm_loc, vtc_i2si_loc, tdm_ai_loc, + ai_loc, spdif_loc, hif_en_loc, scan_switch, wd_rset, boot_sel, + reset_n, testmode ] + + function: + enum: [ gpio, nf, emmc, ao, gspi_loc0, gspi_loc1, uart0, uart1, + uart2_loc0, uart2_loc1, i2c0, i2c1, i2c4, i2c5, pcie1, + etn_led, etn_phy, spi, pwm0_loc0, pwm0_loc1, pwm1_loc0, + pwm1_loc1, pwm2_loc0, pwm2_loc1, pwm3_loc0, pwm3_loc1, + spdif_optical_loc0, spdif_optical_loc1, usb_cc1, usb_cc2, + sd, dmic_loc0, dmic_loc1, ai_loc0, ai_loc1, tdm_ai_loc0, + tdm_ai_loc1, hi_loc0, hi_m, vtc_i2so, vtc_i2si_loc0, + vtc_i2si_loc1, vtc_dmic_loc0, vtc_dmic_loc1, vtc_tdm_loc0, + vtc_tdm_loc1, dc_fan, pll_test_loc0, pll_test_loc1, + ir_rx, uart2_disable, gspi_disable, hi_width_disable, + hi_width_1bit, sf_disable, sf_enable, scpu_ejtag_loc0, + scpu_ejtag_loc1, scpu_ejtag_loc2, scpu_ejtag_loc3, + acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2, + vcpu_ejtag_loc0, vcpu_ejtag_loc1, vcpu_ejtag_loc2, + aucpu_ejtag_loc0, aucpu_ejtag_loc1, aucpu_ejtag_loc2, + gpu_ejtag, iso_tristate, dbg_out0, dbg_out1, standby_dbg, + spdif, arm_trace_debug_disable, arm_trace_debug_enable, + aucpu_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable, + scpu_ejtag_disable, vtc_dmic_loc_disable, vtc_tdm_disable, + vtc_i2si_disable, tdm_ai_disable, ai_disable, spdif_disable, + hif_disable, hif_enable, test_loop, pmic_pwrup ] + + drive-strength: + enum: [4, 8] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-push-pull: true + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + realtek,drive-strength-p: + description: | + Some of pins can be driven using the P-MOS and N-MOS transistor to + achieve finer adjustments. The block-diagram representation is as + follows: + VDD + | + ||--+ + +-----o|| P-MOS-FET + | ||--+ + IN --+ +----- out + | ||--+ + +------|| N-MOS-FET + ||--+ + | + GND + The driving strength of the P-MOS/N-MOS transistors impacts the + waveform's rise/fall times. Greater driving strength results in + shorter rise/fall times. Each P-MOS and N-MOS transistor offers + 8 configurable levels (0 to 7), with higher values indicating + greater driving strength, contributing to achieving the desired + speed. + + The realtek,drive-strength-p is used to control the driving strength + of the P-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,drive-strength-n: + description: | + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n + is used to control the driving strength of the N-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,duty-cycle: + description: | + An integer describing the level to adjust the output pulse width, it + provides a fixed nanosecond-level adjustment to the rising/falling + edges of an existing signal. It is used for Signal Integrity tuning + (adding/subtracting delay to fine-tune the high/low duration), rather + than generating a specific PWM frequency. + Valid arguments are described as below: + 0: 0ns + 2: + 0.25ns + 3: + 0.5ns + 4: -0.25ns + 5: -0.5ns + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 2, 3, 4, 5 ] + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4e000 { + compatible = "realtek,rtd1315e-pinctrl"; + reg = <0x4e000 0x130>; + + emmc-hs200-pins { + pins = "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + function = "emmc"; + realtek,drive-strength-p = <0x2>; + realtek,drive-strength-n = <0x2>; + }; + + i2c-0-pins { + pins = "gpio_12", + "gpio_13"; + function = "i2c0"; + drive-strength = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml new file mode 100644 index 000000000..2136546ad --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1319d-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1319D Pin Controller + +maintainers: + - TY Chang <tychang@realtek.com> + +description: + The Realtek DHC RTD1319D is a high-definition media processor SoC. The + RTD1319D pin controller is used to control pin function, pull up/down + resistor, drive strength, schmitt trigger and power source. + +properties: + compatible: + const: realtek,rtd1319d-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + items: + enum: [ gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7, + gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, gpio_14, + gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, gpio_21, + gpio_22, gpio_23, usb_cc2, gpio_25, gpio_26, gpio_27, gpio_28, + gpio_29, gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, + hif_data, hif_en, hif_rdy, hif_clk, gpio_40, gpio_41, gpio_42, + gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, gpio_48, gpio_49, + gpio_50, usb_cc1, gpio_52, gpio_53, ir_rx, ur0_rx, ur0_tx, + gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_63, + gpio_64, emmc_rst_n, emmc_dd_sb, emmc_clk, emmc_cmd, emmc_data_0, + emmc_data_1, emmc_data_2, emmc_data_3, emmc_data_4, emmc_data_5, + emmc_data_6, emmc_data_7, dummy, gpio_78, gpio_79, gpio_80, + gpio_81, ur2_loc, gspi_loc, hi_width, sf_en, arm_trace_dbg_en, + ejtag_aucpu_loc, ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc, + dmic_loc, ejtag_secpu_loc, vtc_dmic_loc, vtc_tdm_loc, vtc_i2si_loc, + tdm_ai_loc, ai_loc, spdif_loc, hif_en_loc, sc0_loc, sc1_loc, + scan_switch, wd_rset, boot_sel, reset_n, testmode ] + + function: + enum: [ gpio, nf, emmc, tp0, tp1, sc0, sc0_data0, sc0_data1, sc0_data2, + sc1, sc1_data0, sc1_data1, sc1_data2, ao, gspi_loc0, gspi_loc1, + uart0, uart1, uart2_loc0, uart2_loc1, i2c0, i2c1, i2c3, i2c4, + i2c5, pcie1, sdio, etn_led, etn_phy, spi, pwm0_loc0, pwm0_loc1, + pwm1_loc0, pwm1_loc1, pwm2_loc0, pwm2_loc1, pwm3_loc0, pwm3_loc1, + qam_agc_if0, qam_agc_if1, spdif_optical_loc0, spdif_optical_loc1, + usb_cc1, usb_cc2, vfd, sd, dmic_loc0, dmic_loc1, ai_loc0, ai_loc1, + tdm_ai_loc0, tdm_ai_loc1, hi_loc0, hi_m, vtc_i2so, vtc_i2si_loc0, + vtc_i2si_loc1, vtc_dmic_loc0, vtc_dmic_loc1, vtc_tdm_loc0, + vtc_tdm_loc1, dc_fan, pll_test_loc0, pll_test_loc1, ir_rx, + uart2_disable, gspi_disable, hi_width_disable, hi_width_1bit, + sf_disable, sf_enable, scpu_ejtag_loc0, scpu_ejtag_loc1, + scpu_ejtag_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2, + vcpu_ejtag_loc0, vcpu_ejtag_loc1, vcpu_ejtag_loc2, secpu_ejtag_loc0, + secpu_ejtag_loc1, secpu_ejtag_loc2, aucpu_ejtag_loc0, aucpu_ejtag_loc1, + aucpu_ejtag_loc2, iso_tristate, dbg_out0, dbg_out1, standby_dbg, + spdif, arm_trace_debug_disable, arm_trace_debug_enable, + aucpu_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable, + scpu_ejtag_disable, secpu_ejtag_disable, vtc_dmic_loc_disable, + vtc_tdm_disable, vtc_i2si_disable, tdm_ai_disable, ai_disable, + spdif_disable, hif_disable, hif_enable, test_loop, pmic_pwrup ] + + drive-strength: + enum: [4, 8] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-push-pull: true + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + realtek,drive-strength-p: + description: | + Some of pins can be driven using the P-MOS and N-MOS transistor to + achieve finer adjustments. The block-diagram representation is as + follows: + VDD + | + ||--+ + +-----o|| P-MOS-FET + | ||--+ + IN --+ +----- out + | ||--+ + +------|| N-MOS-FET + ||--+ + | + GND + The driving strength of the P-MOS/N-MOS transistors impacts the + waveform's rise/fall times. Greater driving strength results in + shorter rise/fall times. Each P-MOS and N-MOS transistor offers + 8 configurable levels (0 to 7), with higher values indicating + greater driving strength, contributing to achieving the desired + speed. + + The realtek,drive-strength-p is used to control the driving strength + of the P-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,drive-strength-n: + description: | + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n + is used to control the driving strength of the N-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,duty-cycle: + description: | + An integer describing the level to adjust the output pulse width, it + provides a fixed nanosecond-level adjustment to the rising/falling + edges of an existing signal. It is used for Signal Integrity tuning + (adding/subtracting delay to fine-tune the high/low duration), rather + than generating a specific PWM frequency. + Valid arguments are described as below: + 0: 0ns + 2: + 0.25ns + 3: + 0.5ns + 4: -0.25ns + 5: -0.5ns + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 2, 3, 4, 5 ] + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4e000 { + compatible = "realtek,rtd1319d-pinctrl"; + reg = <0x4e000 0x130>; + + emmc-hs200-pins { + pins = "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + function = "emmc"; + realtek,drive-strength-p = <0x2>; + realtek,drive-strength-n = <0x2>; + }; + + i2c-0-pins { + pins = "gpio_12", + "gpio_13"; + function = "i2c0"; + drive-strength = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml new file mode 100644 index 000000000..e8ea1362b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml @@ -0,0 +1,189 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2023 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1619b-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1619B Pin Controller + +maintainers: + - TY Chang <tychang@realtek.com> + +description: + The Realtek DHC RTD1619B is a high-definition media processor SoC. The + RTD1619B pin controller is used to control pin function, pull up/down + resistor, drive strength, schmitt trigger and power source. + +properties: + compatible: + const: realtek,rtd1619b-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + items: + enum: [ gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, gpio_7, + gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, gpio_14, + gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, gpio_21, + gpio_22, gpio_23, usb_cc2, gpio_25, gpio_26, gpio_27, gpio_28, + gpio_29, gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, + hif_data, hif_en, hif_rdy, hif_clk, gpio_40, gpio_41, gpio_42, + gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, gpio_48, gpio_49, + gpio_50, usb_cc1, gpio_52, gpio_53, ir_rx, ur0_rx, ur0_tx, + gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, gpio_62, gpio_63, + gpio_64, gpio_65, gpio_66, gpio_67, gpio_68, gpio_69, gpio_70, + gpio_71, gpio_72, gpio_73, gpio_74, gpio_75, gpio_76, emmc_cmd, + spi_ce_n, spi_sck, spi_so, spi_si, emmc_rst_n, emmc_dd_sb, + emmc_clk, emmc_data_0, emmc_data_1, emmc_data_2, emmc_data_3, + emmc_data_4, emmc_data_5, emmc_data_6, emmc_data_7, ur2_loc, + gspi_loc, sdio_loc, hi_loc, hi_width, sf_en, arm_trace_dbg_en, + pwm_01_open_drain_en_loc0, pwm_23_open_drain_en_loc0, + pwm_01_open_drain_en_loc1, pwm_23_open_drain_en_loc1, + ejtag_acpu_loc, ejtag_vcpu_loc, ejtag_scpu_loc, dmic_loc, + iso_gspi_loc, ejtag_ve3_loc, ejtag_aucpu0_loc, ejtag_aucpu1_loc ] + + function: + enum: [ gpio, nf, nf_spi, spi, pmic, spdif, spdif_coaxial, spdif_optical_loc0, + spdif_optical_loc1, emmc_spi, emmc, sc1, uart0, uart1, uart2_loc0, uart2_loc1, + gspi_loc1, iso_gspi_loc1, i2c0, i2c1, i2c3, i2c4, i2c5, pwm0, pwm1, pwm2, + pwm3, etn_led, etn_phy, etn_clk, sc0, vfd, gspi_loc0, iso_gspi_loc0, pcie1, + pcie2, sd, sdio_loc0, sdio_loc1, hi, hi_m, dc_fan, pll_test_loc0, pll_test_loc1, + usb_cc1, usb_cc2, ir_rx, tdm_ai_loc0, tdm_ai_loc1, dmic_loc0, dmic_loc1, + ai_loc0, ai_loc1, tp0, tp1, ao, uart2_disable, gspi_disable, sdio_disable, + hi_loc_disable, hi_loc0, hi_width_disable, hi_width_1bit, vtc_i2si_loc0, + vtc_tdm_loc0, vtc_dmic_loc0, vtc_i2si_loc1, vtc_tdm_loc1, vtc_dmic_loc1, + vtc_i2so, ve3_ejtag_loc0, aucpu0_ejtag_loc0, aucpu1_ejtag_loc0, ve3_ejtag_loc1, + aucpu0_ejtag_loc1, aucpu1_ejtag_loc1, ve3_ejtag_loc2, aucpu0_ejtag_loc2, + aucpu1_ejtag_loc2, scpu_ejtag_loc0, acpu_ejtag_loc0, vcpu_ejtag_loc0, + scpu_ejtag_loc1, acpu_ejtag_loc1, vcpu_ejtag_loc1, scpu_ejtag_loc2, + acpu_ejtag_loc2, vcpu_ejtag_loc2, ve3_ejtag_disable, aucpu0_ejtag_disable, + aucpu1_ejtag_disable, acpu_ejtag_disable, vcpu_ejtag_disable, + scpu_ejtag_disable, iso_gspi_disable, sf_disable, sf_enable, + arm_trace_debug_disable, arm_trace_debug_enable, pwm_normal, pwm_open_drain, + standby_dbg, test_loop_dis ] + + drive-strength: + enum: [4, 8] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + drive-push-pull: true + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + realtek,drive-strength-p: + description: | + Some of pins can be driven using the P-MOS and N-MOS transistor to + achieve finer adjustments. The block-diagram representation is as + follows: + VDD + | + ||--+ + +-----o|| P-MOS-FET + | ||--+ + IN --+ +----- out + | ||--+ + +------|| N-MOS-FET + ||--+ + | + GND + The driving strength of the P-MOS/N-MOS transistors impacts the + waveform's rise/fall times. Greater driving strength results in + shorter rise/fall times. Each P-MOS and N-MOS transistor offers + 8 configurable levels (0 to 7), with higher values indicating + greater driving strength, contributing to achieving the desired + speed. + + The realtek,drive-strength-p is used to control the driving strength + of the P-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,drive-strength-n: + description: | + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n + is used to control the driving strength of the N-MOS output. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,duty-cycle: + description: | + An integer describing the level to adjust the output pulse width, it + provides a fixed nanosecond-level adjustment to the rising/falling + edges of an existing signal. It is used for Signal Integrity tuning + (adding/subtracting delay to fine-tune the high/low duration), rather + than generating a specific PWM frequency. + Valid arguments are described as below: + 0: 0ns + 2: + 0.25ns + 3: + 0.5ns + 4: -0.25ns + 5: -0.5ns + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 2, 3, 4, 5 ] + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4e000 { + compatible = "realtek,rtd1619b-pinctrl"; + reg = <0x4e000 0x130>; + + emmc-hs200-pins { + pins = "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + function = "emmc"; + realtek,drive-strength-p = <0x2>; + realtek,drive-strength-n = <0x2>; + }; + + i2c-0-pins { + pins = "gpio_12", + "gpio_13"; + function = "i2c0"; + drive-strength = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml new file mode 100644 index 000000000..9562a0437 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml @@ -0,0 +1,260 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025 Realtek Semiconductor Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/realtek,rtd1625-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC RTD1625 Pin Controller + +maintainers: + - Tzuyi Chang <tychang@realtek.com> + - Yu-Chun Lin <eleanor.lin@realtek.com> + +description: + The Realtek DHC RTD1625 is a high-definition media processor SoC. The + RTD1625 pin controller is used to control pin function, pull-up/down + resistors, drive strength, slew rate, Schmitt trigger, power source + (I/O output voltage), input threshold domain selection and a higher-VIL mode. + +properties: + compatible: + items: + - enum: + - realtek,rtd1625-iso-pinctrl + - realtek,rtd1625-main2-pinctrl + - realtek,rtd1625-isom-pinctrl + - realtek,rtd1625-ve4-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pins: + items: + enum: [gpio_0, gpio_1, gpio_2, gpio_3, gpio_4, gpio_5, gpio_6, + gpio_7, gpio_8, gpio_9, gpio_10, gpio_11, gpio_12, gpio_13, + gpio_14, gpio_15, gpio_16, gpio_17, gpio_18, gpio_19, gpio_20, + gpio_21, gpio_22, gpio_23, gpio_24, gpio_25, gpio_28, gpio_29, + gpio_30, gpio_31, gpio_32, gpio_33, gpio_34, gpio_35, gpio_40, + gpio_41, gpio_42, gpio_43, gpio_44, gpio_45, gpio_46, gpio_47, + gpio_48, gpio_49, gpio_50, gpio_51, gpio_52, gpio_53, gpio_54, + gpio_55, gpio_56, gpio_57, gpio_58, gpio_59, gpio_60, gpio_61, + gpio_62, gpio_63, gpio_64, gpio_65, gpio_66, gpio_67, gpio_80, + gpio_81, gpio_82, gpio_83, gpio_84, gpio_85, gpio_86, gpio_87, + gpio_88, gpio_89, gpio_90, gpio_91, gpio_92, gpio_93, gpio_94, + gpio_95, gpio_96, gpio_97, gpio_98, gpio_99, gpio_100, + gpio_101, gpio_102, gpio_103, gpio_104, gpio_105, gpio_106, + gpio_107, gpio_108, gpio_109, gpio_110, gpio_111, gpio_112, + gpio_128, gpio_129, gpio_130, gpio_131, gpio_132, gpio_133, + gpio_134, gpio_135, gpio_136, gpio_137, gpio_138, gpio_139, + gpio_140, gpio_141, gpio_142, gpio_143, gpio_144, gpio_145, + gpio_146, gpio_147, gpio_148, gpio_149, gpio_150, gpio_151, + gpio_152, gpio_153, gpio_154, gpio_155, gpio_156, gpio_157, + gpio_158, gpio_159, gpio_160, gpio_161, gpio_162, gpio_163, + gpio_164, gpio_165, ai_i2s1_loc, ao_i2s1_loc, arm_trace_dbg_en, + csi_vdsel, ejtag_acpu_loc, ejtag_aucpu0_loc, ejtag_aucpu1_loc, + ejtag_pcpu_loc, ejtag_scpu_loc, ejtag_ve2_loc, emmc_clk, + emmc_cmd, emmc_data_0, emmc_data_1, emmc_data_2, emmc_data_3, + emmc_data_4, emmc_data_5, emmc_data_6, emmc_data_7, + emmc_dd_sb, emmc_rst_n, etn_phy_loc, hif_clk, hif_data, + hif_en, hif_rdy, hi_width, i2c6_loc, ir_rx_loc, rgmii_vdsel, + sf_en, spdif_in_mode, spdif_loc, uart0_loc, usb_cc1, usb_cc2, + ve4_uart_loc] + + function: + enum: [gpio, ai_i2s0, ai_i2s2, ai_tdm0, ai_tdm1, ai_tdm2, ao_i2s0, + ao_i2s2, ao_tdm0, ao_tdm1, ao_tdm2, csi0, csi1, csi_1v2, csi_1v8, + csi_2v5, csi_3v3, dmic0, dmic1, dmic2, dptx_hpd, edptx_hdp, emmc, + gspi0, gspi1, gspi2, hi_width_1bit, hi_width_disable, i2c0, i2c1, + i2c3, i2c4, i2c5, i2c7, iso_tristate, pcie0, pcie1, pcm, pctrl, + pwm4, pwm5, pwm6, rgmii, rgmii_1v2, rgmii_1v8, rgmii_2v5, + rgmii_3v3, rmii, sd, sdio, sf_disable, sf_enable, + spdif_in_coaxial, spdif_in_gpio, spdif_out, spi, ts0, ts1, uart1, + uart2, uart3, uart4, uart5, uart6, uart7, uart8, uart9, uart10, + usb_cc1, usb_cc2, vi0_dtv, vi1_dtv, vtc_ao_i2s, vtc_dmic, + vtc_i2s, ai_i2s1_loc0, ai_i2s1_loc1, ao_i2s0_loc0, ao_i2s0_loc1, + ao_i2s1_loc0, ao_i2s1_loc1, ao_tdm1_loc0, ao_tdm1_loc1, + etn_led_loc0, etn_led_loc1, etn_phy_loc0, etn_phy_loc1, + i2c6_loc0, i2c6_loc1, ir_rx_loc0, ir_rx_loc1, pwm0_loc0, + pwm0_loc1, pwm0_loc2, pwm0_loc3, pwm1_loc0, pwm1_loc1, pwm2_loc0, + pwm2_loc1, pwm3_loc0, pwm3_loc1, spdif_loc0, spdif_loc1, + uart0_loc0, uart0_loc1, ve4_uart_loc0, ve4_uart_loc1, + ve4_uart_loc2, acpu_ejtag_loc0, acpu_ejtag_loc1, acpu_ejtag_loc2, + aucpu0_ejtag_loc0, aucpu0_ejtag_loc1, aucpu0_ejtag_loc2, + aucpu1_ejtag_loc0, aucpu1_ejtag_loc1, aucpu1_ejtag_loc2, + aupu0_ejtag_loc1, aupu1_ejtag_loc1, gpu_ejtag_loc0, + pcpu_ejtag_loc0, pcpu_ejtag_loc1, pcpu_ejtag_loc2, + scpu_ejtag_loc0, scpu_ejtag_loc1, scpu_ejtag_loc2, + ve2_ejtag_loc0, ve2_ejtag_loc1, ve2_ejtag_loc2, pll_test_loc0, + pll_test_loc1, dbg_out1, isom_dbg_out, arm_trace_debug_disable, + arm_trace_debug_enable] + + drive-strength: + enum: [4, 8] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + input-voltage-microvolt: + description: | + Select the input receiver voltage domain for the pin. + Valid arguments are: + - 1800000: 1.8V input logic level + - 3300000: 3.3V input logic level + enum: [1800000, 3300000] + + drive-push-pull: true + + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + slew-rate: + description: | + Valid arguments are described as below: + 1: ~1ns falling time + 10: ~10ns falling time + 20: ~20ns falling time + 30: ~30ns falling time + enum: [1, 10, 20, 30] + + realtek,drive-strength-p: + description: | + Some of pins can be driven using the P-MOS and N-MOS transistor to + achieve finer adjustments. The block-diagram representation is as + follows: + VDD + | + ||--+ + +-----o|| P-MOS-FET + | ||--+ + IN --+ +----- out + | ||--+ + +------|| N-MOS-FET + ||--+ + | + GND + The driving strength of the P-MOS/N-MOS transistors impacts the + waveform's rise/fall times. Greater driving strength results in + shorter rise/fall times. Each P-MOS and N-MOS transistor offers + 8 configurable levels (0 to 7), with higher values indicating + greater driving strength, contributing to achieving the desired + speed. + + The realtek,drive-strength-p is used to control the driving strength + of the P-MOS output. + + This value is not a simple count of transistors. Instead, it + represents a weighted configuration. There is a base driving + capability (even at value 0), and each bit adds a different weight to + the total strength. The resulting current is non-linear and varies + significantly based on the IO voltage (1.8V vs 3.3V) and the specific + pad group. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,drive-strength-n: + description: | + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n + is used to control the driving strength of the N-MOS output. + + This property uses the same weighted configuration logic where values + 0-7 represent non-linear strength adjustments rather than a transistor + count. + + Higher values indicate greater driving strength, resulting in shorter + fall times. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + realtek,duty-cycle: + description: | + An integer describing the level to adjust the output pulse width, it + provides a fixed nanosecond-level adjustment to the rising/falling + edges of an existing signal. It is used for Signal Integrity tuning + (adding/subtracting delay to fine-tune the high/low duration), rather + than generating a specific PWM frequency. + + Valid arguments are described as below: + 0: 0ns + 2: + 0.25ns + 3: + 0.5ns + 4: -0.25ns + 5: -0.5ns + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 2, 3, 4, 5] + + realtek,high-vil-microvolt: + description: | + The threshold value for the input receiver's LOW recognition (VIL). + + This property is used to address specific HDMI I2C compatibility + issues where some sinks (TVs) have weak pull-down capabilities and + fail to pull the bus voltage below the standard VIL threshold + (~0.7V). + + Setting this property to 1100000 (1.1V) enables a specialized input + receiver mode that raises the effective VIL threshold to improve + detection. + enum: [1100000] + + required: + - pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pinctrl@4e000 { + compatible = "realtek,rtd1625-iso-pinctrl"; + reg = <0x4e000 0x130>; + + emmc-hs200-pins { + pins = "emmc_clk", + "emmc_cmd", + "emmc_data_0", + "emmc_data_1", + "emmc_data_2", + "emmc_data_3", + "emmc_data_4", + "emmc_data_5", + "emmc_data_6", + "emmc_data_7"; + function = "emmc"; + realtek,drive-strength-p = <2>; + realtek,drive-strength-n = <2>; + }; + + i2c-0-pins { + pins = "gpio_12", + "gpio_13"; + function = "i2c0"; + drive-strength = <4>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml new file mode 100644 index 000000000..075f3abdf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -0,0 +1,196 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Pin Function Controller (GPIO and Pin Mux/Config) + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The Pin Function Controller (PFC) is a Pin Mux/Config controller. + On SH/R-Mobile SoCs it also acts as a GPIO controller. + +properties: + compatible: + enum: + - renesas,pfc-emev2 # EMMA Mobile EV2 + - renesas,pfc-r8a73a4 # R-Mobile APE6 + - renesas,pfc-r8a7740 # R-Mobile A1 + - renesas,pfc-r8a7742 # RZ/G1H + - renesas,pfc-r8a7743 # RZ/G1M + - renesas,pfc-r8a7744 # RZ/G1N + - renesas,pfc-r8a7745 # RZ/G1E + - renesas,pfc-r8a77470 # RZ/G1C + - renesas,pfc-r8a774a1 # RZ/G2M + - renesas,pfc-r8a774a3 # RZ/G2M v3.0 + - renesas,pfc-r8a774b1 # RZ/G2N + - renesas,pfc-r8a774c0 # RZ/G2E + - renesas,pfc-r8a774e1 # RZ/G2H + - renesas,pfc-r8a7778 # R-Car M1 + - renesas,pfc-r8a7779 # R-Car H1 + - renesas,pfc-r8a7790 # R-Car H2 + - renesas,pfc-r8a7791 # R-Car M2-W + - renesas,pfc-r8a7792 # R-Car V2H + - renesas,pfc-r8a7793 # R-Car M2-N + - renesas,pfc-r8a7794 # R-Car E2 + - renesas,pfc-r8a7795 # R-Car H3 + - renesas,pfc-r8a7796 # R-Car M3-W + - renesas,pfc-r8a77961 # R-Car M3-W+ + - renesas,pfc-r8a77965 # R-Car M3-N + - renesas,pfc-r8a77970 # R-Car V3M + - renesas,pfc-r8a77980 # R-Car V3H + - renesas,pfc-r8a77990 # R-Car E3 + - renesas,pfc-r8a77995 # R-Car D3 + - renesas,pfc-r8a779a0 # R-Car V3U + - renesas,pfc-r8a779f0 # R-Car S4-8 + - renesas,pfc-r8a779g0 # R-Car V4H + - renesas,pfc-r8a779h0 # R-Car V4M + - renesas,pfc-sh73a0 # SH-Mobile AG5 + + reg: + minItems: 1 + maxItems: 10 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 16 + + interrupts-extended: + minItems: 32 + maxItems: 64 + description: + Specify the interrupts associated with external IRQ pins on SoCs where + the PFC acts as a GPIO controller. It must contain one interrupt per + external IRQ, sorted by external IRQ number. + + power-domains: + maxItems: 1 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +if: + properties: + compatible: + enum: + - renesas,pfc-r8a73a4 + - renesas,pfc-r8a7740 + - renesas,pfc-sh73a0 +then: + required: + - interrupts-extended + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - power-domains + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + function: true + groups: true + pins: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: + enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values + power-source: + enum: [ 1800, 3300 ] + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + + additionalProperties: false + + - type: object + additionalProperties: + $ref: '#/additionalProperties/anyOf/0' + +examples: + - | + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a7740"; + reg = <0xe6050000 0x8000>, + <0xe605800c 0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 212>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + power-domains = <&pd_c5>; + + lcd0-mux-hog { + /* DBGMD/LCDC0/FSIA MUX */ + gpio-hog; + gpios = <176 0>; + output-high; + }; + }; + + - | + pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0xe6060000 0x50c>; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", + "PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2", + "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1"; + bias-pull-up; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml new file mode 100644 index 000000000..63993b205 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller. + Pin multiplexing and GPIO configuration are performed on a per-pin basis. + Each port supports up to 8 pins, each configurable for either GPIO (port mode) + or alternate function mode. Each pin supports function mode values ranging from + 0x0 to 0x2A, allowing selection from up to 43 different functions. + +properties: + compatible: + enum: + - renesas,r9a09g077-pinctrl # RZ/T2H + - renesas,r9a09g087-pinctrl # RZ/N2H + + reg: + minItems: 1 + items: + - description: Non-safety I/O Port base + - description: Safety I/O Port safety region base + - description: Safety I/O Port Non-safety region base + + reg-names: + minItems: 1 + items: + - const: nsr + - const: srs + - const: srn + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> + (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer + flag. Use the macros defined in include/dt-bindings/gpio/gpio.h. + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> + and the second cell is used to specify the flag. + E.g. "interrupts = <RZT2H_GPIO(8, 6) IRQ_TYPE_EDGE_FALLING>;" if P08_6 is + being used as an interrupt. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +definitions: + renesas-rzt2h-n2h-pins-node: + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + properties: + pinmux: + description: + Values are constructed from I/O port number, pin number, and + alternate function configuration number using the RZT2H_PORT_PINMUX() + helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>. + pins: true + phandle: true + input: true + input-enable: true + output-enable: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + slew-rate: + description: 0 is slow slew rate, 1 is fast slew rate + enum: [0, 1] + drive-strength-microamp: + description: | + Four discrete levels are supported (via registers DRCTLm), corresponding + to the following nominal values: + - 2500 (Low strength) + - 5000 (Middle strength) + - 9000 (High strength) + - 11800 (Ultra High strength) + enum: [2500, 5000, 9000, 11800] + oneOf: + - required: [pinmux] + - required: [pins] + additionalProperties: false + +patternProperties: + # Grouping nodes: allow multiple "-pins" subnodes within a "-group" + '.*-group$': + type: object + description: + Pin controller client devices can organize pin configuration entries into + grouping nodes ending in "-group". These group nodes may contain multiple + child nodes each ending in "-pins" to configure distinct sets of pins. + additionalProperties: false + patternProperties: + '-pins$': + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' + + # Standalone "-pins" nodes under client devices or groups + '-pins$': + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' + + '-hog$': + type: object + description: GPIO hog node + properties: + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + line-name: true + required: + - gpio-hog + - gpios + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - clocks + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> + #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> + + pinctrl@802c0000 { + compatible = "renesas,r9a09g077-pinctrl"; + reg = <0x802c0000 0x2000>, + <0x812c0000 0x2000>, + <0x802b0000 0x2000>; + reg-names = "nsr", "srs", "srn"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 288>; + interrupt-controller; + #interrupt-cells = <2>; + power-domains = <&cpg>; + + serial0-pins { + pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */ + <RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */ + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZT2H_GPIO(39, 2) 0>; + output-high; + line-name = "sd1_pwr_en"; + }; + + i2c0-pins { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + sd0-sd-group { + ctrl-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */ + }; + + data-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */ + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml new file mode 100644 index 000000000..8203c3c46 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/A1 combined Pin and GPIO controller + +maintainers: + - Jacopo Mondi <jacopo+renesas@jmondi.org> + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO + controller, named "Ports" in the hardware reference manual. + Pin multiplexing and GPIO configuration is performed on a per-pin basis + writing configuration values to per-port register sets. + Each "port" features up to 16 pins, each of them configurable for GPIO + function (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + oneOf: + - const: renesas,r7s72100-ports # RZ/A1H + - items: + - const: renesas,r7s72101-ports # RZ/A1M + - const: renesas,r7s72100-ports # fallback + - const: renesas,r7s72102-ports # RZ/A1L + + reg: + maxItems: 1 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +patternProperties: + "^gpio-[0-9]*$": + type: object + additionalProperties: false + + description: + Each port of the r7s72100 pin controller hardware is itself a GPIO + controller. + Different SoCs have different numbers of available pins per port, but + generally speaking, each of them can be configured in GPIO ("port") mode + on this hardware. + Describe GPIO controllers using sub-nodes with the following properties. + + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + A pin multiplexing sub-node describes how to configure a set of (or a + single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + A few alternate function require special pin configuration flags to be + supplied along with the alternate function configuration number. + The hardware reference manual specifies when a pin function requires + "software IO driven" mode to be specified. To do so use the generic + properties from the <include/linux/pinctrl/pinconf_generic.h> header + file to instruct the pin controller to perform the desired pin + configuration operation. + The hardware reference manual specifies when a pin has to be configured + to work in bi-directional mode and when the IO direction has to be + specified by software. Bi-directional pins must be managed by the pin + controller driver internally, while software driven IO direction has to + be explicitly selected when multiple options are available. + + properties: + pinmux: + description: | + Integer array representing pin number and pin multiplexing + configuration. + When a pin has to be configured in alternate function mode, use + this property to identify the pin by its global index, and provide + its alternate function configuration number along with it. + When multiple pins are required to be configured as part of the + same alternate function they shall be specified as members of the + same argument list of a single "pinmux" property. + Helper macros to ease assembling the pin index from its position + (port where it sits on and pin number) and alternate function + identifier are provided by the pin controller header file at: + <include/dt-bindings/pinctrl/r7s72100-pinctrl.h> + Integers values in "pinmux" argument list are assembled as: + ((PORT * 16 + PIN) | MUX_FUNC << 16) + + input-enable: true + output-enable: true + + required: + - pinmux + + additionalProperties: false + + - type: object + additionalProperties: + $ref: '#/additionalProperties/anyOf/0' + +examples: + - | + #include <dt-bindings/pinctrl/r7s72100-pinctrl.h> + pinctrl: pinctrl@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + /* + * A GPIO controller node, controlling 16 pins indexed from 0. + * The GPIO controller base in the global pin indexing space is pin + * 48, thus pins [0 - 15] on this controller map to pins [48 - 63] + * in the global pin indexing space. + */ + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + /* + * A serial communication interface with a TX output pin and an RX + * input pin. + * Pin #0 on port #3 is configured as alternate function #6. + * Pin #2 on port #3 is configured as alternate function #4. + */ + scif2_pins: serial2 { + pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>; + }; + + /* + * I2c master: both SDA and SCL pins need bi-directional operations + * Pin #4 on port #1 is configured as alternate function #1. + * Pin #5 on port #1 is configured as alternate function #1. + * Both need to work in bi-directional mode, the driver must manage + * this internally. + */ + i2c2_pins: i2c2 { + pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>; + }; + + /* + * Multi-function timer input and output compare pins. + */ + tioc0_pins: tioc0 { + /* + * Configure TIOC0A as software driven input + * Pin #0 on port #4 is configured as alternate function #2 + * with IO direction specified by software as input. + */ + tioc0_input_pins { + pinmux = <RZA1_PINMUX(4, 0, 2)>; + input-enable; + }; + + /* + * Configure TIOC0B as software driven output + * Pin #1 on port #4 is configured as alternate function #1 + * with IO direction specified by software as output. + */ + tioc0_output_pins { + pinmux = <RZA1_PINMUX(4, 1, 1)>; + output-enable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml new file mode 100644 index 000000000..8b8e4e1a0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/A2 combined Pin and GPIO controller + +maintainers: + - Chris Brandt <chris.brandt@renesas.com> + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO + controller. + Pin multiplexing and GPIO configuration is performed on a per-pin basis. + Each port features up to 8 pins, each of them configurable for GPIO function + (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + const: renesas,r7s9210-pinctrl # RZ/A2M + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZA2_PIN() helper macro in r7s9210-pinctrl.h. + E.g. "RZA2_PIN(PORT6, 0)" for P6_0. + + gpio-ranges: + maxItems: 1 + +additionalProperties: + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + The child nodes of the pin controller designate pins to be used for + specific peripheral functions or as GPIO. + + A pin multiplexing sub-node describes how to configure a set of + (or a single) pin in some desired alternate function mode. + The values for the pinmux properties are a combination of port name, + pin number and the desired function index. Use the RZA2_PINMUX macro + located in include/dt-bindings/pinctrl/r7s9210-pinctrl.h to easily + define these. + For assigning GPIO pins, use the macro RZA2_PIN also in + to express the desired port pin. + + properties: + pinmux: + description: + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZA2_PINMUX() + helper macro in r7s9210-pinctrl.h. + + required: + - pinmux + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +examples: + - | + #include <dt-bindings/pinctrl/r7s9210-pinctrl.h> + pinctrl: pinctrl@fcffe000 { + compatible = "renesas,r7s9210-pinctrl"; + reg = <0xfcffe000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 176>; + + /* Serial Console */ + scif4_pins: serial4 { + pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */ + <RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */ + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml new file mode 100644 index 000000000..00c05243b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -0,0 +1,226 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller + +maintainers: + - Geert Uytterhoeven <geert+renesas@glider.be> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and + GPIO controller. + Pin multiplexing and GPIO configuration is performed on a per-pin basis. + Each port features up to 8 pins, each of them configurable for GPIO function + (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five + - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a09g047-pinctrl # RZ/G3E + - renesas,r9a09g056-pinctrl # RZ/V2N + - renesas,r9a09g057-pinctrl # RZ/V2H(P) + + - items: + - enum: + - renesas,r9a07g054-pinctrl # RZ/V2L + - const: renesas,r9a07g044-pinctrl # RZ/G2{L,LC} fallback for RZ/V2L + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the + second cell represents consumer flag as mentioned in ../gpio/gpio.txt + E.g. "RZG2L_GPIO(39, 1)" for P39_1. + + gpio-ranges: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the + second cell is used to specify the flag. + E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is + being used as an interrupt. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + oneOf: + - items: + - description: GPIO_RSTN signal + - description: GPIO_PORT_RESETN signal + - description: GPIO_SPARE_RESETN signal + - items: + - description: PFC main reset + - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins + +additionalProperties: + anyOf: + - type: object + additionalProperties: false + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + pinmux: + description: + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZG2L_PORT_PINMUX() + helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>. + pins: true + drive-strength: + enum: [ 2, 4, 8, 12 ] + drive-strength-microamp: + enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700, + 5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000, + 10000 ] + output-impedance-ohms: + enum: [ 33, 50, 66, 100 ] + power-source: + description: I/O voltage in millivolt. + enum: [ 1800, 2500, 3300 ] + slew-rate: true + gpio-hog: true + gpios: true + input: true + input-enable: true + output-enable: true + output-high: true + output-low: true + line-name: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-schmitt-enable: true + input-schmitt-disable: true + drive-open-drain: true + drive-push-pull: true + renesas,output-impedance: + description: + Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this + property corresponds to register bit values that can be set in the PFC_IOLH_mn + register, which adjusts the drive strength value and is pin-dependent. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + - type: object + additionalProperties: + $ref: '#/additionalProperties/anyOf/0' + +allOf: + - $ref: pinctrl.yaml# + + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g047-pinctrl + - renesas,r9a09g056-pinctrl + - renesas,r9a09g057-pinctrl + then: + properties: + resets: + maxItems: 2 + else: + properties: + resets: + minItems: 3 + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupt-controller + - '#interrupt-cells' + - clocks + - power-domains + - resets + +examples: + - | + #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> + #include <dt-bindings/clock/r9a07g044-cpg.h> + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g044-pinctrl"; + reg = <0x11030000 0x10000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 392>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; + resets = <&cpg R9A07G044_GPIO_RSTN>, + <&cpg R9A07G044_GPIO_PORT_RESETN>, + <&cpg R9A07G044_GPIO_SPARE_RESETN>; + power-domains = <&cpg>; + + scif0_pins: serial0 { + pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */ + <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */ + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZG2L_GPIO(39, 2) 0>; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_mux { + pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */ + <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */ + power-source = <3300>; + }; + + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml new file mode 100644 index 000000000..ab2d456c9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G2L Port Output Enable for GPT (POEG) + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be + disabled by using the port output enabling function for the GPT (POEG). + Specifically, either of the following ways can be used. + * Input level detection of the GTETRGA to GTETRGD pins. + * Output-disable request from the GPT. + * SSF bit setting(ie, by setting POEGGn.SSF to 1) + + The state of the GTIOCxA and the GTIOCxB pins when the output is disabled, + are controlled by the GPT module. + +properties: + compatible: + items: + - enum: + - renesas,r9a07g044-poeg # RZ/G2{L,LC} + - renesas,r9a07g054-poeg # RZ/V2L + - const: renesas,rzg2l-poeg + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + renesas,gpt: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to gpt instance that serves the pwm operation. + + renesas,poeg-id: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + description: | + POEG group index. Valid values are: + <0> : POEG group A + <1> : POEG group B + <2> : POEG group C + <3> : POEG group D + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + - resets + - renesas,poeg-id + - renesas,gpt + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a07g044-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + poeggd: poeg@10049400 { + compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg"; + reg = <0x10049400 0x400>; + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_POEG_D_RST>; + renesas,poeg-id = <3>; + renesas,gpt = <&gpt>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml new file mode 100644 index 000000000..aa882b5bf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Pin Controller + +maintainers: + - Fabrizio Castro <fabrizio.castro.jz@renesas.com> + - Geert Uytterhoeven <geert+renesas@glider.be> + +properties: + compatible: + items: + - const: renesas,r9a06g032-pinctrl # RZ/N1D + - const: renesas,rzn1-pinctrl # Generic RZ/N1 + + reg: + items: + - description: GPIO Multiplexing Level1 Register Block + - description: GPIO Multiplexing Level2 Register Block + + clocks: + maxItems: 1 + + clock-names: + const: bus + description: + The bus clock, sometimes described as pclk, for register accesses. + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + A pin multiplexing sub-node describes how to configure a set of (or a + single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + + properties: + pinmux: + description: | + Integer array representing pin number and pin multiplexing + configuration. + When a pin has to be configured in alternate function mode, use + this property to identify the pin by its global index, and provide + its alternate function configuration number along with it. + When multiple pins are required to be configured as part of the + same alternate function they shall be specified as members of the + same argument list of a single "pinmux" property. + Integers values in the "pinmux" argument list are assembled as: + (PIN | MUX_FUNC << 8) + where PIN directly corresponds to the pl_gpio pin number and + MUX_FUNC is one of the alternate function identifiers defined in: + <include/dt-bindings/pinctrl/rzn1-pinctrl.h> + These identifiers collapse the IO Multiplex Configuration Level 1 + and Level 2 numbers that are detailed in the hardware reference + manual into a single number. The identifiers for Level 2 are simply + offset by 10. Additional identifiers are provided to specify the + MDIO source peripheral. + + bias-disable: true + bias-pull-up: + description: Pull up the pin with 50 kOhm + bias-pull-down: + description: Pull down the pin with 50 kOhm + bias-high-impedance: true + drive-strength: + enum: [ 4, 6, 8, 12 ] + + required: + - pinmux + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + + - type: object + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + #include <dt-bindings/pinctrl/rzn1-pinctrl.h> + pinctrl: pinctrl@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + + /* + * A serial communication interface with a TX output pin and an RX + * input pin. + */ + pins_uart0: pins_uart0 { + pinmux = < + RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ + RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ + >; + }; + + /* + * Set the pull-up on the RXD pin of the UART. + */ + pins_uart0_alt: pins_uart0_alt { + pinmux = <RZN1_PINMUX(103, RZN1_FUNC_UART0_I)>; + + pins_uart6_rx { + pinmux = <RZN1_PINMUX(104, RZN1_FUNC_UART0_I)>; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml new file mode 100644 index 000000000..88b2fa5e6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzv2m-pinctrl.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M combined Pin and GPIO controller + +maintainers: + - Fabrizio Castro <fabrizio.castro.jz@renesas.com> + - Geert Uytterhoeven <geert+renesas@glider.be> + +description: + The Renesas RZ/V2M SoC features a combined Pin and GPIO controller. + Pin multiplexing and GPIO configuration is performed on a per-pin basis. + Each port features up to 16 pins, each of them configurable for GPIO function + (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + const: renesas,r9a09g011-pinctrl # RZ/V2M + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZV2M_GPIO() helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h> and the + second cell represents consumer flag as mentioned in ../gpio/gpio.txt + E.g. "RZV2M_GPIO(8, 1)" for P8_1. + + gpio-ranges: + maxItems: 1 + + interrupts: + description: INEXINT[0..38] corresponding to individual pin inputs. + maxItems: 39 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +additionalProperties: + anyOf: + - type: object + additionalProperties: false + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + pinmux: + description: + Values are constructed from GPIO port number, pin number, and + alternate function configuration number using the RZV2M_PORT_PINMUX() + helper macro in <dt-bindings/pinctrl/rzv2m-pinctrl.h>. + pins: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength-microamp: + # Superset of supported values + enum: [ 1600, 1800, 2000, 3200, 3800, 4000, 6400, 7800, 8000, + 9000, 9600, 11000, 12000, 13000, 18000 ] + slew-rate: + description: 0 is slow slew rate, 1 is fast slew rate + enum: [ 0, 1 ] + gpio-hog: true + gpios: true + output-high: true + output-low: true + line-name: true + + - type: object + additionalProperties: + $ref: '#/additionalProperties/anyOf/0' + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - interrupts + - clocks + - power-domains + - resets + +examples: + - | + #include <dt-bindings/pinctrl/rzv2m-pinctrl.h> + #include <dt-bindings/clock/r9a09g011-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl: pinctrl@b6250000 { + compatible = "renesas,r9a09g011-pinctrl"; + reg = <0xb6250000 0x800>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 352>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>; + resets = <&cpg R9A09G011_PFC_PRESETN>; + power-domains = <&cpg>; + + i2c2_pins: i2c2 { + pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */ + <RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */ + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml new file mode 100644 index 000000000..9b3cbeb54 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -0,0 +1,195 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Pinmux Controller + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +description: | + The Rockchip Pinmux Controller enables the IC to share one PAD + to several functional blocks. The sharing is done by multiplexing + the PAD input/output signals. For each PAD there are several muxing + options with option 0 being used as a GPIO. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The Rockchip pin configuration node is a node of a group of pins which can be + used for a specific device or function. This node represents both mux and + config of the pins in that group. The 'pins' selects the function mode + (also named pin mode) this pin can work on and the 'config' configures + various pad settings such as pull-up, etc. + + The pins are grouped into up to 9 individual pin banks which need to be + defined as gpio sub-nodes of the pinmux controller. + +properties: + compatible: + enum: + - rockchip,px30-pinctrl + - rockchip,rk2928-pinctrl + - rockchip,rk3036-pinctrl + - rockchip,rk3066a-pinctrl + - rockchip,rk3066b-pinctrl + - rockchip,rk3128-pinctrl + - rockchip,rk3188-pinctrl + - rockchip,rk3228-pinctrl + - rockchip,rk3288-pinctrl + - rockchip,rk3308-pinctrl + - rockchip,rk3328-pinctrl + - rockchip,rk3368-pinctrl + - rockchip,rk3399-pinctrl + - rockchip,rk3506-pinctrl + - rockchip,rk3528-pinctrl + - rockchip,rk3562-pinctrl + - rockchip,rk3568-pinctrl + - rockchip,rk3576-pinctrl + - rockchip,rk3588-pinctrl + - rockchip,rv1103b-pinctrl + - rockchip,rv1108-pinctrl + - rockchip,rv1126-pinctrl + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the GRF registers. + + rockchip,pmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the PMU registers, + as some SoCs carry parts of the iomux controller registers there. + Required for at least rk3188 and rk3288. On the rk3368 this should + point to the PMUGRF syscon. + + "#address-cells": + enum: [1, 2] + + "#size-cells": + enum: [1, 2] + + ranges: true + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - rockchip,grf + +patternProperties: + "gpio@[0-9a-f]+$": + type: object + + $ref: /schemas/gpio/rockchip,gpio-bank.yaml# + deprecated: true + + unevaluatedProperties: false + + "pcfg-[a-z0-9-]+$": + type: object + properties: + bias-disable: true + + bias-pull-down: true + + bias-pull-pin-default: true + + bias-pull-up: true + + drive-strength: + minimum: 0 + maximum: 20 + + input-enable: true + + input-schmitt-enable: true + + output-high: true + + output-low: true + + additionalProperties: false + +additionalProperties: + type: object + additionalProperties: + type: object + additionalProperties: false + + properties: + rockchip,pins: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + items: + items: + - minimum: 0 + maximum: 8 + description: + Pin bank. + - minimum: 0 + maximum: 31 + description: + Pin bank index. + - minimum: 0 + maximum: 14 + description: + Mux 0 means GPIO and mux 1 to N means + the specific device function. + - description: + The phandle of a node contains the generic pinconfig options + to use as described in pinctrl-bindings.txt. + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/rockchip.h> + + pinctrl: pinctrl { + compatible = "rockchip,rk3066a-pinctrl"; + rockchip,grf = <&grf>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@20034000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20034000 0x100>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk_gates8 9>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; + }; + }; + }; + + uart2: serial@20064000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20064000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mux_uart2>; + pinctrl-0 = <&uart2_xfer>; + pinctrl-names = "default"; + reg-io-width = <1>; + reg-shift = <2>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml new file mode 100644 index 000000000..8cf3c47ab --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-gpio-bank.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller. + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + '#gpio-cells': + const: 2 + + gpio-controller: true + + '#interrupt-cells': + description: + For GPIO banks supporting external GPIO interrupts or external wake-up + interrupts. + const: 2 + + interrupt-controller: + description: + For GPIO banks supporting external GPIO interrupts or external wake-up + interrupts. + + interrupts: + description: + For GPIO banks supporting direct external wake-up interrupts (without + multiplexing). Number of interrupts must match number of wake-up capable + pins of this bank. + minItems: 1 + maxItems: 8 + +required: + - '#gpio-cells' + - gpio-controller + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml new file mode 100644 index 000000000..f796f27bf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-pins-cfg.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller. + + The values used for config properties should be derived from the hardware + manual and these values are programmed as-is into the pin pull up/down and + driver strength register of the pin-controller. + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + samsung,pins: + description: | + List of pins to configure. For initial and sleep states, the maximum + number is one pin. In other cases there is no upper limit. + + The pins should use lowercase names matching hardware manual, e.g. for + GPA0 bank: gpa0-0, gpa0-1, gpa0-2. + $ref: /schemas/types.yaml#/definitions/string-array + + samsung,pin-function: + description: | + The pin function selection that should be applied on the pins listed in the + child node is specified using the "samsung,pin-function" property. The value + of this property that should be applied to each of the pins listed in the + "samsung,pins" property should be picked from the hardware manual of the SoC + for the specified pin group. This property is optional in the child node if + no specific function selection is desired for the pins listed in the child + node. The value of this property is used as-is to program the pin-controller + function selector register of the pin-bank. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + samsung,pin-drv: + description: Drive strength configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + samsung,pin-pud: + description: Pull up/down configuration. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + samsung,pin-val: + description: Initial value of pin output buffer. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + + samsung,pin-con-pdn: + description: Function in power down mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + + samsung,pin-pud-pdn: + description: Pull up/down configuration in power down mode. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + +required: + - samsung,pins + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml new file mode 100644 index 000000000..2b88f25e8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -0,0 +1,116 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller. + For S3C24xx, S3C64xx, S5PV210 and Exynos4210 compatible wake-up interrupt + controllers, only one pin-controller device node can include external wake-up + interrupts child node (in other words, only one External wake-up interrupts + pin-controller is supported). + For newer controllers, multiple pin-controller device node can include + external wake-up interrupts child node. + + See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for + additional information and example. + +properties: + compatible: + oneOf: + - enum: + - samsung,s3c64xx-wakeup-eint + - samsung,s5pv210-wakeup-eint + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + - samsung,exynosautov920-wakeup-eint + - items: + - enum: + - samsung,exynos5433-wakeup-eint + - samsung,exynos7870-wakeup-eint + - samsung,exynos7885-wakeup-eint + - samsung,exynos850-wakeup-eint + - samsung,exynos8890-wakeup-eint + - samsung,exynos8895-wakeup-eint + - const: samsung,exynos7-wakeup-eint + - items: + - enum: + - google,gs101-wakeup-eint + - samsung,exynos2200-wakeup-eint + - samsung,exynos9610-wakeup-eint + - samsung,exynos9810-wakeup-eint + - samsung,exynos990-wakeup-eint + - samsung,exynosautov9-wakeup-eint + - const: samsung,exynos850-wakeup-eint + - const: samsung,exynos7-wakeup-eint + + interrupts: + description: + Interrupt used by multiplexed external wake-up interrupts. + minItems: 1 + maxItems: 4 + +required: + - compatible + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,s3c64xx-wakeup-eint + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 + required: + - interrupts + + - if: + properties: + compatible: + oneOf: + # Match without "contains", to skip newer variants which are still + # compatible with samsung,exynos7-wakeup-eint + - enum: + - samsung,exynos4210-wakeup-eint + - samsung,exynos7-wakeup-eint + - samsung,s5pv210-wakeup-eint + - contains: + enum: + - samsung,exynos5433-wakeup-eint + - samsung,exynos7870-wakeup-eint + - samsung,exynos7885-wakeup-eint + - samsung,exynos8895-wakeup-eint + then: + properties: + interrupts: + minItems: 1 + maxItems: 1 + required: + - interrupts + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-wakeup-eint + - samsung,exynosautov920-wakeup-eint + then: + properties: + interrupts: false + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml new file mode 100644 index 000000000..7b006009c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -0,0 +1,418 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S3C/S5P/Exynos SoC pin controller + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + - Sylwester Nawrocki <s.nawrocki@samsung.com> + - Tomasz Figa <tomasz.figa@gmail.com> + +description: | + This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin + controller. + + All the pin controller nodes should be represented in the aliases node using + the following format 'pinctrl{n}' where n is a unique number for the alias. + + The controller supports three types of interrupts:: + - External GPIO interrupts (see interrupts property in pin controller node); + + - External wake-up interrupts - multiplexed (capable of waking up the system + see interrupts property in external wake-up interrupt controller node - + samsung,pinctrl-wakeup-interrupt.yaml); + + - External wake-up interrupts - direct (capable of waking up the system, see + interrupts property in every bank of pin controller with external wake-up + interrupt controller - samsung,pinctrl-gpio-bank.yaml). + +properties: + $nodename: + pattern: "^pinctrl(@.*)?" + + compatible: + enum: + - axis,artpec8-pinctrl + - axis,artpec9-pinctrl + - google,gs101-pinctrl + - samsung,s3c64xx-pinctrl + - samsung,s5pv210-pinctrl + - samsung,exynos2200-pinctrl + - samsung,exynos3250-pinctrl + - samsung,exynos4210-pinctrl + - samsung,exynos4x12-pinctrl + - samsung,exynos5250-pinctrl + - samsung,exynos5260-pinctrl + - samsung,exynos5410-pinctrl + - samsung,exynos5420-pinctrl + - samsung,exynos5433-pinctrl + - samsung,exynos7-pinctrl + - samsung,exynos7870-pinctrl + - samsung,exynos7885-pinctrl + - samsung,exynos850-pinctrl + - samsung,exynos8890-pinctrl + - samsung,exynos8895-pinctrl + - samsung,exynos9610-pinctrl + - samsung,exynos9810-pinctrl + - samsung,exynos990-pinctrl + - samsung,exynosautov9-pinctrl + - samsung,exynosautov920-pinctrl + - tesla,fsd-pinctrl + + interrupts: + description: + Required for GPIO banks supporting external GPIO interrupts. + maxItems: 1 + + power-domains: + maxItems: 1 + + reg: + description: + Second base address of the pin controller if the specific registers of + the pin controller are separated into the different base address. + Only certain banks of certain pin controller might need it. + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + wakeup-interrupt-controller: + $ref: samsung,pinctrl-wakeup-interrupt.yaml + +patternProperties: + "^[a-z]+[0-9]*-gpio-bank$": + description: + Pin banks of the controller are represented by child nodes of the + controller node. Bank name is taken from name of the node. + $ref: samsung,pinctrl-gpio-bank.yaml + + "^[a-z0-9-]+-pins$": + oneOf: + - $ref: samsung,pinctrl-pins-cfg.yaml + required: + - samsung,pins + - type: object + patternProperties: + "^[a-z0-9-]+-pins$": + $ref: samsung,pinctrl-pins-cfg.yaml + + additionalProperties: false + + "^(initial|sleep)-state$": + type: object + additionalProperties: false + + patternProperties: + "^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$": + $ref: samsung,pinctrl-pins-cfg.yaml + + properties: + samsung,pins: + description: See samsung,pinctrl-pins-cfg.yaml + $ref: /schemas/types.yaml#/definitions/string-array + maxItems: 1 + + required: + - samsung,pins + + unevaluatedProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + enum: + - google,gs101-pinctrl + - samsung,exynos8890-pinctrl + then: + required: + - clocks + - clock-names + else: + properties: + clocks: false + clock-names: false + + - if: + properties: + compatible: + contains: + const: samsung,exynos5433-pinctrl + then: + properties: + reg: + minItems: 1 + maxItems: 2 + else: + properties: + reg: + minItems: 1 + maxItems: 1 + +additionalProperties: false + +examples: + - | + pinctrl@7f008000 { + compatible = "samsung,s3c64xx-pinctrl"; + reg = <0x7f008000 0x1000>; + interrupt-parent = <&vic1>; + interrupts = <21>; + + wakeup-interrupt-controller { + compatible = "samsung,s3c64xx-wakeup-eint"; + interrupts-extended = <&vic0 0>, + <&vic0 1>, + <&vic1 0>, + <&vic1 1>; + }; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpa-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + uart0-data-pins { + samsung,pins = "gpa-0", "gpa-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + }; + + // ... + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@11400000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + uart0-data-pins { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + // ... + + sleep0: sleep-state { + gpa0-0-pin { + samsung,pins = "gpa0-0"; + samsung,pin-con-pdn = <2>; + samsung,pin-pud-pdn = <0>; + }; + + gpa0-1-pin { + samsung,pins = "gpa0-1"; + samsung,pin-con-pdn = <0>; + samsung,pin-pud-pdn = <0>; + }; + + // ... + }; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@11000000 { + compatible = "samsung,exynos4210-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpj0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* Pin bank without external interrupts */ + gpy0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + }; + + /* Pin bank with external direct wake-up interrupts */ + gpx0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + }; + + // ... + + sd0-clk-pins { + samsung,pins = "gpk0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd4-bus-width8-pins { + part-1-pins { + samsung,pins = "gpk0-3", "gpk0-4", + "gpk0-5", "gpk0-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + part-2-pins { + samsung,pins = "gpk1-3", "gpk1-4", + "gpk1-5", "gpk1-6"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + }; + + // ... + + otg-gp-pins { + samsung,pins = "gpx3-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + samsung,pin-val = <0>; + }; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@10580000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x10580000 0x1a20>, <0x11090000 0x100>; + + pinctrl-names = "default"; + pinctrl-0 = <&initial_alive>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos5433-wakeup-eint", + "samsung,exynos7-wakeup-eint"; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* Pin bank with external direct wake-up interrupts */ + gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + }; + + // ... + + te-irq-pins { + samsung,pins = "gpf1-3"; + samsung,pin-function = <0xf>; + }; + + // .. + + initial_alive: initial-state { + gpa0-0-pin { + samsung,pins = "gpa0-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + // ... + }; + }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pinctrl@114b0000 { + compatible = "samsung,exynos5433-pinctrl"; + reg = <0x114b0000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_aud>; + + /* Pin bank with external GPIO or muxed external wake-up interrupts */ + gpz0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // ... + + i2s0-bus-pins { + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3", + "gpz0-4", "gpz0-5", "gpz0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + // ... + }; diff --git a/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml new file mode 100644 index 000000000..39d7dad33 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/semtech,sx1501q.yaml @@ -0,0 +1,251 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2022 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/semtech,sx1501q.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Semtech SX150x GPIO expander + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + enum: + - semtech,sx1501q + - semtech,sx1502q + - semtech,sx1503q + - semtech,sx1504q + - semtech,sx1505q + - semtech,sx1506q + - semtech,sx1507q + - semtech,sx1508q + - semtech,sx1509q + + reg: + maxItems: 1 + + gpio-line-names: + minItems: 5 + maxItems: 17 + + interrupts: + maxItems: 1 + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + + '#gpio-cells': + const: 2 + + gpio-controller: true + + semtech,probe-reset: + description: Will trigger a reset of the GPIO expander on probe + type: boolean + +patternProperties: + '-cfg$': + type: object + properties: + pins: true + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-push-pull: true + output-low: true + output-high: true + drive-open-drain: true + + required: + - pins + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + - if: + properties: + pins: + contains: + const: oscio + then: + properties: + bias-disable: false + bias-pull-up: false + bias-pull-down: false + bias-pull-pin-default: false + drive-open-drain: false + + additionalProperties: false + +required: + - compatible + - reg + - '#gpio-cells' + - gpio-controller + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1501q + - semtech,sx1504q + - semtech,sx1507q + then: + properties: + gpio-line-names: + minItems: 5 + maxItems: 5 + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1502q + - semtech,sx1505q + - semtech,sx1508q + then: + properties: + gpio-line-names: + minItems: 9 + maxItems: 9 + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1503q + - semtech,sx1506q + - semtech,sx1509q + then: + properties: + gpio-line-names: + minItems: 17 + maxItems: 17 + - if: + not: + properties: + compatible: + contains: + enum: + - semtech,sx1507q + - semtech,sx1508q + - semtech,sx1509q + then: + properties: + semtech,probe-reset: false + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1501q + - semtech,sx1504q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^gpio[0-3]$' + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1502q + - semtech,sx1505q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^gpio[0-7]$' + - if: + properties: + compatible: + contains: + enum: + - semtech,sx1503q + - semtech,sx1506q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(gpio[0-9]|gpio1[0-5])$' + - if: + properties: + compatible: + contains: + const: semtech,sx1507q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-3])$' + - if: + properties: + compatible: + contains: + const: semtech,sx1508q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-7])$' + - if: + properties: + compatible: + contains: + const: semtech,sx1509q + then: + patternProperties: + '-cfg$': + properties: + pins: + items: + pattern: '^(oscio|gpio[0-9]|gpio1[0-5])$' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + i2c@1000 { + reg = <0x1000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl@20 { + compatible = "semtech,sx1501q"; + reg = <0x20>; + + #gpio-cells = <2>; + #interrupt-cells = <2>; + + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + interrupt-controller; + + gpio1-cfg { + pins = "gpio1"; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml new file mode 100644 index 000000000..880da721a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/socionext,uniphier-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UniPhier SoCs pin controller + +maintainers: + - Masahiro Yamada <yamada.masahiro@socionext.com> + +properties: + compatible: + enum: + - socionext,uniphier-ld4-pinctrl + - socionext,uniphier-pro4-pinctrl + - socionext,uniphier-sld8-pinctrl + - socionext,uniphier-pro5-pinctrl + - socionext,uniphier-pxs2-pinctrl + - socionext,uniphier-ld6b-pinctrl + - socionext,uniphier-ld11-pinctrl + - socionext,uniphier-ld20-pinctrl + - socionext,uniphier-pxs3-pinctrl + - socionext,uniphier-nx1-pinctrl + +additionalProperties: + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + function: true + groups: true + pins: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-strength: true + + additionalProperties: + type: object + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + function: true + groups: true + pins: true + bias-pull-up: true + bias-pull-down: true + bias-pull-pin-default: true + drive-strength: true + + unevaluatedProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +examples: + - | + // The UniPhier pinctrl should be a subnode of a "syscon" compatible node. + + pinctrl { + compatible = "socionext,uniphier-ld20-pinctrl"; + + pinctrl_ether_rgmii: ether-rgmii { + groups = "ether_rgmii"; + function = "ether_rgmii"; + + tx { + pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1", + "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL"; + drive-strength = <9>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml new file mode 100644 index 000000000..feb4785a3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo CV1800 Pin Controller + +maintainers: + - Inochi Amaoto <inochiama@outlook.com> + +properties: + compatible: + enum: + - sophgo,cv1800b-pinctrl + - sophgo,cv1812h-pinctrl + - sophgo,sg2000-pinctrl + - sophgo,sg2002-pinctrl + + reg: + items: + - description: pinctrl for system domain + - description: pinctrl for rtc domain + + reg-names: + items: + - const: sys + - const: rtc + + resets: + maxItems: 1 + +patternProperties: + '-cfg$': + type: object + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + additionalProperties: false + + patternProperties: + '-pins$': + type: object + description: | + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias, input + enable/disable, input schmitt trigger, slew-rate, drive strength + and bus hold state. In addition, all pins in the same subnode + should have the same power domain. For configuration detail, + refer to https://github.com/sophgo/sophgo-doc/. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the PINMUX or PINMUX2 + macro. + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + description: typical current when output high level. + + input-schmitt-microvolt: + description: typical threshold for schmitt trigger. + + power-source: + description: power supplies at X mV. + enum: [ 1800, 3300 ] + + slew-rate: + description: slew rate for output buffer (0 is fast, 1 is slow) + enum: [ 0, 1 ] + + bias-bus-hold: true + + required: + - pinmux + - power-source + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-cv1800b.h> + + pinctrl@3001000 { + compatible = "sophgo,cv1800b-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = <PINMUX(PIN_UART0_TX, 0)>, + <PINMUX(PIN_UART0_RX, 0)>; + bias-pull-up; + drive-strength-microamp = <10800>; + input-schmitt-microvolt = <0>; + power-source = <3300>; + slew-rate = <0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/sophgo,sg2042-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sophgo,sg2042-pinctrl.yaml new file mode 100644 index 000000000..924dfe140 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sophgo,sg2042-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sophgo,sg2042-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Pin Controller + +maintainers: + - Inochi Amaoto <inochiama@outlook.com> + +properties: + compatible: + enum: + - sophgo,sg2042-pinctrl + - sophgo,sg2044-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-cfg$': + type: object + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + additionalProperties: false + + patternProperties: + '-pins$': + type: object + description: | + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias input + enable/disable, input schmitt trigger enable, drive strength + output enable/disable state. For configuration detail, + refer to https://github.com/sophgo/sophgo-doc/. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the PINMUX macro. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + description: typical current when output low level. + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: sophgo,sg2042-pinctrl + then: + patternProperties: + '-cfg$': + patternProperties: + '-pins$': + properties: + drive-strength-microamp: + enum: [ 5400, 8100, 10700, 13400, + 16100, 18800, 21400, 24100, + 26800, 29400, 32100, 34800, + 37400, 40100, 42800, 45400 ] + + - if: + properties: + compatible: + contains: + const: sophgo,sg2044-pinctrl + then: + patternProperties: + '-cfg$': + patternProperties: + '-pins$': + properties: + drive-strength-microamp: + enum: [ 3200, 6400, 9600, 12700, + 15900, 19100, 22200, 25300, + 29500, 32700, 35900, 39000, + 42000, 45200, 48300, 51400] + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-sg2042.h> + + pinctrl@30011000 { + compatible = "sophgo,sg2042-pinctrl"; + reg = <30011000 0x1000>; + + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = <PINMUX(PIN_UART0_TX, 0)>, + <PINMUX(PIN_UART0_RX, 0)>; + bias-pull-up; + drive-strength-microamp = <13400>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml new file mode 100644 index 000000000..3e734aeb0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/spacemit,k1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC Pin Controller + +maintainers: + - Yixun Lan <dlan@gentoo.org> + +properties: + compatible: + enum: + - spacemit,k1-pinctrl + - spacemit,k3-pinctrl + + reg: + items: + - description: pinctrl io memory base + + clocks: + items: + - description: Functional Clock + - description: Bus Clock + + clock-names: + items: + - const: func + - const: bus + + resets: + maxItems: 1 + + spacemit,apbc: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to syscon that access the protected register + +patternProperties: + '-cfg$': + type: object + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + patternProperties: + '-pins$': + type: object + additionalProperties: false + + description: + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias pull, + drive strength, input schmitt trigger, slew rate, power source. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the K1_PADCONF macro to + construct the value. + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: + description: | + typical value for selecting bias pull up or strong pull up. + 0: normal bias pull up + 1: strong bias pull up + enum: [ 0, 1 ] + + drive-strength: + description: + typical current (in mA) when the output at high level. + anyOf: + - enum: [ 11, 21, 32, 42 ] + description: For K1 SoC, 1.8V voltage output + + - enum: [ 7, 10, 13, 16, 19, 23, 26, 29 ] + description: For K1 SoC, 3.3V voltage output + + - enum: [ 2, 4, 6, 7, 9, 11, 13, 14, 21, 23, 25, 26, 28, 30, 31, 33 ] + description: For K3 SoC, 1.8V voltage output + + - enum: [ 3, 5, 7, 9, 11, 13, 15, 17, 25, 27, 29, 31, 33, 35, 37, 38 ] + description: For K3 SoC, 3.3V voltage output + + input-schmitt: + description: | + typical threshold for schmitt trigger. + 0: buffer mode + 1: trigger mode + 2, 3: trigger mode + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + + power-source: + description: external power supplies at 1.8v or 3.3v. + enum: [ 1800, 3300 ] + + slew-rate: + description: | + slew rate for output buffer. + 0: disable it + 1: enable it (via bundled value from drive strength) + 2: slow speed 0 + 3: slow speed 1 + 4: medium speed + 5: fast speed + enum: [ 0, 1, 2, 3, 4, 5 ] + + required: + - pinmux + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #define K1_PADCONF(pin, func) (((pin) << 16) | (func)) + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x400>; + clocks = <&syscon_apbc 42>, + <&syscon_apbc 94>; + clock-names = "func", "bus"; + spacemit,apbc = <&syscon_apbc>; + + uart0_2_cfg: uart0-2-cfg { + uart0-2-pins { + pinmux = <K1_PADCONF(68, 2)>, + <K1_PADCONF(69, 2)>; + + bias-pull-up = <0>; + drive-strength = <32>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.yaml new file mode 100644 index 000000000..59d23eb8a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sprd,sc9860-pinctrl.yaml @@ -0,0 +1,199 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sprd,sc9860-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Spreadtrum SC9860 Pin Controller + +maintainers: + - Baolin Wang <baolin.wang@linux.alibaba.com> + +description: > + The Spreadtrum pin controller are organized in 3 blocks (types). + + The first block comprises some global control registers, and each + register contains several bit fields with one bit or several bits + to configure for some global common configuration, such as domain + pad driving level, system control select and so on ("domain pad + driving level": One pin can output 3.0v or 1.8v, depending on the + related domain pad driving selection, if the related domain pad + select 3.0v, then the pin can output 3.0v. "system control" is used + to choose one function (like: UART0) for which system, since we + have several systems (AP/CP/CM4) on one SoC.). + + There are too much various configuration that we can not list all + of them, so we can not make every Spreadtrum-special configuration + as one generic configuration, and maybe it will add more strange + global configuration in future. Then we add one "sprd,control" to + set these various global control configuration, and we need use + magic number for this property. + + Moreover we recognize every fields comprising one bit or several + bits in one global control register as one pin, thus we should + record every pin's bit offset, bit width and register offset to + configure this field (pin). + + The second block comprises some common registers which have unified + register definition, and each register described one pin is used + to configure the pin sleep mode, function select and sleep related + configuration. + + Now we have 4 systems for sleep mode on SC9860 SoC: AP system, + PUBCP system, TGLDSP system and AGDSP system. And the pin sleep + related configuration are: + - input-enable + - input-disable + - output-high + - output-low + - bias-pull-up + - bias-pull-down + + In some situation we need set the pin sleep mode and pin sleep related + configuration, to set the pin sleep related configuration automatically + by hardware when the system specified by sleep mode goes into deep + sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP + and set the pin sleep related configuration as "input-enable", which + means when PUBCP system goes into deep sleep mode, this pin will be set + input enable automatically. + + Moreover we can not use the "sleep" state, since some systems (like: + PUBCP system) do not run linux kernel OS (only AP system run linux + kernel on SC9860 platform), then we can not select "sleep" state + when the PUBCP system goes into deep sleep mode. Thus we introduce + "sprd,sleep-mode" property to set pin sleep mode. + + The last block comprises some misc registers which also have unified + register definition, and each register described one pin is used to + configure drive strength, pull up/down and so on. Especially for pull + up, we have two kind pull up resistor: 20K and 4.7K. + +properties: + compatible: + const: sprd,sc9860-pinctrl + + reg: + maxItems: 1 + +additionalProperties: + $ref: '#/$defs/pin-node' + unevaluatedProperties: false + + properties: + function: + description: Function to assign to the pins. + enum: + - func1 + - func2 + - func3 + - func4 + + drive-strength: + description: Drive strength in mA. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [2, 4, 6, 8, 10, 12, 14, 16, 20, 21, 24, 25, 27, 29, 31, 33] + + input-schmitt-disable: true + + input-schmitt-enable: true + + bias-pull-up: + enum: [20000, 4700] + + sprd,sleep-mode: + description: Pin sleep mode selection. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0x1f + + sprd,control: + description: Control values referring to databook for global control pins. + $ref: /schemas/types.yaml#/definitions/uint32 + + patternProperties: + 'sleep$': + $ref: '#/$defs/pin-node' + unevaluatedProperties: false + + properties: + bias-pull-up: + type: boolean + + sleep-hardware-state: + description: Indicate these configs in sleep related state. + type: boolean + +$defs: + pin-node: + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + properties: + pins: + description: Names of pins to configure. + $ref: /schemas/types.yaml#/definitions/string-array + + bias-disable: + description: Disable pin bias. + type: boolean + + bias-pull-down: + description: Pull down on pin. + type: boolean + + bias-pull-up: true + + input-enable: + description: Enable pin input. + type: boolean + + input-disable: + description: Enable pin output. + type: boolean + + output-high: + description: Set the pin as an output level high. + type: boolean + + output-low: + description: Set the pin as an output level low. + type: boolean + +required: + - compatible + - reg + +examples: + - | + pin_controller: pinctrl@402a0000 { + compatible = "sprd,sc9860-pinctrl"; + reg = <0x402a0000 0x10000>; + + grp1: sd0 { + pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE"; + sprd,control = <0x1>; + }; + + grp2: rfctl_33 { + pins = "SC9860_RFCTL33"; + function = "func2"; + sprd,sleep-mode = <3>; + grp2_sleep_mode: rfctl_33_sleep { + pins = "SC9860_RFCTL33"; + sleep-hardware-state; + output-low; + }; + }; + + grp3: rfctl_misc_20 { + pins = "SC9860_RFCTL20_MISC"; + drive-strength = <10>; + bias-pull-up = <4700>; + grp3_sleep_mode: rfctl_misc_sleep { + pins = "SC9860_RFCTL20_MISC"; + sleep-hardware-state; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml new file mode 100644 index 000000000..8f8b4b68a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-hdp.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) STMicroelectronics 2025. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/st,stm32-hdp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Hardware Debug Port Mux/Config + +maintainers: + - Clément LE GOFFIC <legoffic.clement@gmail.com> + +description: + STMicroelectronics's STM32 MPUs integrate a Hardware Debug Port (HDP). + It allows to output internal signals on SoC's GPIO. + +properties: + compatible: + enum: + - st,stm32mp131-hdp + - st,stm32mp151-hdp + - st,stm32mp251-hdp + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + access-controllers: + minItems: 1 + items: + - description: debug configuration access controller + - description: access controller that manages the HDP as a peripheral + +patternProperties: + "^hdp[0-7]-pins$": + type: object + $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + pins: + pattern: '^HDP[0-7]$' + + function: true + + required: + - function + - pins + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + const: st,stm32mp131-hdp + then: + patternProperties: + "^hdp[0-7]-pins$": + properties: + function: + enum: [ pwr_pwrwake_sys, pwr_stop_forbidden, pwr_stdby_wakeup, pwr_encomp_vddcore, + bsec_out_sec_niden, aiec_sys_wakeup, none, ddrctrl_lp_req, + pwr_ddr_ret_enable_n, dts_clk_ptat, sram3ctrl_tamp_erase_act, gpoval0, + pwr_sel_vth_vddcpu, pwr_mpu_ram_lowspeed, ca7_naxierrirq, pwr_okin_mr, + bsec_out_sec_dbgen, aiec_c1_wakeup, rcc_pwrds_mpu, ddrctrl_dfi_ctrlupd_req, + ddrctrl_cactive_ddrc_asr, sram3ctrl_hw_erase_act, nic400_s0_bready, gpoval1, + pwr_pwrwake_mpu, pwr_mpu_clock_disable_ack, ca7_ndbgreset_i, + bsec_in_rstcore_n, bsec_out_sec_bsc_dis, ddrctrl_dfi_init_complete, + ddrctrl_perf_op_is_refresh, ddrctrl_gskp_dfi_lp_req, sram3ctrl_sw_erase_act, + nic400_s0_bvalid, gpoval2, pwr_sel_vth_vddcore, pwr_mpu_clock_disable_req, + ca7_npmuirq0, ca7_nfiqout0, bsec_out_sec_dftlock, bsec_out_sec_jtag_dis, + rcc_pwrds_sys, sram3ctrl_tamp_erase_req, ddrctrl_stat_ddrc_reg_selfref_type0, + dts_valobus1_0, dts_valobus2_0, tamp_potential_tamp_erfcfg, nic400_s0_wready, + nic400_s0_rready, gpoval3, pwr_stop2_active, ca7_nl2reset_i, + ca7_npreset_varm_i, bsec_out_sec_dften, bsec_out_sec_dbgswenable, + eth1_out_pmt_intr_o, eth2_out_pmt_intr_o, ddrctrl_stat_ddrc_reg_selfref_type1, + ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, tamp_nreset_sram_ercfg, + nic400_s0_wlast, nic400_s0_rlast, gpoval4, ca7_standbywfil2, + pwr_vth_vddcore_ack, ca7_ncorereset_i, ca7_nirqout0, bsec_in_pwrok, + bsec_out_sec_deviceen, eth1_out_lpi_intr_o, eth2_out_lpi_intr_o, + ddrctrl_cactive_ddrc, ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2, + pka_pka_itamp_out, nic400_s0_wvalid, nic400_s0_rvalid, gpoval5, + ca7_standbywfe0, pwr_vth_vddcpu_ack, ca7_evento, bsec_in_tamper_det, + bsec_out_sec_spniden, eth1_out_mac_speed_o1, eth2_out_mac_speed_o1, + ddrctrl_csysack_ddrc, ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3, + saes_tamper_out, nic400_s0_awready, nic400_s0_arready, gpoval6, + ca7_standbywfi0, pwr_rcc_vcpu_rdy, ca7_eventi, ca7_dbgack0, bsec_out_fuse_ok, + bsec_out_sec_spiden, eth1_out_mac_speed_o0, eth2_out_mac_speed_o0, + ddrctrl_csysreq_ddrc, ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4, + rng_tamper_out, nic400_s0_awavalid, nic400_s0_aravalid, gpoval7 ] + - if: + properties: + compatible: + contains: + const: st,stm32mp151-hdp + then: + patternProperties: + "^hdp[0-7]-pins$": + properties: + function: + enum: [ pwr_pwrwake_sys, cm4_sleepdeep, pwr_stdby_wkup, pwr_encomp_vddcore, + bsec_out_sec_niden, none, rcc_cm4_sleepdeep, gpu_dbg7, ddrctrl_lp_req, + pwr_ddr_ret_enable_n, dts_clk_ptat, gpoval0, pwr_pwrwake_mcu, cm4_halted, + ca7_naxierrirq, pwr_okin_mr, bsec_out_sec_dbgen, exti_sys_wakeup, + rcc_pwrds_mpu, gpu_dbg6, ddrctrl_dfi_ctrlupd_req, ddrctrl_cactive_ddrc_asr, + gpoval1, pwr_pwrwake_mpu, cm4_rxev, ca7_npmuirq1, ca7_nfiqout1, + bsec_in_rstcore_n, exti_c2_wakeup, rcc_pwrds_mcu, gpu_dbg5, + ddrctrl_dfi_init_complete, ddrctrl_perf_op_is_refresh, + ddrctrl_gskp_dfi_lp_req, gpoval2, pwr_sel_vth_vddcore, cm4_txev, ca7_npmuirq0, + ca7_nfiqout0, bsec_out_sec_dftlock, exti_c1_wakeup, rcc_pwrds_sys, gpu_dbg4, + ddrctrl_stat_ddrc_reg_selfref_type0, ddrctrl_cactive_1, dts_valobus1_0, + dts_valobus2_0, gpoval3, pwr_mpu_pdds_not_cstbydis, cm4_sleeping, ca7_nreset1, + ca7_nirqout1, bsec_out_sec_dften, bsec_out_sec_dbgswenable, + eth_out_pmt_intr_o, gpu_dbg3, ddrctrl_stat_ddrc_reg_selfref_type1, + ddrctrl_cactive_0, dts_valobus1_1, dts_valobus2_1, gpoval4, ca7_standbywfil2, + pwr_vth_vddcore_ack, ca7_nreset0, ca7_nirqout0, bsec_in_pwrok, + bsec_out_sec_deviceen, eth_out_lpi_intr_o, gpu_dbg2, ddrctrl_cactive_ddrc, + ddrctrl_wr_credit_cnt, dts_valobus1_2, dts_valobus2_2, gpoval5, + ca7_standbywfi1, ca7_standbywfe1, ca7_evento, ca7_dbgack1, + bsec_out_sec_spniden, eth_out_mac_speed_o1, gpu_dbg1, ddrctrl_csysack_ddrc, + ddrctrl_lpr_credit_cnt, dts_valobus1_3, dts_valobus2_3, gpoval6, + ca7_standbywfi0, ca7_standbywfe0, ca7_dbgack0, bsec_out_fuse_ok, + bsec_out_sec_spiden, eth_out_mac_speed_o0, gpu_dbg0, ddrctrl_csysreq_ddrc, + ddrctrl_hpr_credit_cnt, dts_valobus1_4, dts_valobus2_4, gpoval7 ] + - if: + properties: + compatible: + contains: + const: st,stm32mp251-hdp + then: + patternProperties: + "^hdp[0-7]-pins$": + properties: + function: + enum: [ pwr_pwrwake_sys, cpu2_sleep_deep, bsec_out_tst_sdr_unlock_or_disable_scan, + bsec_out_nidenm, bsec_out_nidena, cpu2_state_0, rcc_pwrds_sys, gpu_dbg7, + ddrss_csysreq_ddrc, ddrss_dfi_phyupd_req, cpu3_sleep_deep, + d2_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_0, + pcie_usb_cxpl_debug_info_ei_8, d3_state_0, gpoval0, pwr_pwrwake_cpu2, + cpu2_halted, cpu2_state_1, bsec_out_dbgenm, bsec_out_dbgena, exti1_sys_wakeup, + rcc_pwrds_cpu2, gpu_dbg6, ddrss_csysack_ddrc, ddrss_dfi_phymstr_req, + cpu3_halted, d2_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_1, + pcie_usb_cxpl_debug_info_ei_9, d3_state_1, gpoval1, pwr_pwrwake_cpu1, + cpu2_rxev, cpu1_npumirq1, cpu1_nfiqout1, bsec_out_shdbgen, exti1_cpu2_wakeup, + rcc_pwrds_cpu1, gpu_dbg5, ddrss_cactive_ddrc, ddrss_dfi_lp_req, cpu3_rxev, + hpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_2, + pcie_usb_cxpl_debug_info_ei_10, d3_state_2, gpoval2, pwr_sel_vth_vddcpu, + cpu2_txev, cpu1_npumirq0, cpu1_nfiqout0, bsec_out_ddbgen, exti1_cpu1_wakeup, + cpu3_state_0, gpu_dbg4, ddrss_mcdcg_en, ddrss_dfi_freq_0, cpu3_txev, + hpdma2_clk_bus_req, pcie_usb_cxpl_debug_info_ei_3, + pcie_usb_cxpl_debug_info_ei_11, d1_state_0, gpoval3, pwr_sel_vth_vddcore, + cpu2_sleeping, cpu1_evento, cpu1_nirqout1, bsec_out_spnidena, exti2_d3_wakeup, + eth1_out_pmt_intr_o, gpu_dbg3, ddrss_dphycg_en, ddrss_obsp0, cpu3_sleeping, + hpdma3_clk_bus_req, pcie_usb_cxpl_debug_info_ei_4, + pcie_usb_cxpl_debug_info_ei_12, d1_state_1, gpoval4, cpu1_standby_wfil2, + none, cpu1_nirqout0, bsec_out_spidena, exti2_cpu3_wakeup, eth1_out_lpi_intr_o, + gpu_dbg2, ddrctrl_dfi_init_start, ddrss_obsp1, cpu3_state_1, + d3_gbl_per_clk_bus_req, pcie_usb_cxpl_debug_info_ei_5, + pcie_usb_cxpl_debug_info_ei_13, d1_state_2, gpoval5, cpu1_standby_wfi1, + cpu1_standby_wfe1, cpu1_halted1, cpu1_naxierrirq, bsec_out_spnidenm, + exti2_cpu2_wakeup, eth2_out_pmt_intr_o, gpu_dbg1, ddrss_dfi_init_complete, + ddrss_obsp2, d2_state_0, d3_gbl_per_dma_req, pcie_usb_cxpl_debug_info_ei_6, + pcie_usb_cxpl_debug_info_ei_14, cpu1_state_0, gpoval6, cpu1_standby_wfi0, + cpu1_standby_wfe0, cpu1_halted0, bsec_out_spidenm, exti2_cpu1__wakeup, + eth2_out_lpi_intr_o, gpu_dbg0, ddrss_dfi_ctrlupd_req, ddrss_obsp3, d2_state_1, + lpdma1_clk_bus_req, pcie_usb_cxpl_debug_info_ei_7, + pcie_usb_cxpl_debug_info_ei_15, cpu1_state_1, gpoval7 ] + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/stm32mp1-clks.h> + + pinctrl@54090000 { + compatible = "st,stm32mp151-hdp"; + reg = <0x54090000 0x400>; + clocks = <&rcc HDP>; + pinctrl-names = "default"; + pinctrl-0 = <&hdp2_gpo>; + hdp2_gpo: hdp2-pins { + function = "gpoval2"; + pins = "HDP2"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml new file mode 100644 index 000000000..76d956b4a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -0,0 +1,383 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) STMicroelectronics 2019. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 GPIO and Pin Mux/Config controller + +maintainers: + - Alexandre TORGUE <alexandre.torgue@foss.st.com> + +description: | + STMicroelectronics's STM32 MCUs integrate a GPIO and Pin mux/config hardware + controller. It controls the input/output settings on the available pins and + also provides ability to multiplex and configure the output of various + on-chip controllers onto these pads. + +properties: + compatible: + enum: + - st,stm32f429-pinctrl + - st,stm32f469-pinctrl + - st,stm32f746-pinctrl + - st,stm32f769-pinctrl + - st,stm32h743-pinctrl + - st,stm32mp135-pinctrl + - st,stm32mp157-pinctrl + - st,stm32mp157-z-pinctrl + - st,stm32mp257-pinctrl + - st,stm32mp257-z-pinctrl + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + + pins-are-numbered: + $ref: /schemas/types.yaml#/definitions/flag + deprecated: true + + hwlocks: true + + interrupts: + maxItems: 1 + + st,syscfg: + description: Phandle+args to the syscon node which includes IRQ mux selection. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - minItems: 2 + items: + - description: syscon node which includes IRQ mux selection + - description: The offset of the IRQ mux selection register + - description: The field mask of IRQ mux, needed if different of 0xf + + st,package: + description: + Indicates the SOC package used. + More details in include/dt-bindings/pinctrl/stm32-pinfunc.h + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800] + +patternProperties: + '^gpio@[0-9a-f]*$': + type: object + additionalProperties: false + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + '#interrupt-cells': + const: 2 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + gpio-line-names: true + + gpio-ranges: + minItems: 1 + maxItems: 16 + + ngpios: + description: + Number of available gpios in a bank. + minimum: 1 + maximum: 16 + + st,bank-name: + description: + Should be a name string for this bank as specified in the datasheet. + $ref: /schemas/types.yaml#/definitions/string + enum: + - GPIOA + - GPIOB + - GPIOC + - GPIOD + - GPIOE + - GPIOF + - GPIOG + - GPIOH + - GPIOI + - GPIOJ + - GPIOK + - GPIOZ + + st,bank-ioport: + description: + Should correspond to the EXTI IOport selection (EXTI line used + to select GPIOs as interrupts). + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 11 + + patternProperties: + "^(.+-hog(-[0-9]+)?)$": + type: object + required: + - gpio-hog + + required: + - gpio-controller + - '#gpio-cells' + - reg + - clocks + - st,bank-name + + '-[0-9]*$': + type: object + additionalProperties: false + + patternProperties: + '^pins': + type: object + additionalProperties: false + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl group available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive, output high/low and output speed. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pinmux: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are + defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly. + These defines are calculated as: ((port * 16 + line) << 8) | function + With: + - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) + - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) + - function: The function number, can be: + * 0 : GPIO + * 1 : Alternate Function 0 + * 2 : Alternate Function 1 + * 3 : Alternate Function 2 + * ... + * 16 : Alternate Function 15 + * 17 : Analog + * 18 : Reserved + To simplify the usage, macro is available to generate "pinmux" field. + This macro is available here: + - include/dt-bindings/pinctrl/stm32-pinfunc.h + Setting the pinmux's function to the Reserved (RSVD) value is used to inform + the driver that it shall not apply the mux setting. This can be used to + reserve some pins, for example to a co-processor not running Linux. + Some examples of using macro: + /* GPIO A9 set as alternate function 2 */ + ... { + pinmux = <STM32_PINMUX('A', 9, AF2)>; + }; + /* GPIO A9 set as GPIO */ + ... { + pinmux = <STM32_PINMUX('A', 9, GPIO)>; + }; + /* GPIO A9 set as analog */ + ... { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>; + }; + /* GPIO A9 reserved for co-processor */ + ... { + pinmux = <STM32_PINMUX('A', 9, RSVD)>; + }; + + bias-disable: true + + bias-pull-down: true + + bias-pull-up: true + + drive-push-pull: true + + drive-open-drain: true + + output-low: true + + output-high: true + + slew-rate: + description: | + 0: Low speed + 1: Medium speed + 2: Fast speed + 3: High speed + minimum: 0 + maximum: 3 + + skew-delay-input-ps: + description: | + IO synchronization skew rate applied to the input path + enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250] + + skew-delay-output-ps: + description: | + IO synchronization latch delay applied to the output path + enum: [0, 300, 500, 750, 1000, 1250, 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250] + + st,io-sync: + $ref: /schemas/types.yaml#/definitions/string + enum: + - pass-through + - clock inverted + - data on rising edge + - data on falling edge + - data on both edges + description: | + IO synchronization through re-sampling or inversion + "pass-through" - data or clock GPIO pass-through + "clock inverted" - clock GPIO inverted + "data on rising edge" - data GPIO re-sampled on clock rising edge + "data on falling edge" - data GPIO re-sampled on clock falling edge + "data on both edges" - data GPIO re-sampled on both clock edges + default: pass-through + + required: + - pinmux + + # Not allowed both skew-delay-input-ps and skew-delay-output-ps + if: + required: + - skew-delay-input-ps + then: + properties: + skew-delay-output-ps: false + +allOf: + - $ref: pinctrl.yaml# + + - if: + not: + properties: + compatible: + contains: + enum: + - st,stm32mp257-pinctrl + - st,stm32mp257-z-pinctrl + then: + patternProperties: + '-[0-9]*$': + patternProperties: + '^pins': + properties: + skew-delay-input-ps: false + skew-delay-output-ps: false + st,io-sync: false + +required: + - compatible + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/stm32-pinfunc.h> + #include <dt-bindings/mfd/stm32f4-rcc.h> + //Example 1 + pinctrl@40020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + + gpioa: gpio@0 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>; + st,bank-name = "GPIOA"; + }; + }; + + //Example 2 (using gpio-ranges) + pinctrl@50020000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x50020000 0x3000>; + + gpiob: gpio@1000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x400>; + resets = <&reset_ahb1 0>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>; + st,bank-name = "GPIOB"; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpioc: gpio@2000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x400>; + resets = <&reset_ahb1 0>; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>; + st,bank-name = "GPIOC"; + ngpios = <5>; + gpio-ranges = <&pinctrl 0 16 3>, + <&pinctrl 14 30 2>; + }; + }; + + //Example 3 pin groups + pinctrl { + usart1_pins_a: usart1-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, AF7)>; + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 10, AF7)>; + bias-disable; + }; + }; + }; + + usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + }; + + - | + #include <dt-bindings/pinctrl/stm32-pinfunc.h> + //Example 4 skew-delay and st,io-sync + pinctrl: pinctrl@44240000 { + compatible = "st,stm32mp257-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44240000 0xa0400>; + + eth3_rgmii_pins_a: eth3-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 6, AF14)>; + st,io-sync = "data on both edges"; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 2, AF14)>; + skew-delay-output-ps = <500>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml new file mode 100644 index 000000000..3f14eab01 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml @@ -0,0 +1,306 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 Pin Controller + +description: | + Bindings for the JH7100 RISC-V SoC from StarFive Ltd. + + Out of the SoC's many pins only the ones named PAD_GPIO[0] to PAD_GPIO[63] + and PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141] can be multiplexed and have + configurable bias, drive strength, schmitt trigger etc. The SoC has an + interesting 2-layered approach to pin muxing best illustrated by the diagram + below. + + Signal group 0, 1, ... or 6 + ___|___ + | | + LCD output -----------------| | + CMOS Camera interface ------| |--- PAD_GPIO[0] + Ethernet PHY interface -----| MUX |--- PAD_GPIO[1] + ... | | ... + | |--- PAD_GPIO[63] + -------- GPIO0 ------------| | + | -------|-- GPIO1 --------| |--- PAD_FUNC_SHARE[0] + | | | | | |--- PAD_FUNC_SHARE[1] + | | | | ... | | ... + | | | | | |--- PAD_FUNC_SHARE[141] + | | -----|---|-- GPIO63 ---| | + | | | | | | ------- + UART0 UART1 -- + + The big MUX in the diagram only has 7 different ways of mapping peripherals + on the left to pins on the right. StarFive calls the 7 configurations "signal + groups". + However some peripherals have their I/O go through the 64 "GPIOs". The + diagram only shows UART0 and UART1, but this also includes a number of other + UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64 + GPIOs such that any GPIO can be set up to be controlled by any of the + peripherals. + Note that signal group 0 doesn't map any of the GPIOs to pins, and only + signal group 1 maps the GPIOs to the pins named PAD_GPIO[0] to PAD_GPIO[63]. + +maintainers: + - Emil Renner Berthing <kernel@esmil.dk> + - Drew Fustini <drew@beagleboard.org> + +properties: + compatible: + const: starfive,jh7100-pinctrl + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: gpio + - const: padctl + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupts: + maxItems: 1 + description: The GPIO parent interrupt. + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + starfive,signal-group: + description: | + Select one of the 7 signal groups. If this property is not set it + defaults to the configuration already chosen by the earlier boot stages. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3, 4, 5, 6] + +required: + - compatible + - reg + - reg-names + - clocks + - gpio-controller + - "#gpio-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + +patternProperties: + '-[0-9]+$': + type: object + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: | + The list of pin identifiers that properties in the node apply to. + This should be set using either the PAD_GPIO or PAD_FUNC_SHARE + macros. + Either this or "pinmux" has to be specified, but not both. + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pins + + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX macro. + Either this or "pins" has to be specified, but not both. + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 14, 21, 28, 35, 42, 49, 56, 63 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 7 + + starfive,strong-pull-up: + description: enable strong pull-up. + type: boolean + + additionalProperties: false + + additionalProperties: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive-jh7100.h> + #include <dt-bindings/reset/starfive-jh7100.h> + #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@11910000 { + compatible = "starfive,jh7100-pinctrl"; + reg = <0x0 0x11910000 0x0 0x10000>, + <0x0 0x11858000 0x0 0x1000>; + reg-names = "gpio", "padctl"; + clocks = <&clkgen JH7100_CLK_GPIO_APB>; + resets = <&clkgen JH7100_RSTN_GPIO_APB>; + interrupts = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + starfive,signal-group = <6>; + + gmac_pins_default: gmac-0 { + gtxclk-pins { + pins = <PAD_FUNC_SHARE(115)>; + bias-pull-up; + drive-strength = <35>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + miitxclk-pins { + pins = <PAD_FUNC_SHARE(116)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + tx-pins { + pins = <PAD_FUNC_SHARE(117)>, + <PAD_FUNC_SHARE(119)>, + <PAD_FUNC_SHARE(120)>, + <PAD_FUNC_SHARE(121)>, + <PAD_FUNC_SHARE(122)>, + <PAD_FUNC_SHARE(123)>, + <PAD_FUNC_SHARE(124)>, + <PAD_FUNC_SHARE(125)>, + <PAD_FUNC_SHARE(126)>; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + rxclk-pins { + pins = <PAD_FUNC_SHARE(127)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <6>; + }; + rxer-pins { + pins = <PAD_FUNC_SHARE(129)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + rx-pins { + pins = <PAD_FUNC_SHARE(128)>, + <PAD_FUNC_SHARE(130)>, + <PAD_FUNC_SHARE(131)>, + <PAD_FUNC_SHARE(132)>, + <PAD_FUNC_SHARE(133)>, + <PAD_FUNC_SHARE(134)>, + <PAD_FUNC_SHARE(135)>, + <PAD_FUNC_SHARE(136)>, + <PAD_FUNC_SHARE(137)>, + <PAD_FUNC_SHARE(138)>, + <PAD_FUNC_SHARE(139)>, + <PAD_FUNC_SHARE(140)>, + <PAD_FUNC_SHARE(141)>; + bias-pull-up; + drive-strength = <14>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + + i2c0_pins_default: i2c0-0 { + i2c-pins { + pinmux = <GPIOMUX(62, GPO_LOW, + GPO_I2C0_PAD_SCK_OEN, + GPI_I2C0_PAD_SCK_IN)>, + <GPIOMUX(61, GPO_LOW, + GPO_I2C0_PAD_SDA_OEN, + GPI_I2C0_PAD_SDA_IN)>; + bias-disable; /* external pull-up */ + input-enable; + input-schmitt-enable; + }; + }; + + uart3_pins_default: uart3-0 { + rx-pins { + pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE, + GPI_UART3_PAD_SIN)>; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + tx-pins { + pinmux = <GPIOMUX(14, GPO_UART3_PAD_SOUT, + GPO_ENABLE, GPI_NONE)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + }; + + gmac { + pinctrl-0 = <&gmac_pins_default>; + pinctrl-names = "default"; + }; + + i2c { + pinctrl-0 = <&i2c0_pins_default>; + pinctrl-names = "default"; + }; + + uart3 { + pinctrl-0 = <&uart3_pins_default>; + pinctrl-names = "default"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml new file mode 100644 index 000000000..4dbef86bd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-aon-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 AON Pin Controller + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + + Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3 + can be multiplexed and have configurable bias, drive strength, + schmitt trigger etc. + Some peripherals such as PWM have their I/O go through the 4 "GPIOs". + +maintainers: + - Hal Feng <hal.feng@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-aon-pinctrl + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX macro. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pinctrl@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x17020000 0x10000>; + resets = <&aoncrg 2>; + interrupts = <85>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + pwm-0 { + pwm-pins { + pinmux = <0xff030802>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml new file mode 100644 index 000000000..e2a25a20f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7110-sys-pinctrl.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SYS Pin Controller + +description: | + Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd. + + Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63 + can be multiplexed and have configurable bias, drive strength, + schmitt trigger etc. + Some peripherals have their I/O go through the 64 "GPIOs". This also + includes a number of other UARTs, I2Cs, SPIs, PWMs etc. + All these peripherals are connected to all 64 GPIOs such that + any GPIO can be set up to be controlled by any of the peripherals. + +maintainers: + - Hal Feng <hal.feng@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-sys-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to + muxer configuration, bias, input enable/disable, input schmitt + trigger enable/disable, slew-rate and drive strength. + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + additionalProperties: false + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the GPIOMUX or PINMUX + macros. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength: + enum: [ 2, 4, 8, 12 ] + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pinctrl@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x13040000 0x10000>; + clocks = <&syscrg 112>; + resets = <&syscrg 2>; + interrupts = <86>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + uart0-0 { + tx-pins { + pinmux = <0xff140005>; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = <0x0E000406>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt new file mode 100644 index 000000000..876974204 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ste,abx500.txt @@ -0,0 +1,318 @@ +ST Ericsson abx500 pinmux controller + +Required properties: +- compatible: "stericsson,ab8500-gpio", "stericsson,ab8540-gpio", + "stericsson,ab8505-gpio", "stericsson,ab9540-gpio", + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +ST Ericsson's pin configuration nodes use the generic pin multiplexing +and pin configuration bindings, see pinctrl-bindings.txt + +Example board file extract: + +&pinctrl_abx500 { + pinctrl-names = "default"; + pinctrl-0 = <&sysclkreq2_default_mode>, <&sysclkreq3_default_mode>, <&gpio3_default_mode>, <&sysclkreq6_default_mode>, <&pwmout1_default_mode>, <&pwmout2_default_mode>, <&pwmout3_default_mode>, <&adi1_default_mode>, <&dmic12_default_mode>, <&dmic34_default_mode>, <&dmic56_default_mode>, <&sysclkreq5_default_mode>, <&batremn_default_mode>, <&service_default_mode>, <&pwrctrl0_default_mode>, <&pwrctrl1_default_mode>, <&pwmextvibra1_default_mode>, <&pwmextvibra2_default_mode>, <&gpio51_default_mode>, <&gpio52_default_mode>, <&gpio53_default_mode>, <&gpio54_default_mode>, <&pdmclkdat_default_mode>; + + sysclkreq2 { + sysclkreq2_default_mode: sysclkreq2_default { + default_mux { + function = "sysclkreq"; + groups = "sysclkreq2_d_1"; + }; + default_cfg { + pins = "GPIO1"; + bias-disable; + }; + }; + }; + sysclkreq3 { + sysclkreq3_default_mode: sysclkreq3_default { + default_mux { + function = "sysclkreq"; + groups = "sysclkreq3_d_1"; + }; + default_cfg { + pins = "GPIO2"; + output-low; + }; + }; + }; + gpio3 { + gpio3_default_mode: gpio3_default { + default_mux { + function = "gpio"; + groups = "gpio3_a_1"; + }; + default_cfg { + pins = "GPIO3"; + output-low; + }; + }; + }; + sysclkreq6 { + sysclkreq6_default_mode: sysclkreq6_default { + default_mux { + function = "sysclkreq"; + groups = "sysclkreq6_d_1"; + }; + default_cfg { + pins = "GPIO4"; + bias-disable; + }; + }; + }; + pwmout1 { + pwmout1_default_mode: pwmout1_default { + default_mux { + function = "pwmout"; + groups = "pwmout1_d_1"; + }; + default_cfg { + pins = "GPIO14"; + output-low; + }; + }; + }; + pwmout2 { + pwmout2_default_mode: pwmout2_default { + pwmout2_default_mux { + function = "pwmout"; + groups = "pwmout2_d_1"; + }; + pwmout2_default_cfg { + pins = "GPIO15"; + output-low; + }; + }; + }; + pwmout3 { + pwmout3_default_mode: pwmout3_default { + pwmout3_default_mux { + function = "pwmout"; + groups = "pwmout3_d_1"; + }; + pwmout3_default_cfg { + pins = "GPIO16"; + output-low; + }; + }; + }; + adi1 { + + adi1_default_mode: adi1_default { + adi1_default_mux { + function = "adi1"; + groups = "adi1_d_1"; + }; + adi1_default_cfg1 { + pins = "GPIO17","GPIO19","GPIO20"; + bias-disable; + }; + adi1_default_cfg2 { + pins = "GPIO18"; + output-low; + }; + }; + }; + dmic12 { + dmic12_default_mode: dmic12_default { + dmic12_default_mux { + function = "dmic"; + groups = "dmic12_d_1"; + }; + dmic12_default_cfg1 { + pins = "GPIO27"; + output-low; + }; + dmic12_default_cfg2 { + pins = "GPIO28"; + bias-disable; + }; + }; + }; + dmic34 { + dmic34_default_mode: dmic34_default { + dmic34_default_mux { + function = "dmic"; + groups = "dmic34_d_1"; + }; + dmic34_default_cfg1 { + pins = "GPIO29"; + output-low; + }; + dmic34_default_cfg2 { + pins = "GPIO30"; + bias-disable;{ + + }; + }; + }; + dmic56 { + dmic56_default_mode: dmic56_default { + dmic56_default_mux { + function = "dmic"; + groups = "dmic56_d_1"; + }; + dmic56_default_cfg1 { + pins = "GPIO31"; + output-low; + }; + dmic56_default_cfg2 { + pins = "GPIO32"; + bias-disable; + }; + }; + }; + sysclkreq5 { + sysclkreq5_default_mode: sysclkreq5_default { + sysclkreq5_default_mux { + function = "sysclkreq"; + groups = "sysclkreq5_d_1"; + }; + sysclkreq5_default_cfg { + pins = "GPIO42"; + output-low; + }; + }; + }; + batremn { + batremn_default_mode: batremn_default { + batremn_default_mux { + function = "batremn"; + groups = "batremn_d_1"; + }; + batremn_default_cfg { + pins = "GPIO43"; + bias-disable; + }; + }; + }; + service { + service_default_mode: service_default { + service_default_mux { + function = "service"; + groups = "service_d_1"; + }; + service_default_cfg { + pins = "GPIO44"; + bias-disable; + }; + }; + }; + pwrctrl0 { + pwrctrl0_default_mux: pwrctrl0_mux { + pwrctrl0_default_mux { + function = "pwrctrl"; + groups = "pwrctrl0_d_1"; + }; + }; + pwrctrl0_default_mode: pwrctrl0_default { + pwrctrl0_default_cfg { + pins = "GPIO45"; + bias-disable; + }; + }; + }; + pwrctrl1 { + pwrctrl1_default_mux: pwrctrl1_mux { + pwrctrl1_default_mux { + function = "pwrctrl"; + groups = "pwrctrl1_d_1"; + }; + }; + pwrctrl1_default_mode: pwrctrl1_default { + pwrctrl1_default_cfg { + pins = "GPIO46"; + bias-disable; + }; + }; + }; + pwmextvibra1 { + pwmextvibra1_default_mode: pwmextvibra1_default { + pwmextvibra1_default_mux { + function = "pwmextvibra"; + groups = "pwmextvibra1_d_1"; + }; + pwmextvibra1_default_cfg { + pins = "GPIO47"; + bias-disable; + }; + }; + }; + pwmextvibra2 { + pwmextvibra2_default_mode: pwmextvibra2_default { + pwmextvibra2_default_mux { + function = "pwmextvibra"; + groups = "pwmextvibra2_d_1"; + }; + pwmextvibra1_default_cfg { + pins = "GPIO48"; + bias-disable; + }; + }; + }; + gpio51 { + gpio51_default_mode: gpio51_default { + gpio51_default_mux { + function = "gpio"; + groups = "gpio51_a_1"; + }; + gpio51_default_cfg { + pins = "GPIO51"; + output-low; + }; + }; + }; + gpio52 { + gpio52_default_mode: gpio52_default { + gpio52_default_mux { + function = "gpio"; + groups = "gpio52_a_1"; + }; + gpio52_default_cfg { + pins = "GPIO52"; + bias-pull-down; + }; + }; + }; + gpio53 { + gpio53_default_mode: gpio53_default { + gpio53_default_mux { + function = "gpio"; + groups = "gpio53_a_1"; + }; + gpio53_default_cfg { + pins = "GPIO53"; + bias-pull-down; + }; + }; + }; + gpio54 { + gpio54_default_mode: gpio54_default { + gpio54_default_mux { + function = "gpio"; + groups = "gpio54_a_1"; + }; + gpio54_default_cfg { + pins = "GPIO54"; + output-low; + }; + }; + }; + pdmclkdat { + pdmclkdat_default_mode: pdmclkdat_default { + pdmclkdat_default_mux { + function = "pdm"; + groups = "pdmclkdat_d_1"; + }; + pdmclkdat_default_cfg { + pins = "GPIO55", "GPIO56"; + bias-disable; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt new file mode 100644 index 000000000..221380243 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ste,nomadik.txt @@ -0,0 +1,148 @@ +ST Ericsson Nomadik pinmux controller + +Required properties: +- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl", + "stericsson,stn8815-pinctrl" +- nomadik-gpio-chips: array of phandles to the corresponding GPIO chips + (these have the register ranges used by the pin controller). +- prcm: phandle to the PRCMU managing the back end of this pin controller + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +ST Ericsson's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as input, output, pull up, pull down... + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. The subnodes use the generic +pin multiplexing node layout from the standard pin control bindings +(see pinctrl-bindings.txt): + +Required pin multiplexing subnode properties: +- function: A string containing the name of the function to mux to the + pin or group. +- groups : An array of strings. Each string contains the name of a pin + group that will be combined with the function to form a multiplexing + set-up. + +Required pin configuration subnode properties: +- pins: A string array describing the pins affected by the configuration + in the node. +- ste,config: Handle of pin configuration node + (e.g. ste,config = <&slpm_in_wkup_pdis>) + +- ste,input : <0/1/2> + 0: input with no pull + 1: input with pull up, + 2: input with pull down, + +- ste,output: <0/1/2> + 0: output low, + 1: output high, + 2: output (value is not specified). + +- ste,sleep: <0/1> + 0: sleep mode disable, + 1: sleep mode enable. + +- ste,sleep-input: <0/1/2/3> + 0: sleep input with no pull, + 1: sleep input with pull up, + 2: sleep input with pull down. + 3: sleep input and keep last input configuration (no pull, pull up or pull down). + +- ste,sleep-output: <0/1/2> + 0: sleep output low, + 1: sleep output high, + 2: sleep output (value is not specified). + +- ste,sleep-gpio: <0/1> + 0: disable sleep gpio mode, + 1: enable sleep gpio mode. + +- ste,sleep-wakeup: <0/1> + 0: wake-up detection enabled, + 1: wake-up detection disabled. + +- ste,sleep-pull-disable: <0/1> + 0: GPIO pull-up or pull-down resistor is enabled, when pin is an input, + 1: GPIO pull-up and pull-down resistor are disabled. + +Example board file extract: + + pinctrl@80157000 { + compatible = "stericsson,db8500-pinctrl"; + nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; + prcm = <&prcmu>; + + pinctrl-names = "default"; + + slpm_in_wkup_pdis: slpm_in_wkup_pdis { + ste,sleep = <1>; + ste,sleep-input = <3>; + ste,sleep-wakeup = <1>; + ste,sleep-pull-disable = <0>; + }; + + slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis { + ste,sleep = <1>; + ste,sleep-output = <1>; + ste,sleep-wakeup = <1>; + ste,sleep-pull-disable = <0>; + }; + + slpm_out_wkup_pdis: slpm_out_wkup_pdis { + ste,sleep = <1>; + ste,sleep-output = <2>; + ste,sleep-wakeup = <1>; + ste,sleep-pull-disable = <0>; + }; + + uart0 { + uart0_default_mux: uart0_mux { + u0_default_mux { + function = "u0"; + pins = "u0_a_1"; + }; + }; + uart0_default_mode: uart0_default { + uart0_default_cfg1 { + pins = "GPIO0", "GPIO2"; + ste,input = <1>; + }; + + uart0_default_cfg2 { + pins = "GPIO1", "GPIO3"; + ste,output = <1>; + }; + }; + uart0_sleep_mode: uart0_sleep { + uart0_sleep_cfg1 { + pins = "GPIO0", "GPIO2"; + ste,config = <&slpm_in_wkup_pdis>; + }; + uart0_sleep_cfg2 { + pins = "GPIO1"; + ste,config = <&slpm_out_hi_wkup_pdis>; + }; + uart0_sleep_cfg3 { + pins = "GPIO3"; + ste,config = <&slpm_out_wkup_pdis>; + }; + }; + }; + }; + + uart@80120000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80120000 0x1000>; + interrupts = <0 11 0x4>; + + pinctrl-names = "default","sleep"; + pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>; + pinctrl-1 = <&uart0_sleep_mode>; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml new file mode 100644 index 000000000..94b868c7c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml @@ -0,0 +1,377 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) Sunplus Co., Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sunplus SP7021 Pin Controller + +maintainers: + - Dvorkin Dmitry <dvorkin@tibbo.com> + - Wells Lu <wellslutw@gmail.com> + +description: | + The Sunplus SP7021 pin controller is used to control SoC pins. Please + refer to pinctrl-bindings.txt in this directory for details of the common + pinctrl bindings used by client devices. + + SP7021 has 99 digital GPIO pins which are numbered from GPIO 0 to 98. All + are multiplexed with some special function pins. SP7021 has 3 types of + special function pins: + + (1) function-group pins: + Ex 1 (SPI-NOR flash): + If control-field SPI_FLASH_SEL is set to 1, GPIO 83, 84, 86 and 87 + will be pins of SPI-NOR flash. If it is set to 2, GPIO 76, 78, 79 + and 81 will be pins of SPI-NOR flash. + + Ex 2 (UART_0): + If control-bit UA0_SEL is set to 1, GPIO 88 and 89 will be TX and + RX pins of UART_0 (UART channel 0). + + Ex 3 (eMMC): + If control-bit EMMC_SEL is set to 1, GPIO 72, 73, 74, 75, 76, 77, + 78, 79, 80, 81 will be pins of an eMMC device. + + Properties "function" and "groups" are used to select function-group + pins. + + (2) fully pin-mux (like phone exchange mux) pins: + GPIO 8 to 71 are 'fully pin-mux' pins. Any pins of peripherals of + SP7021 (ex: UART_1, UART_2, UART_3, UART_4, I2C_0, I2C_1, and etc.) + can be routed to any pins of fully pin-mux pins. + + Ex 1 (UART channel 1): + If control-field UA1_TX_SEL is set to 3, TX pin of UART_1 will be + routed to GPIO 10 (3 - 1 + 8 = 10). + If control-field UA1_RX_SEL is set to 4, RX pin of UART_1 will be + routed to GPIO 11 (4 - 1 + 8 = 11). + If control-field UA1_RTS_SEL is set to 5, RTS pin of UART_1 will + be routed to GPIO 12 (5 - 1 + 8 = 12). + If control-field UA1_CTS_SEL is set to 6, CTS pin of UART_1 will + be routed to GPIO 13 (6 - 1 + 8 = 13). + + Ex 2 (I2C channel 0): + If control-field I2C0_CLK_SEL is set to 20, CLK pin of I2C_0 will + be routed to GPIO 27 (20 - 1 + 8 = 27). + If control-field I2C0_DATA_SEL is set to 21, DATA pin of I2C_0 + will be routed to GPIO 28 (21 - 1 + 9 = 28). + + Totally, SP7021 has 120 peripheral pins. The peripheral pins can be + routed to any of 64 'fully pin-mux' pins. + + (3) I/O processor pins + SP7021 has a built-in I/O processor. + Any GPIO pins (GPIO 0 to 98) can be set to pins of I/O processor. + + Vendor property "sunplus,pins" is used to select "fully pin-mux" pins, + "I/O processor pins" and "digital GPIO" pins. + + The device node of pin controller of Sunplus SP7021 has following + properties. + +properties: + compatible: + const: sunplus,sp7021-pctl + + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + items: + - description: the MOON2 registers + - description: the GPIOXT registers + - description: the FIRST registers + - description: the MOON1 registers + + reg-names: + items: + - const: moon2 + - const: gpioxt + - const: first + - const: moon1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pins or function-pins group available on the machine. Each subnode + will list the pins it needs, and how they should be configured. + + Pinctrl node's client devices use subnodes for desired pin + configuration. Client device subnodes use below standard properties. + $ref: pinmux-node.yaml# + + properties: + sunplus,pins: + description: | + Define 'sunplus,pins' which are used by pinctrl node's client + device. + + It consists of one or more integers which represents the config + setting for corresponding pin. Each integer defines a individual + pin in which: + + Bit 32~24: defines GPIO number. Its range is 0 ~ 98. + Bit 23~16: defines types: (1) fully pin-mux pins + (2) IO processor pins + (3) digital GPIO pins + Bit 15~8: defines pins of peripherals (which are defined in + 'include/dt-binging/pinctrl/sppctl.h'). + Bit 7~0: defines types or initial-state of digital GPIO pins. + + Please use macro SPPCTL_IOPAD to define the integers for pins. + + $ref: /schemas/types.yaml#/definitions/uint32-array + + function: + description: | + Define pin-function which is used by pinctrl node's client device. + The name should be one of string in the following enumeration. + $ref: /schemas/types.yaml#/definitions/string + enum: [ SPI_FLASH, SPI_FLASH_4BIT, SPI_NAND, CARD0_EMMC, SD_CARD, + UA0, FPGA_IFX, HDMI_TX, LCDIF, USB0_OTG, USB1_OTG ] + + groups: + description: | + Define pin-group in a specified pin-function. + The name should be one of string in the following enumeration. + $ref: /schemas/types.yaml#/definitions/string + enum: [ SPI_FLASH1, SPI_FLASH2, SPI_FLASH_4BIT1, SPI_FLASH_4BIT2, + SPI_NAND, CARD0_EMMC, SD_CARD, UA0, FPGA_IFX, HDMI_TX1, + HDMI_TX2, HDMI_TX3, LCDIF, USB0_OTG, USB1_OTG ] + + sunplus,zerofunc: + description: | + This is a vendor specific property. It is used to disable pins + which are not used by pinctrl node's client device. + Some pins may be enabled by boot-loader. We can use this + property to disable them. + $ref: /schemas/types.yaml#/definitions/uint32-array + + additionalProperties: false + + allOf: + - if: + properties: + function: + enum: + - SPI_FLASH + then: + properties: + groups: + enum: + - SPI_FLASH1 + - SPI_FLASH2 + - if: + properties: + function: + enum: + - SPI_FLASH_4BIT + then: + properties: + groups: + enum: + - SPI_FLASH_4BIT1 + - SPI_FLASH_4BIT2 + - if: + properties: + function: + enum: + - SPI_NAND + then: + properties: + groups: + enum: + - SPI_NAND + - if: + properties: + function: + enum: + - CARD0_EMMC + then: + properties: + groups: + enum: + - CARD0_EMMC + - if: + properties: + function: + enum: + - SD_CARD + then: + properties: + groups: + enum: + - SD_CARD + - if: + properties: + function: + enum: + - UA0 + then: + properties: + groups: + enum: + - UA0 + - if: + properties: + function: + enum: + - FPGA_IFX + then: + properties: + groups: + enum: + - FPGA_IFX + - if: + properties: + function: + enum: + - HDMI_TX + then: + properties: + groups: + enum: + - HDMI_TX1 + - HDMI_TX2 + - HDMI_TX3 + - if: + properties: + function: + enum: + - LCDIF + then: + properties: + groups: + enum: + - LCDIF + - if: + properties: + function: + enum: + - USB0_OTG + then: + properties: + groups: + enum: + - USB0_OTG + - if: + properties: + function: + enum: + - USB1_OTG + then: + properties: + groups: + enum: + - USB1_OTG + +required: + - compatible + - reg + - reg-names + - "#gpio-cells" + - gpio-controller + - clocks + - resets + +additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +examples: + - | + #include <dt-bindings/pinctrl/sppctl-sp7021.h> + + pinctrl@9c000100 { + compatible = "sunplus,sp7021-pctl"; + reg = <0x9c000100 0x100>, <0x9c000300 0x100>, + <0x9c0032e4 0x1c>, <0x9c000080 0x20>; + reg-names = "moon2", "gpioxt", "first", "moon1"; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clkc 0x83>; + resets = <&rstc 0x73>; + + uart0-pins { + function = "UA0"; + groups = "UA0"; + }; + + spinand0-pins { + function = "SPI_NAND"; + groups = "SPI_NAND"; + }; + + uart1-pins { + sunplus,pins = < + SPPCTL_IOPAD(11, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(10, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + >; + }; + + uart2-pins { + sunplus,pins = < + SPPCTL_IOPAD(20, SPPCTL_PCTL_G_PMUX, MUXF_UA1_TX, 0) + SPPCTL_IOPAD(21, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RX, 0) + SPPCTL_IOPAD(22, SPPCTL_PCTL_G_PMUX, MUXF_UA1_RTS, 0) + SPPCTL_IOPAD(23, SPPCTL_PCTL_G_PMUX, MUXF_UA1_CTS, 0) + >; + }; + + emmc-pins { + function = "CARD0_EMMC"; + groups = "CARD0_EMMC"; + }; + + sdcard-pins { + function = "SD_CARD"; + groups = "SD_CARD"; + sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >; + }; + + hdmi_A_tx1-pins { + function = "HDMI_TX"; + groups = "HDMI_TX1"; + }; + hdmi_A_tx2-pins { + function = "HDMI_TX"; + groups = "HDMI_TX2"; + }; + hdmi_A_tx3-pins { + function = "HDMI_TX"; + groups = "HDMI_TX3"; + }; + + ethernet-pins { + sunplus,pins = < + SPPCTL_IOPAD(49,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_CLK_OUT,0) + SPPCTL_IOPAD(44,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDC,0) + SPPCTL_IOPAD(43,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_MAC_SMI_MDIO,0) + SPPCTL_IOPAD(52,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXEN,0) + SPPCTL_IOPAD(50,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD0,0) + SPPCTL_IOPAD(51,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_TXD1,0) + SPPCTL_IOPAD(46,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_CRSDV,0) + SPPCTL_IOPAD(47,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD0,0) + SPPCTL_IOPAD(48,SPPCTL_PCTL_G_PMUX,MUXF_L2SW_P0_MAC_RMII_RXD1,0) + >; + sunplus,zerofunc = < + MUXF_L2SW_LED_FLASH0 + MUXF_L2SW_LED_ON0 + MUXF_L2SW_P0_MAC_RMII_RXER + >; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml new file mode 100644 index 000000000..21f86740a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 SoC pin controller + +maintainers: + - Emil Renner Berthing <emil.renner.berthing@canonical.com> + +description: | + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. + + The TH1520 has 3 groups of pads each controlled from different memory ranges. + Confusingly the memory ranges are named + PADCTRL_AOSYS -> PAD Group 1 + PADCTRL1_APSYS -> PAD Group 2 + PADCTRL0_APSYS -> PAD Group 3 + + Each pad can be muxed individually to up to 6 different functions. For most + pads only a few of those 6 configurations are valid though, and a few pads in + group 1 does not support muxing at all. + + Pinconf is fairly regular except for a few pads in group 1 that either can't + be configured or has some special functions. The rest have configurable drive + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in + addition to a special strong pull up. + + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and + are then meant to be used by the audio co-processor. Each such pad can then + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is + also configured in different registers. All of this is done from a different + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. + +properties: + compatible: + enum: + - thead,th1520-pinctrl + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + thead,pad-group: + description: | + Select the pad group that is associated with the pin controller instance. + + Base Address Name Group + 0xFF_FFF4_A000 PADCTRL_AOSYS 1 + 0xFF_E7F3_C000 PADCTRL1_APSYS 2 + 0xFF_EC00_7000 PADCTRL0_APSYS 3 + + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + +required: + - compatible + - reg + - clocks + +patternProperties: + '-[0-9]+$': + type: object + additionalProperties: false + + patternProperties: + '-pins$': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode describing one + or more pads and their associated pinmux and pinconf settings. + + properties: + pins: + description: List of pads that properties in the node apply to. + + function: + enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, + gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, + clock, jtag, iso7816, efuse, reset ] + description: The mux function to select for the given pins. + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: Enable the regular 48kOhm pull-up + - enum: [ 2100, 48000 ] + description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up + + bias-pull-down: + oneOf: + - type: boolean + - const: 44000 + description: Enable the regular 44kOhm pull-down + + drive-strength: + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ] + description: Drive strength in mA + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + + required: + - pins + +additionalProperties: false + +examples: + - | + padctrl0_apsys: pinctrl@ec007000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xec007000 0x1000>; + clocks = <&apb_clk>; + thead,pad-group = <3>; + + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; + function = "uart"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "UART0_RXD"; + function = "uart"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; + + padctrl1_apsys: pinctrl@e7f3c000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xe7f3c000 0x1000>; + clocks = <&apb_clk>; + thead,pad-group = <2>; + + i2c5_pins: i2c5-0 { + i2c-pins { + pins = "QSPI1_CSN0", /* I2C5_SCL */ + "QSPI1_D0_MOSI"; /* I2C5_SDA */ + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt new file mode 100644 index 000000000..7f2980567 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,da850-pupd.txt @@ -0,0 +1,55 @@ +* Pin configuration for TI DA850/OMAP-L138/AM18x + +These SoCs have a separate controller for setting bias (internal pullup/down). +Bias can only be selected for groups rather than individual pins. + +Required Properties: + + - compatible: Must be "ti,da850-pupd" + - reg: Base address and length of the memory resource used by the pullup/down + controller hardware module. + +The controller node also acts as a container for pin group configuration nodes. +The names of these groups are ignored. + +Pin Group Node Properties: + +- groups: An array of strings, each string containing the name of a pin group. + Valid names are "cp0".."cp31". + +The pin configuration parameters use the generic pinconf bindings defined in +pinctrl-bindings.txt in this directory. The supported parameters are +bias-disable, bias-pull-up, bias-pull-down. + + +Example +------- + +In common dtsi file: + + pinconf: pin-controller@22c00c { + compatible = "ti,da850-pupd"; + reg = <0x22c00c 0x8>; + }; + +In board-specific file: + + &pinconf { + pinctrl-0 = <&pinconf_bias_groups>; + pinctrl-names = "default"; + + pinconf_bias_groups: bias-groups { + pull-up { + groups = "cp30", "cp31"; + bias-pull-up; + }; + pull-down { + groups = "cp29", "cp28"; + bias-pull-down; + }; + disable { + groups = "cp27", "cp26"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt new file mode 100644 index 000000000..c3ed1232b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ti,iodelay.txt @@ -0,0 +1,47 @@ +* Pin configuration for TI IODELAY controller + +TI dra7 based SoCs such as am57xx have a controller for setting the IO delay +for each pin. For most part the IO delay values are programmed by the bootloader, +but some pins need to be configured dynamically by the kernel such as the +MMC pins. + +Required Properties: + + - compatible: Must be "ti,dra7-iodelay" + - reg: Base address and length of the memory resource used + - #address-cells: Number of address cells + - #size-cells: Size of cells + - #pinctrl-cells: Number of pinctrl cells, must be 2. See also + Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt + +Example +------- + +In the SoC specific dtsi file: + + dra7_iodelay_core: padconf@4844a000 { + compatible = "ti,dra7-iodelay"; + reg = <0x4844a000 0x0d1c>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + }; + +In board-specific file: + +&dra7_iodelay_core { + mmc2_iodelay_3v3_conf: mmc2_iodelay_3v3_conf { + pinctrl-pin-array = < + 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */ + 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */ + 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */ + 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */ + 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */ + 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */ + 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */ + 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */ + 0x1f8 A_DELAY_PS(120) G_DELAY_PS(180) /* CFG_GPMC_A27_IN */ + 0x360 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_CS1_IN */ + >; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml new file mode 100644 index 000000000..0eff0a0ee --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti TMPV770x pin mux/config controller + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> + +description: + Toshiba's Visconti ARM SoC a pin mux/config controller. + +properties: + compatible: + enum: + - toshiba,tmpv7708-pinctrl + + reg: + maxItems: 1 + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + +patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength. + $ref: pinmux-node.yaml + additionalProperties: false + + properties: + function: + description: + Function to mux. + enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, + spi0, spi1, spi2, spi3, spi4, spi5, spi6, + uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] + + groups: + description: + Name of the pin group to use for the functions. + items: + enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, + i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp, + spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp, + spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp, + uart0_grp, uart1_grp, uart2_grp, uart3_grp, + pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp, + pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp, + pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp, + pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp, + pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp, + pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp] + minItems: 1 + maxItems: 8 + + drive-strength: + enum: [2, 4, 6, 8, 16, 24, 32] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-up: true + + bias-pull-down: true + + bias-disable: true + +additionalProperties: false + +examples: + # Pinmux controller node + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pmux: pinmux@24190000 { + compatible = "toshiba,tmpv7708-pinctrl"; + reg = <0 0x24190000 0 0x10000>; + + spi0_pins: spi0-pins { + function = "spi0"; + groups = "spi0_grp"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,pinctrl-zynq.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,pinctrl-zynq.yaml new file mode 100644 index 000000000..70548cb37 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,pinctrl-zynq.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/xlnx,pinctrl-zynq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynq Pinctrl + +maintainers: + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> + +description: | + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + Zynq's pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, slew rate, etc. + + Each configuration node can consist of multiple nodes describing the pinmux and + pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + +properties: + compatible: + const: xlnx,pinctrl-zynq + + reg: + description: Specifies the base address and size of the SLCR space. + maxItems: 1 + + syscon: + description: + phandle to the SLCR. + +patternProperties: + '^(.*-)?(default|gpio-grp)$': + type: object + patternProperties: + '^mux': + type: object + description: + Pinctrl node's client devices use subnodes for pin muxes, + which in turn use below standard properties. + $ref: pinmux-node.yaml# + + properties: + groups: + description: + List of groups to select (either this or "pins" must be + specified), available groups for this subnode. + items: + enum: [ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, + mdio1_0_grp, qspi0_0_grp, qspi1_0_grp, qspi_fbclk, + qspi_cs1_grp, spi0_0_grp, spi0_1_grp, spi0_2_grp, + spi0_0_ss0, spi0_0_ss1, spi0_0_ss2, spi0_1_ss0, + spi0_1_ss1, spi0_1_ss2, spi0_2_ss0, spi0_2_ss1, + spi0_2_ss2, spi1_0_grp, spi1_1_grp, spi1_2_grp, + spi1_3_grp, spi1_0_ss0, spi1_0_ss1, spi1_0_ss2, + spi1_1_ss0, spi1_1_ss1, spi1_1_ss2, spi1_2_ss0, + spi1_2_ss1, spi1_2_ss2, spi1_3_ss0, spi1_3_ss1, + spi1_3_ss2, sdio0_0_grp, sdio0_1_grp, sdio0_2_grp, + sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, sdio1_3_grp, + sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp, + sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, + smc0_nor_addr25_grp, smc0_nand, can0_0_grp, can0_1_grp, + can0_2_grp, can0_3_grp, can0_4_grp, can0_5_grp, + can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp, + can0_10_grp, can1_0_grp, can1_1_grp, can1_2_grp, + can1_3_grp, can1_4_grp, can1_5_grp, can1_6_grp, + can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp, + can1_11_grp, uart0_0_grp, uart0_1_grp, uart0_2_grp, + uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp, + uart0_7_grp, uart0_8_grp, uart0_9_grp, uart0_10_grp, + uart1_0_grp, uart1_1_grp, uart1_2_grp, uart1_3_grp, + uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp, + uart1_8_grp, uart1_9_grp, uart1_10_grp, uart1_11_grp, + i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp, + i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp, + i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, i2c1_0_grp, + i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, i2c1_4_grp, + i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp, + i2c1_9_grp, i2c1_10_grp, ttc0_0_grp, ttc0_1_grp, + ttc0_2_grp, ttc1_0_grp, ttc1_1_grp, ttc1_2_grp, + swdt0_0_grp, swdt0_1_grp, swdt0_2_grp, swdt0_3_grp, + swdt0_4_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp, + gpio0_3_grp, gpio0_4_grp, gpio0_5_grp, gpio0_6_grp, + gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, gpio0_10_grp, + gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp, + gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp, + gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, gpio0_22_grp, + gpio0_23_grp, gpio0_24_grp, gpio0_25_grp, gpio0_26_grp, + gpio0_27_grp, gpio0_28_grp, gpio0_29_grp, gpio0_30_grp, + gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, gpio0_34_grp, + gpio0_35_grp, gpio0_36_grp, gpio0_37_grp, gpio0_38_grp, + gpio0_39_grp, gpio0_40_grp, gpio0_41_grp, gpio0_42_grp, + gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, gpio0_46_grp, + gpio0_47_grp, gpio0_48_grp, gpio0_49_grp, gpio0_50_grp, + gpio0_51_grp, gpio0_52_grp, gpio0_53_grp, usb0_0_grp, + usb1_0_grp] + maxItems: 54 + + function: + description: + Specify the alternative function to be configured for the + given pin groups. + enum: [ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, + qspi_cs1, spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, + sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp, + smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, + can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, + usb0, usb1] + + required: + - groups + - function + + additionalProperties: false + + '^conf': + type: object + description: + Pinctrl node's client devices use subnodes for pin configurations, + which in turn use the standard properties below. + $ref: pincfg-node.yaml# + + properties: + groups: + description: + List of pin groups as mentioned above. + + pins: + description: + List of pin names to select in this subnode. + items: + pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$' + maxItems: 54 + + bias-pull-up: true + + bias-pull-down: true + + bias-disable: true + + bias-high-impedance: true + + low-power-enable: true + + low-power-disable: true + + slew-rate: + enum: [0, 1] + + power-source: + enum: [1, 2, 3, 4] + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - syscon + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-zynq.h> + pinctrl@700 { + compatible = "xlnx,pinctrl-zynq"; + reg = <0x700 0x200>; + syscon = <&slcr>; + + uart1-default { + mux { + groups = "uart1_10_grp"; + function = "uart1"; + }; + + conf { + groups = "uart1_10_grp"; + slew-rate = <0>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO49"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO48"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml new file mode 100644 index 000000000..81e2164ea --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,versal-pinctrl.yaml @@ -0,0 +1,279 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/xlnx,versal-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal Pinctrl + +maintainers: + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> + +description: | + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + Versal's pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, slew rate, etc. + + Each configuration node can consist of multiple nodes describing the pinmux and + pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + +properties: + compatible: + const: xlnx,versal-pinctrl + +patternProperties: + '^(.*-)?(default|gpio-grp)$': + type: object + patternProperties: + '^mux': + type: object + description: + Pinctrl node's client devices use subnodes for pin muxes, + which in turn use below standard properties. + $ref: pinmux-node.yaml# + + properties: + pins: + description: + List of pins to select (either this or "groups" must be specified) + $ref: "#/$defs/pins/properties/pins" + + groups: + description: + List of groups to select (either this or "pins" must be + specified), available groups for this subnode. + anyOf: + - pattern: '^((LPD|PMC)_)MIO([0-9]|[1-6][0-9]|7[0-7])$' + - $ref: "#/$defs/pins/properties/groups" + + function: + description: + Specify the alternative function to be configured for the + given pin groups. + enum: [spi0, spi0_ss, spi1, spi1_ss, can0, can1, i2c0, i2c1, i2c_pmc, ttc0_clk, + ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav, ttc3_clk, ttc3_wav, wwdt0, + wwdt1, sysmon_i2c0, sysmon_i2c0_alrt, uart0, uart0_ctrl, uart1, uart1_ctrl, + gpio0, gpio1, gpio2, emio0, gem0, gem1, trace0, trace0_clk, mdio0, mdio1, gem_tsu0, + pcie0, smap0, usb0, sd0, sd0_pc, sd0_cd, sd0_wp, sd1, sd1_pc, sd1_wp, sd1_cd, + ospi0, ospi0_ss, qspi0, qspi0_fbclk, qspi0_ss, test_clk, test_scan, tamper_trigger] + + required: + - function + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + + '^conf': + type: object + unevaluatedProperties: false + description: + Pinctrl node's client devices use subnodes for pin configurations, + which in turn use the standard properties below. + allOf: + - $ref: pincfg-node.yaml# + - $ref: "#/$defs/pins" + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +$defs: + pins: + properties: + groups: + description: + List of pin groups to select in this subnode. + items: + enum: [spi0_0_grp, spi0_1_grp, spi0_2_grp, spi0_3_grp, spi0_4_grp, spi0_5_grp, + spi0_ss_0_grp, spi0_ss_1_grp, spi0_ss_2_grp, spi0_ss_3_grp, spi0_ss_4_grp, + spi0_ss_5_grp, spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp, spi0_ss_9_grp, + spi0_ss_10_grp, spi0_ss_11_grp, spi0_ss_12_grp, spi0_ss_13_grp, spi0_ss_14_grp, + spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp, spi1_0_grp, spi1_1_grp, + spi1_2_grp, spi1_3_grp, spi1_4_grp, spi1_5_grp, spi1_ss_0_grp, spi1_ss_1_grp, + spi1_ss_2_grp, spi1_ss_3_grp, spi1_ss_4_grp, spi1_ss_5_grp, spi1_ss_6_grp, + spi1_ss_7_grp, spi1_ss_8_grp, spi1_ss_9_grp, spi1_ss_10_grp, spi1_ss_11_grp, + spi1_ss_12_grp, spi1_ss_13_grp, spi1_ss_14_grp, spi1_ss_15_grp, spi1_ss_16_grp + spi1_ss_17_grp, can0_0_grp, can0_1_grp, can0_2_grp, can0_3_grp, can0_4_grp, + can0_5_grp, can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp, can0_10_grp, + can0_11_grp, can0_12_grp, can0_13_grp, can0_14_grp, can0_15_grp, can0_16_grp, + can0_17_grp, can1_0_grp, can1_1_grp, can1_2_grp, can1_3_grp, can1_4_grp, + can1_5_grp, can1_6_grp, can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp, + can1_11_grp, can1_12_grp, can1_13_grp, can1_14_grp, can1_15_grp, can1_16_grp, + can1_17_grp, can1_18_grp, i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp, + i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp, i2c0_8_grp, i2c0_9_grp, + i2c0_10_grp, i2c0_11_grp, i2c0_12_grp, i2c0_13_grp, i2c0_14_grp, i2c0_15_grp, + i2c0_16_grp, i2c0_17_grp, i2c1_0_grp, i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, + i2c1_4_grp, i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp, i2c1_9_grp, + i2c1_10_grp, i2c1_11_grp, i2c1_12_grp, i2c1_13_grp, i2c1_14_grp, i2c1_15_grp, + i2c1_16_grp, i2c1_17_grp, i2c1_18_grp, i2c_pmc_0_grp, i2c_pmc_1_grp, + i2c_pmc_2_grp, i2c_pmc_3_grp, i2c_pmc_4_grp, i2c_pmc_5_grp, i2c_pmc_6_grp, + i2c_pmc_7_grp, i2c_pmc_8_grp, i2c_pmc_9_grp, i2c_pmc_10_grp, i2c_pmc_11_grp, + i2c_pmc_12_grp, ttc0_clk_0_grp, ttc0_clk_1_grp, ttc0_clk_2_grp, ttc0_clk_3_grp, + ttc0_clk_4_grp, ttc0_clk_5_grp, ttc0_clk_6_grp, ttc0_clk_7_grp, ttc0_clk_8_grp, + ttc0_wav_0_grp, ttc0_wav_1_grp, ttc0_wav_2_grp, ttc0_wav_3_grp, ttc0_wav_4_grp, + ttc0_wav_5_grp, ttc0_wav_6_grp, ttc0_wav_7_grp, ttc0_wav_8_grp, ttc1_clk_0_grp, + ttc1_clk_1_grp, ttc1_clk_2_grp, ttc1_clk_3_grp, ttc1_clk_4_grp, ttc1_clk_5_grp, + ttc1_clk_6_grp, ttc1_clk_7_grp, ttc1_clk_8_grp, ttc1_wav_0_grp, ttc1_wav_1_grp, + ttc1_wav_2_grp, ttc1_wav_3_grp, ttc1_wav_4_grp, ttc1_wav_5_grp, ttc1_wav_6_grp, + ttc1_wav_7_grp, ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_clk_1_grp, ttc2_clk_2_grp, + ttc2_clk_3_grp, ttc2_clk_4_grp, ttc2_clk_5_grp, ttc2_clk_6_grp, ttc2_clk_7_grp, + ttc2_clk_8_grp, ttc2_wav_0_grp, ttc2_wav_1_grp, ttc2_wav_2_grp, ttc2_wav_3_grp, + ttc2_wav_4_grp, ttc2_wav_5_grp, ttc2_wav_6_grp, ttc2_wav_7_grp, ttc2_wav_8_grp, + ttc3_clk_0_grp, ttc3_clk_1_grp, ttc3_clk_2_grp, ttc3_clk_3_grp, ttc3_clk_4_grp, + ttc3_clk_5_grp, ttc3_clk_6_grp, ttc3_clk_7_grp, ttc3_clk_8_grp, ttc3_wav_0_grp, + ttc3_wav_1_grp, ttc3_wav_2_grp, ttc3_wav_3_grp, ttc3_wav_4_grp, ttc3_wav_5_grp, + ttc3_wav_6_grp, ttc3_wav_7_grp, ttc3_wav_8_grp, wwdt0_0_grp, wwdt0_1_grp, + wwdt0_2_grp, wwdt0_3_grp, wwdt0_4_grp, wwdt0_5_grp, wwdt1_0_grp, wwdt1_1_grp, + wwdt1_2_grp, wwdt1_3_grp, wwdt1_4_grp, wwdt1_5_grp, sysmon_i2c0_0_grp, + sysmon_i2c0_1_grp, sysmon_i2c0_2_grp, sysmon_i2c0_3_grp, sysmon_i2c0_4_grp, + sysmon_i2c0_5_grp, sysmon_i2c0_6_grp, sysmon_i2c0_7_grp, sysmon_i2c0_8_grp, + sysmon_i2c0_9_grp, sysmon_i2c0_10_grp, sysmon_i2c0_11_grp, sysmon_i2c0_12_grp, + sysmon_i2c0_13_grp, sysmon_i2c0_14_grp, sysmon_i2c0_15_grp, + sysmon_i2c0_16_grp, sysmon_i2c0_17_grp, sysmon_i2c0_alrt_0_grp, + sysmon_i2c0_alrt_1_grp, sysmon_i2c0_alrt_2_grp, sysmon_i2c0_alrt_3_grp, + sysmon_i2c0_alrt_4_grp, sysmon_i2c0_alrt_5_grp, sysmon_i2c0_alrt_6_grp, + sysmon_i2c0_alrt_7_grp, sysmon_i2c0_alrt_8_grp, sysmon_i2c0_alrt_9_grp, + sysmon_i2c0_alrt_10_grp, sysmon_i2c0_alrt_11_grp, sysmon_i2c0_alrt_12_grp, + sysmon_i2c0_alrt_13_grp, sysmon_i2c0_alrt_14_grp, sysmon_i2c0_alrt_15_grp, + sysmon_i2c0_alrt_16_grp, sysmon_i2c0_alrt_17_grp, uart0_0_grp, uart0_1_grp, + uart0_2_grp, uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp, uart0_7_grp, + uart0_8_grp, uart0_ctrl_0_grp, uart0_ctrl_1_grp, uart0_ctrl_2_grp, + uart0_ctrl_3_grp, uart0_ctrl_4_grp, uart0_ctrl_5_grp, uart0_ctrl_6_grp, + uart0_ctrl_7_grp, uart0_ctrl_8_grp, uart1_0_grp, uart1_1_grp, uart1_2_grp, + uart1_3_grp, uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp, uart1_8_grp, + uart1_ctrl_0_grp, uart1_ctrl_1_grp, uart1_ctrl_2_grp, uart1_ctrl_3_grp, + uart1_ctrl_4_grp, uart1_ctrl_5_grp, uart1_ctrl_6_grp, uart1_ctrl_7_grp, + uart1_ctrl_8_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp, gpio0_3_grp, + gpio0_4_grp, gpio0_5_grp, gpio0_6_grp, gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, + gpio0_10_grp, gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp, + gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp, gpio0_19_grp, + gpio0_20_grp, gpio0_21_grp, gpio0_22_grp, gpio0_23_grp, gpio0_24_grp, + gpio0_25_grp, gpio1_0_grp, gpio1_1_grp, gpio1_2_grp, gpio1_3_grp, gpio1_4_grp, + gpio1_5_grp, gpio1_6_grp, gpio1_7_grp, gpio1_8_grp, gpio1_9_grp, + gpio1_10_grp, gpio1_11_grp, gpio1_12_grp, gpio1_13_grp, gpio1_14_grp, + gpio1_15_grp, gpio1_16_grp, gpio1_17_grp, gpio1_18_grp, gpio1_19_grp, + gpio1_20_grp, gpio1_21_grp, gpio1_22_grp, gpio1_23_grp, gpio1_24_grp, + gpio1_25_grp, gpio2_0_grp, gpio2_1_grp, gpio2_2_grp, gpio2_3_grp, gpio2_4_grp, + gpio2_5_grp, gpio2_6_grp, gpio2_7_grp, gpio2_8_grp, gpio2_9_grp, gpio2_10_grp, + gpio2_11_grp, gpio2_12_grp, gpio2_13_grp, gpio2_14_grp, gpio2_15_grp, + gpio2_16_grp, gpio2_17_grp, gpio2_18_grp, gpio2_19_grp, gpio2_20_grp, + gpio2_21_grp, gpio2_22_grp, gpio2_23_grp, gpio2_24_grp, gpio2_25_grp, + emio0_0_grp, emio0_1_grp, emio0_2_grp, emio0_3_grp, emio0_4_grp, emio0_5_grp, + emio0_6_grp, emio0_7_grp, emio0_8_grp, emio0_9_grp, emio0_10_grp, + emio0_11_grp, emio0_12_grp, emio0_13_grp, emio0_14_grp, emio0_15_grp, + emio0_16_grp, emio0_17_grp, emio0_18_grp, emio0_19_grp, emio0_20_grp, + emio0_21_grp, emio0_22_grp, emio0_23_grp, emio0_24_grp, emio0_25_grp, + emio0_26_grp, emio0_27_grp, emio0_28_grp, emio0_29_grp, emio0_30_grp, + emio0_31_grp, emio0_32_grp, emio0_33_grp, emio0_34_grp, emio0_35_grp, + emio0_36_grp, emio0_37_grp, emio0_38_grp, emio0_39_grp, emio0_40_grp, + emio0_41_grp, emio0_42_grp, emio0_43_grp, emio0_44_grp, emio0_45_grp, + emio0_46_grp, emio0_47_grp, emio0_48_grp, emio0_49_grp, emio0_50_grp, + emio0_51_grp, emio0_52_grp, emio0_53_grp, emio0_54_grp, emio0_55_grp, + emio0_56_grp, emio0_57_grp, emio0_58_grp, emio0_59_grp, emio0_60_grp, + emio0_61_grp, emio0_62_grp, emio0_63_grp, emio0_64_grp, emio0_65_grp, + emio0_66_grp, emio0_67_grp, emio0_68_grp, emio0_69_grp, emio0_70_grp, + emio0_71_grp, emio0_72_grp, emio0_73_grp, emio0_74_grp, emio0_75_grp, + emio0_76_grp, emio0_77_grp, gem0_0_grp, gem0_1_grp, gem1_0_grp, gem1_1_grp, + trace0_0_grp, trace0_1_grp, trace0_2_grp, trace0_clk_0_grp, trace0_clk_1_grp, + trace0_clk_2_grp, mdio0_0_grp, mdio0_1_grp, mdio1_0_grp, mdio1_1_grp, + gem_tsu0_0_grp, gem_tsu0_1_grp, gem_tsu0_2_grp, gem_tsu0_3_grp, pcie0_0_grp, + pcie0_1_grp, pcie0_2_grp, smap0_0_grp, usb0_0_grp, sd0_0_grp, sd0_1_grp, + sd0_2_grp, sd0_3_grp, sd0_4_grp, sd0_5_grp, sd0_6_grp, sd0_7_grp, sd0_8_grp, + sd0_9_grp, sd0_10_grp, sd0_11_grp, sd0_12_grp, sd0_13_grp, sd0_14_grp, + sd0_15_grp, sd0_16_grp, sd0_17_grp, sd0_18_grp, sd0_19_grp, sd0_20_grp, + sd0_21_grp, sd0_pc_0_grp, sd0_pc_1_grp, sd0_cd_0_grp, sd0_cd_1_grp, + sd0_wp_0_grp, sd0_wp_1_grp, sd1_0_grp, sd1_1_grp, sd1_2_grp, sd1_3_grp, + sd1_4_grp, sd1_5_grp, sd1_6_grp, sd1_7_grp, sd1_8_grp, sd1_9_grp, sd1_10_grp, + sd1_11_grp, sd1_12_grp, sd1_13_grp, sd1_14_grp, sd1_15_grp, sd1_16_grp, + sd1_17_grp, sd1_18_grp, sd1_19_grp, sd1_20_grp, sd1_21_grp, sd1_pc_0_grp, + sd1_pc_1_grp, sd1_cd_0_grp, sd1_cd_1_grp, sd1_wp_0_grp, sd1_wp_1_grp, + ospi0_0_grp, ospi0_ss_0_grp, qspi0_0_grp, qspi0_fbclk_0_grp, qspi0_ss_0_grp, + test_clk_0_grp, test_scan_0_grp, tamper_trigger_0_grp] + minItems: 1 + maxItems: 78 + + pins: + description: + List of pin names to select in this subnode. + items: + pattern: '^((LPD|PMC)_)MIO([0-9]|[1-6][0-9]|7[0-7])$' + minItems: 1 + maxItems: 78 + + bias-pull-up: true + bias-pull-down: true + bias-disable: true + input-schmitt-enable: true + input-schmitt-disable: true + bias-high-impedance: true + low-power-enable: true + low-power-disable: true + + slew-rate: + enum: [0, 1] + + output-enable: + description: + This will internally disable the tri-state for MIO pins. + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 8, 12] + + power-source: + enum: [0, 1] + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + pinctrl { + compatible = "xlnx,versal-pinctrl"; + + uart0-default { + mux { + groups = "uart0_4_grp", "uart0_5_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "PMC_MIO42"; + bias-pull-up; + }; + + conf-tx { + pins = "PMC_MIO43"; + bias-disable; + input-schmitt-disable; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml new file mode 100644 index 000000000..ce66fd15f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -0,0 +1,353 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/xlnx,zynqmp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx ZynqMP Pinctrl + +maintainers: + - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> + +description: | + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + ZynqMP's pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, slew rate, etc. + + Each configuration node can consist of multiple nodes describing the pinmux and + pinconf options. Those nodes can be pinmux nodes or pinconf nodes. + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + +properties: + compatible: + const: xlnx,zynqmp-pinctrl + +patternProperties: + '^(.*-)?(default|gpio-grp)$': + type: object + patternProperties: + '^mux': + type: object + description: + Pinctrl node's client devices use subnodes for pin muxes, + which in turn use below standard properties. + $ref: pinmux-node.yaml# + + properties: + pins: + description: + List of pins to select (either this or "groups" must be specified) + items: + pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$' + + groups: + description: + List of groups to select (either this or "pins" must be + specified), available groups for this subnode. + items: + anyOf: + - pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$' + - enum: [ethernet0_0_grp, ethernet1_0_grp, ethernet2_0_grp, + ethernet3_0_grp, gemtsu0_0_grp, gemtsu0_1_grp, + gemtsu0_2_grp, mdio0_0_grp, mdio1_0_grp, + mdio1_1_grp, mdio2_0_grp, mdio3_0_grp, + qspi0_0_grp, qspi_ss_0_grp, qspi_fbclk_0_grp, + spi0_0_grp, spi0_ss_0_grp, spi0_ss_1_grp, + spi0_ss_2_grp, spi0_1_grp, spi0_ss_3_grp, + spi0_ss_4_grp, spi0_ss_5_grp, spi0_2_grp, + spi0_ss_6_grp, spi0_ss_7_grp, spi0_ss_8_grp, + spi0_3_grp, spi0_ss_9_grp, spi0_ss_10_grp, + spi0_ss_11_grp, spi0_4_grp, spi0_ss_12_grp, + spi0_ss_13_grp, spi0_ss_14_grp, spi0_5_grp, + spi0_ss_15_grp, spi0_ss_16_grp, spi0_ss_17_grp, + spi1_0_grp, spi1_ss_0_grp, spi1_ss_1_grp, + spi1_ss_2_grp, spi1_1_grp, spi1_ss_3_grp, + spi1_ss_4_grp, spi1_ss_5_grp, spi1_2_grp, + spi1_ss_6_grp, spi1_ss_7_grp, spi1_ss_8_grp, + spi1_3_grp, spi1_ss_9_grp, spi1_ss_10_grp, + spi1_ss_11_grp, spi1_4_grp, spi1_ss_12_grp, + spi1_ss_13_grp, spi1_ss_14_grp, spi1_5_grp, + spi1_ss_15_grp, spi1_ss_16_grp, spi1_ss_17_grp, + sdio0_0_grp, sdio0_1_grp, sdio0_2_grp, + sdio0_3_grp, sdio0_4_grp, sdio0_5_grp, + sdio0_6_grp, sdio0_7_grp, sdio0_8_grp, + sdio0_9_grp, sdio0_10_grp, sdio0_11_grp, + sdio0_12_grp, sdio0_13_grp, sdio0_14_grp, + sdio0_15_grp, sdio0_16_grp, sdio0_17_grp, + sdio0_18_grp, sdio0_19_grp, sdio0_20_grp, + sdio0_21_grp, sdio0_22_grp, sdio0_23_grp, + sdio0_24_grp, sdio0_25_grp, sdio0_26_grp, + sdio0_27_grp, sdio0_28_grp, sdio0_29_grp, + sdio0_30_grp, sdio0_31_grp, sdio0_32_grp, + sdio0_pc_0_grp, sdio0_cd_0_grp, sdio0_wp_0_grp, + sdio0_pc_1_grp, sdio0_cd_1_grp, sdio0_wp_1_grp, + sdio0_pc_2_grp, sdio0_cd_2_grp, sdio0_wp_2_grp, + sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, + sdio1_3_grp, sdio1_4_grp, sdio1_5_grp, + sdio1_6_grp, sdio1_7_grp, sdio1_8_grp, + sdio1_9_grp, sdio1_10_grp, sdio1_11_grp, + sdio1_12_grp, sdio1_13_grp, sdio1_14_grp, + sdio1_15_grp, sdio1_pc_0_grp, sdio1_cd_0_grp, + sdio1_wp_0_grp, sdio1_pc_1_grp, sdio1_cd_1_grp, + sdio1_wp_1_grp, nand0_0_grp, nand0_ce_0_grp, + nand0_rb_0_grp, nand0_dqs_0_grp, nand0_ce_1_grp, + nand0_rb_1_grp, nand0_dqs_1_grp, can0_0_grp, + can0_1_grp, can0_2_grp, can0_3_grp, + can0_4_grp, can0_5_grp, can0_6_grp, + can0_7_grp, can0_8_grp, can0_9_grp, + can0_10_grp, can0_11_grp, can0_12_grp, + can0_13_grp, can0_14_grp, can0_15_grp, + can0_16_grp, can0_17_grp, can0_18_grp, + can1_0_grp, can1_1_grp, can1_2_grp, + can1_3_grp, can1_4_grp, can1_5_grp, + can1_6_grp, can1_7_grp, can1_8_grp, + can1_9_grp, can1_10_grp, can1_11_grp, + can1_12_grp, can1_13_grp, can1_14_grp, + can1_15_grp, can1_16_grp, can1_17_grp, + can1_18_grp, can1_19_grp, uart0_0_grp, + uart0_1_grp, uart0_2_grp, uart0_3_grp, + uart0_4_grp, uart0_5_grp, uart0_6_grp, + uart0_7_grp, uart0_8_grp, uart0_9_grp, + uart0_10_grp, uart0_11_grp, uart0_12_grp, + uart0_13_grp, uart0_14_grp, uart0_15_grp, + uart0_16_grp, uart0_17_grp, uart0_18_grp, + uart1_0_grp, uart1_1_grp, uart1_2_grp, + uart1_3_grp, uart1_4_grp, uart1_5_grp, + uart1_6_grp, uart1_7_grp, uart1_8_grp, + uart1_9_grp, uart1_10_grp, uart1_11_grp, + uart1_12_grp, uart1_13_grp, uart1_14_grp, + uart1_15_grp, uart1_16_grp, uart1_17_grp, + uart1_18_grp, i2c0_0_grp, i2c0_1_grp, + i2c0_2_grp, i2c0_3_grp, i2c0_4_grp, + i2c0_5_grp, i2c0_6_grp, i2c0_7_grp, + i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, + i2c0_11_grp, i2c0_12_grp, i2c0_13_grp, + i2c0_14_grp, i2c0_15_grp, i2c0_16_grp, + i2c0_17_grp, i2c0_18_grp, i2c1_0_grp, + i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, + i2c1_4_grp, i2c1_5_grp, i2c1_6_grp, + i2c1_7_grp, i2c1_8_grp, i2c1_9_grp, + i2c1_10_grp, i2c1_11_grp, i2c1_12_grp, + i2c1_13_grp, i2c1_14_grp, i2c1_15_grp, + i2c1_16_grp, i2c1_17_grp, i2c1_18_grp, + i2c1_19_grp, ttc0_clk_0_grp, ttc0_wav_0_grp, + ttc0_clk_1_grp, ttc0_wav_1_grp, ttc0_clk_2_grp, + ttc0_wav_2_grp, ttc0_clk_3_grp, ttc0_wav_3_grp, + ttc0_clk_4_grp, ttc0_wav_4_grp, ttc0_clk_5_grp, + ttc0_wav_5_grp, ttc0_clk_6_grp, ttc0_wav_6_grp, + ttc0_clk_7_grp, ttc0_wav_7_grp, ttc0_clk_8_grp, + ttc0_wav_8_grp, ttc1_clk_0_grp, ttc1_wav_0_grp, + ttc1_clk_1_grp, ttc1_wav_1_grp, ttc1_clk_2_grp, + ttc1_wav_2_grp, ttc1_clk_3_grp, ttc1_wav_3_grp, + ttc1_clk_4_grp, ttc1_wav_4_grp, ttc1_clk_5_grp, + ttc1_wav_5_grp, ttc1_clk_6_grp, ttc1_wav_6_grp, + ttc1_clk_7_grp, ttc1_wav_7_grp, ttc1_clk_8_grp, + ttc1_wav_8_grp, ttc2_clk_0_grp, ttc2_wav_0_grp, + ttc2_clk_1_grp, ttc2_wav_1_grp, ttc2_clk_2_grp, + ttc2_wav_2_grp, ttc2_clk_3_grp, ttc2_wav_3_grp, + ttc2_clk_4_grp, ttc2_wav_4_grp, ttc2_clk_5_grp, + ttc2_wav_5_grp, ttc2_clk_6_grp, ttc2_wav_6_grp, + ttc2_clk_7_grp, ttc2_wav_7_grp, ttc2_clk_8_grp, + ttc2_wav_8_grp, ttc3_clk_0_grp, ttc3_wav_0_grp, + ttc3_clk_1_grp, ttc3_wav_1_grp, ttc3_clk_2_grp, + ttc3_wav_2_grp, ttc3_clk_3_grp, ttc3_wav_3_grp, + ttc3_clk_4_grp, ttc3_wav_4_grp, ttc3_clk_5_grp, + ttc3_wav_5_grp, ttc3_clk_6_grp, ttc3_wav_6_grp, + ttc3_clk_7_grp, ttc3_wav_7_grp, ttc3_clk_8_grp, + ttc3_wav_8_grp, swdt0_clk_0_grp, swdt0_rst_0_grp, + swdt0_clk_1_grp, swdt0_rst_1_grp, swdt0_clk_2_grp, + swdt0_rst_2_grp, swdt0_clk_3_grp, swdt0_rst_3_grp, + swdt0_clk_4_grp, swdt0_rst_4_grp, swdt0_clk_5_grp, + swdt0_rst_5_grp, swdt0_clk_6_grp, swdt0_rst_6_grp, + swdt0_clk_7_grp, swdt0_rst_7_grp, swdt0_clk_8_grp, + swdt0_rst_8_grp, swdt0_clk_9_grp, swdt0_rst_9_grp, + swdt0_clk_10_grp, swdt0_rst_10_grp, swdt0_clk_11_grp, + swdt0_rst_11_grp, swdt0_clk_12_grp, swdt0_rst_12_grp, + swdt1_clk_0_grp, swdt1_rst_0_grp, swdt1_clk_1_grp, + swdt1_rst_1_grp, swdt1_clk_2_grp, swdt1_rst_2_grp, + swdt1_clk_3_grp, swdt1_rst_3_grp, swdt1_clk_4_grp, + swdt1_rst_4_grp, swdt1_clk_5_grp, swdt1_rst_5_grp, + swdt1_clk_6_grp, swdt1_rst_6_grp, swdt1_clk_7_grp, + swdt1_rst_7_grp, swdt1_clk_8_grp, swdt1_rst_8_grp, + swdt1_clk_9_grp, swdt1_rst_9_grp, swdt1_clk_10_grp, + swdt1_rst_10_grp, swdt1_clk_11_grp, swdt1_rst_11_grp, + swdt1_clk_12_grp, swdt1_rst_12_grp, gpio0_0_grp, + gpio0_1_grp, gpio0_2_grp, gpio0_3_grp, + gpio0_4_grp, gpio0_5_grp, gpio0_6_grp, + gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, + gpio0_10_grp, gpio0_11_grp, gpio0_12_grp, + gpio0_13_grp, gpio0_14_grp, gpio0_15_grp, + gpio0_16_grp, gpio0_17_grp, gpio0_18_grp, + gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, + gpio0_22_grp, gpio0_23_grp, gpio0_24_grp, + gpio0_25_grp, gpio0_26_grp, gpio0_27_grp, + gpio0_28_grp, gpio0_29_grp, gpio0_30_grp, + gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, + gpio0_34_grp, gpio0_35_grp, gpio0_36_grp, + gpio0_37_grp, gpio0_38_grp, gpio0_39_grp, + gpio0_40_grp, gpio0_41_grp, gpio0_42_grp, + gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, + gpio0_46_grp, gpio0_47_grp, gpio0_48_grp, + gpio0_49_grp, gpio0_50_grp, gpio0_51_grp, + gpio0_52_grp, gpio0_53_grp, gpio0_54_grp, + gpio0_55_grp, gpio0_56_grp, gpio0_57_grp, + gpio0_58_grp, gpio0_59_grp, gpio0_60_grp, + gpio0_61_grp, gpio0_62_grp, gpio0_63_grp, + gpio0_64_grp, gpio0_65_grp, gpio0_66_grp, + gpio0_67_grp, gpio0_68_grp, gpio0_69_grp, + gpio0_70_grp, gpio0_71_grp, gpio0_72_grp, + gpio0_73_grp, gpio0_74_grp, gpio0_75_grp, + gpio0_76_grp, gpio0_77_grp, usb0_0_grp, + usb1_0_grp, pmu0_0_grp, pmu0_1_grp, + pmu0_2_grp, pmu0_3_grp, pmu0_4_grp, + pmu0_5_grp, pmu0_6_grp, pmu0_7_grp, + pmu0_8_grp, pmu0_9_grp, pmu0_10_grp, + pmu0_11_grp, pcie0_0_grp, pcie0_1_grp, + pcie0_2_grp, pcie0_3_grp, pcie0_4_grp, + pcie0_5_grp, pcie0_6_grp, pcie0_7_grp, + csu0_0_grp, csu0_1_grp, csu0_2_grp, + csu0_3_grp, csu0_4_grp, csu0_5_grp, + csu0_6_grp, csu0_7_grp, csu0_8_grp, + csu0_9_grp, csu0_10_grp, csu0_11_grp, + dpaux0_0_grp, dpaux0_1_grp, dpaux0_2_grp, + dpaux0_3_grp, pjtag0_0_grp, pjtag0_1_grp, + pjtag0_2_grp, pjtag0_3_grp, pjtag0_4_grp, + pjtag0_5_grp, trace0_0_grp, trace0_clk_0_grp, + trace0_1_grp, trace0_clk_1_grp, trace0_2_grp, + trace0_clk_2_grp, testscan0_0_grp] + maxItems: 78 + + function: + description: + Specify the alternative function to be configured for the + given pin groups. + enum: [ethernet0, ethernet1, ethernet2, ethernet3, gemtsu0, usb0, usb1, mdio0, + mdio1, mdio2, mdio3, qspi0, qspi_fbclk, qspi_ss, spi0, spi1, spi0_ss, + spi1_ss, sdio0, sdio0_pc, sdio0_wp, sdio0_cd, sdio1, sdio1_pc, sdio1_wp, + sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1, + i2c0, i2c1, ttc0_clk, ttc0_wav, ttc1_clk, ttc1_wav, ttc2_clk, ttc2_wav, + ttc3_clk, ttc3_wav, swdt0_clk, swdt0_rst, swdt1_clk, swdt1_rst, gpio0, pmu0, + pcie0, csu0, dpaux0, pjtag0, trace0, trace0_clk, testscan0] + + required: + - function + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + + '^conf': + type: object + description: + Pinctrl node's client devices use subnodes for pin configurations, + which in turn use the standard properties below. + $ref: pincfg-node.yaml# + + properties: + groups: + description: + List of pin groups as mentioned above. + + pins: + description: + List of pin names to select in this subnode. + items: + pattern: '^MIO([0-9]|[1-6][0-9]|7[0-7])$' + maxItems: 78 + + bias-pull-up: true + + bias-pull-down: true + + bias-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + bias-high-impedance: true + + low-power-enable: true + + low-power-disable: true + + slew-rate: + enum: [0, 1] + + output-enable: + description: + This will internally disable the tri-state for MIO pins. + + drive-strength: + description: + Selects the drive strength for MIO pins, in mA. + enum: [2, 4, 8, 12] + + power-source: + enum: [0, 1] + + oneOf: + - required: [ groups ] + - required: [ pins ] + + additionalProperties: false + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + zynqmp_firmware: zynqmp-firmware { + pinctrl0: pinctrl { + compatible = "xlnx,zynqmp-pinctrl"; + + pinctrl_uart1_default: uart1-default { + mux { + groups = "uart0_4_grp", "uart0_5_grp"; + function = "uart0"; + }; + + conf { + groups = "uart0_4_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO18"; + bias-pull-up; + }; + + conf-tx { + pins = "MIO19"; + bias-disable; + input-schmitt-disable; + }; + }; + }; + }; + + uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + }; + +... |