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authorLinus Walleij <linusw@kernel.org>2026-06-30 18:05:56 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2026-08-05 16:48:11 +0100
commitbb3b2cfeb206f5b10b859e134651b54120e3f530 (patch)
tree6717fcea088ba5c5f15002a48101fa2537135bf2 /tools/perf/util/cacheline.h
downloadlinux-stable-bb3b2cfeb206f5b10b859e134651b54120e3f530.tar.gz
linux-stable-bb3b2cfeb206f5b10b859e134651b54120e3f530.zip
ARM: 9480/1: entry: expand comment in __switch_tografted
As per discussion between the developers in the mail thread linked, expand the comment in __switch_to so that readers of the code understand what is going on. Suggested-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Linus Walleij <linusw@kernel.org>> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'tools/perf/util/cacheline.h')
-rw-r--r--tools/perf/util/cacheline.h36
1 files changed, 36 insertions, 0 deletions
diff --git a/tools/perf/util/cacheline.h b/tools/perf/util/cacheline.h
new file mode 100644
index 000000000..fe6d5b60a
--- /dev/null
+++ b/tools/perf/util/cacheline.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef PERF_CACHELINE_H
+#define PERF_CACHELINE_H
+
+#include <linux/compiler.h>
+
+int __pure cacheline_size(void);
+
+
+/*
+ * Some architectures have 'Adjacent Cacheline Prefetch' feature,
+ * which performs like the cacheline size being doubled.
+ */
+static inline u64 cl_address(u64 address, bool double_cl)
+{
+ u64 size = cacheline_size();
+
+ if (double_cl)
+ size *= 2;
+
+ /* return the cacheline of the address */
+ return (address & ~(size - 1));
+}
+
+static inline u64 cl_offset(u64 address, bool double_cl)
+{
+ u64 size = cacheline_size();
+
+ if (double_cl)
+ size *= 2;
+
+ /* return the offset inside cacheline */
+ return (address & (size - 1));
+}
+
+#endif // PERF_CACHELINE_H