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| author | Linus Walleij <linusw@kernel.org> | 2026-06-30 18:05:56 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2026-08-05 16:48:11 +0100 |
| commit | bb3b2cfeb206f5b10b859e134651b54120e3f530 (patch) | |
| tree | 6717fcea088ba5c5f15002a48101fa2537135bf2 /tools/perf/util/cacheline.c | |
| download | linux-stable-bb3b2cfeb206f5b10b859e134651b54120e3f530.tar.gz linux-stable-bb3b2cfeb206f5b10b859e134651b54120e3f530.zip | |
ARM: 9480/1: entry: expand comment in __switch_tografted
As per discussion between the developers in the mail thread
linked, expand the comment in __switch_to so that readers
of the code understand what is going on.
Suggested-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'tools/perf/util/cacheline.c')
| -rw-r--r-- | tools/perf/util/cacheline.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tools/perf/util/cacheline.c b/tools/perf/util/cacheline.c new file mode 100644 index 000000000..e98b5250a --- /dev/null +++ b/tools/perf/util/cacheline.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "cacheline.h" +#include <unistd.h> + +#ifdef _SC_LEVEL1_DCACHE_LINESIZE +#define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE) +#else +#include <api/fs/fs.h> +#include "debug.h" +static void cache_line_size(int *cacheline_sizep) +{ + if (sysfs__read_int("devices/system/cpu/cpu0/cache/index0/coherency_line_size", cacheline_sizep)) + pr_debug("cannot determine cache line size"); +} +#endif + +int cacheline_size(void) +{ + static int size; + + if (!size) + cache_line_size(&size); + + return size; +} |
