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authorLinus Torvalds <torvalds@linux-foundation.org>2026-08-24 08:46:03 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2026-08-24 08:46:03 -0700
commitcf9610f9116d55c5a66ef9f1faecacabd93a9322 (patch)
tree757a3d280760c654767631cab5ad8af2d86d1848 /tools/include/nolibc/arch-alpha.h
downloadlinux-stable-cf9610f9116d55c5a66ef9f1faecacabd93a9322.tar.gz
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Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlgrafted
Pull pin control updates from Linus Walleij: "Core changes: - Use the non-blocking mux_state_try_select() in the generic MUX pin control back-end - Free pin maps on pinctrl_generic_to_map() failure in the core helpers New hardware pin control: - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC (this is for the low power audio, LPASS = Low Power Audio SubSystem portions) - Upboard support on top of the Intel pin controller - Apple T6030 and T6031 support (just compatible strings) - Samsung Exynos 8855 SoC - Mediatek MT6858 SoC - Rockchip RK3308B and RV1106 SoCs - Airoha EN7523 and AN7563 SoCs Improvements: - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable - Qualcomm improvements on top of the Qualcomm PDC (power domain controller) irqchip improvements from tglx:s tree - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups - The NPCM8xx driver has been put into shape fixing many pin and group definitions - Some non-urgent Tegra 264 pin assignments are fixed up - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and pin assignments, missing features etc" * tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits) dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema pinctrl: meson: sync some modify from A4 pinctrl: meson: a4: Add input enable pin configuration pinctrl: realtek: rtd1625: remove unused group name spdif_sel pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13 dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema Revert "Merge branch 'ib-rsk7204' into devel" pinctrl: rockchip: Add RV1106 pinctrl support dt-bindings: pinctrl: rockchip: Add RV1106 compatible pinctrl: rockchip: Decode drive strength in the get function pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable pinctrl: airoha: add support of an7563 SoC dt-bindings: pinctrl: airoha: add support of an7563 pin controller pinctrl: airoha: try to find chip scu node by phandle first pinctrl: airoha: add support of en7523 SoC dt-bindings: pinctrl: airoha: add support of en7523 pin controller pinctrl: airoha: an7583: add support for olt pinmux pinctrl: airoha: an7583: add support for pon_alt pinmux pinctrl: airoha: an7583: add support for npu_uart pinmux dt-bindings: pinctrl: airoha: an7583: add missed features ...
Diffstat (limited to 'tools/include/nolibc/arch-alpha.h')
-rw-r--r--tools/include/nolibc/arch-alpha.h159
1 files changed, 159 insertions, 0 deletions
diff --git a/tools/include/nolibc/arch-alpha.h b/tools/include/nolibc/arch-alpha.h
new file mode 100644
index 000000000..04ff8a95c
--- /dev/null
+++ b/tools/include/nolibc/arch-alpha.h
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
+/*
+ * Alpha specific definitions for NOLIBC
+ * Copyright (C) 2025 Thomas Weißschuh <linux@weissschuh.net>
+ */
+
+#ifndef _NOLIBC_ARCH_ALPHA_H
+#define _NOLIBC_ARCH_ALPHA_H
+
+#include "compiler.h"
+#include "crt.h"
+
+/*
+ * Syscalls for Alpha:
+ * - registers are 64-bit
+ * - syscall number is passed in $0/v0
+ * - the system call is performed by calling callsys
+ * - syscall return comes in $0/v0, error flag in $19/a3
+ * - arguments are passed in $16/a0 to $21/a5
+ * - GCC does not support symbol register names
+ */
+
+#define _NOLIBC_SYSCALL_CLOBBERLIST \
+ "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", \
+ "$22", "$23", "$24", "$25", "$27", "$28", "memory", "cc"
+
+#define __nolibc_syscall0(num) \
+({ \
+ register long _num __asm__ ("$0") = (num); \
+ register long _err __asm__ ("$19"); \
+ \
+ __asm__ volatile ( \
+ "callsys" \
+ : "+r"(_num), "=r"(_err) \
+ : \
+ : _NOLIBC_SYSCALL_CLOBBERLIST, \
+ "$16", "$17", "$18", "$20", "$21" \
+ ); \
+ _err ? -_num : _num; \
+})
+
+#define __nolibc_syscall1(num, arg1) \
+({ \
+ register long _num __asm__ ("$0") = (num); \
+ register long _err __asm__ ("$19"); \
+ register long _arg1 __asm__ ("$16") = (long)(arg1); \
+ \
+ __asm__ volatile ( \
+ "callsys" \
+ : "+r"(_num), "=r"(_err) \
+ : "r"(_arg1) \
+ : _NOLIBC_SYSCALL_CLOBBERLIST, "$17", "$18", "$20", "$21" \
+ ); \
+ _err ? -_num : _num; \
+})
+
+#define __nolibc_syscall2(num, arg1, arg2) \
+({ \
+ register long _num __asm__ ("$0") = (num); \
+ register long _err __asm__ ("$19"); \
+ register long _arg1 __asm__ ("$16") = (long)(arg1); \
+ register long _arg2 __asm__ ("$17") = (long)(arg2); \
+ \
+ __asm__ volatile ( \
+ "callsys" \
+ : "+r"(_num), "=r"(_err) \
+ : "r"(_arg1), "r"(_arg2) \
+ : _NOLIBC_SYSCALL_CLOBBERLIST, "$18", "$20", "$21" \
+ ); \
+ _err ? -_num : _num; \
+})
+
+#define __nolibc_syscall3(num, arg1, arg2, arg3) \
+({ \
+ register long _num __asm__ ("$0") = (num); \
+ register long _err __asm__ ("$19"); \
+ register long _arg1 __asm__ ("$16") = (long)(arg1); \
+ register long _arg2 __asm__ ("$17") = (long)(arg2); \
+ register long _arg3 __asm__ ("$18") = (long)(arg3); \
+ \
+ __asm__ volatile ( \
+ "callsys" \
+ : "+r"(_num), "=r"(_err) \
+ : "r"(_arg1), "r"(_arg2), "r"(_arg3) \
+ : _NOLIBC_SYSCALL_CLOBBERLIST, "$20", "$21" \
+ ); \
+ _err ? -_num : _num; \
+})
+
+#define __nolibc_syscall4(num, arg1, arg2, arg3, arg4) \
+({ \
+ register long _num __asm__ ("$0") = (num); \
+ register long _arg1 __asm__ ("$16") = (long)(arg1); \
+ register long _arg2 __asm__ ("$17") = (long)(arg2); \
+ register long _arg3 __asm__ ("$18") = (long)(arg3); \
+ register long _arg4 __asm__ ("$19") = (long)(arg4); \
+ \
+ __asm__ volatile ( \
+ "callsys" \
+ : "+r"(_num), "+r"(_arg4) \
+ : "r"(_arg1), "r"(_arg2), "r"(_arg3) \
+ : _NOLIBC_SYSCALL_CLOBBERLIST, "$20", "$21" \
+ ); \
+ _arg4 ? -_num : _num; \
+})
+
+#define __nolibc_syscall5(num, arg1, arg2, arg3, arg4, arg5) \
+({ \
+ register long _num __asm__ ("$0") = (num); \
+ register long _arg1 __asm__ ("$16") = (long)(arg1); \
+ register long _arg2 __asm__ ("$17") = (long)(arg2); \
+ register long _arg3 __asm__ ("$18") = (long)(arg3); \
+ register long _arg4 __asm__ ("$19") = (long)(arg4); \
+ register long _arg5 __asm__ ("$20") = (long)(arg5); \
+ \
+ __asm__ volatile ( \
+ "callsys" \
+ : "+r"(_num), "+r"(_arg4) \
+ : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg5) \
+ : _NOLIBC_SYSCALL_CLOBBERLIST, "$21" \
+ ); \
+ _arg4 ? -_num : _num; \
+})
+
+#define __nolibc_syscall6(num, arg1, arg2, arg3, arg4, arg5, arg6) \
+({ \
+ register long _num __asm__ ("$0") = (num); \
+ register long _arg1 __asm__ ("$16") = (long)(arg1); \
+ register long _arg2 __asm__ ("$17") = (long)(arg2); \
+ register long _arg3 __asm__ ("$18") = (long)(arg3); \
+ register long _arg4 __asm__ ("$19") = (long)(arg4); \
+ register long _arg5 __asm__ ("$20") = (long)(arg5); \
+ register long _arg6 __asm__ ("$21") = (long)(arg6); \
+ \
+ __asm__ volatile ( \
+ "callsys" \
+ : "+r"(_num), "+r"(_arg4) \
+ : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg5), \
+ "r"(_arg6) \
+ : _NOLIBC_SYSCALL_CLOBBERLIST \
+ ); \
+ _arg4 ? -_num : _num; \
+})
+
+/* startup code */
+void __attribute__((weak, noreturn)) __nolibc_entrypoint __nolibc_no_stack_protector
+_start(void)
+{
+ __asm__ volatile (
+ "br $gp, 0f\n" /* setup $gp, so that 'lda' works */
+ "0: ldgp $gp, 0($gp)\n"
+ "lda $27, _start_c\n" /* setup current function address for _start_c */
+ "mov $sp, $16\n" /* save argc pointer to $16, as arg1 of _start_c */
+ "br _start_c\n" /* transfer to c runtime */
+ );
+ __nolibc_entrypoint_epilogue();
+}
+
+#endif /* _NOLIBC_ARCH_ALPHA_H */