summaryrefslogtreecommitdiffstats
path: root/rust/syn/bigint.rs
diff options
context:
space:
mode:
authorDapeng Mi <dapeng1.mi@linux.intel.com>2026-09-17 09:52:33 +0800
committerIngo Molnar <mingo@kernel.org>2026-09-22 11:37:46 +0200
commit0102c8c7fdfc4bd700971daff2b94470f4eafae4 (patch)
tree531306c2299f9a269f0a986e29f17ba972180104 /rust/syn/bigint.rs
downloadlinux-stable-0102c8c7fdfc4bd700971daff2b94470f4eafae4.tar.gz
linux-stable-0102c8c7fdfc4bd700971daff2b94470f4eafae4.zip
perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rspgrafted
DMR introduces Offmodule Response events in place of the legacy Offcore Response events, but it still exposes the inherited offcore_rsp PMU attribute for programming the corresponding MSR data. Rename the DMR PMU attribute to offmodule_rsp so the sysfs interface matches the underlying event name and avoids user & tooling confusion. Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://patch.msgid.link/20260917015234.981153-12-dapeng1.mi@linux.intel.com
Diffstat (limited to 'rust/syn/bigint.rs')
-rw-r--r--rust/syn/bigint.rs68
1 files changed, 68 insertions, 0 deletions
diff --git a/rust/syn/bigint.rs b/rust/syn/bigint.rs
new file mode 100644
index 000000000..d706f9f51
--- /dev/null
+++ b/rust/syn/bigint.rs
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+
+use std::ops::{AddAssign, MulAssign};
+
+// For implementing base10_digits() accessor on LitInt.
+pub(crate) struct BigInt {
+ digits: Vec<u8>,
+}
+
+impl BigInt {
+ pub(crate) fn new() -> Self {
+ BigInt { digits: Vec::new() }
+ }
+
+ pub(crate) fn to_string(&self) -> String {
+ let mut repr = String::with_capacity(self.digits.len());
+
+ let mut has_nonzero = false;
+ for digit in self.digits.iter().rev() {
+ has_nonzero |= *digit != 0;
+ if has_nonzero {
+ repr.push((*digit + b'0') as char);
+ }
+ }
+
+ if repr.is_empty() {
+ repr.push('0');
+ }
+
+ repr
+ }
+
+ fn reserve_two_digits(&mut self) {
+ let len = self.digits.len();
+ let desired =
+ len + !self.digits.ends_with(&[0, 0]) as usize + !self.digits.ends_with(&[0]) as usize;
+ self.digits.resize(desired, 0);
+ }
+}
+
+impl AddAssign<u8> for BigInt {
+ // Assumes increment <16.
+ fn add_assign(&mut self, mut increment: u8) {
+ self.reserve_two_digits();
+
+ let mut i = 0;
+ while increment > 0 {
+ let sum = self.digits[i] + increment;
+ self.digits[i] = sum % 10;
+ increment = sum / 10;
+ i += 1;
+ }
+ }
+}
+
+impl MulAssign<u8> for BigInt {
+ // Assumes base <=16.
+ fn mul_assign(&mut self, base: u8) {
+ self.reserve_two_digits();
+
+ let mut carry = 0;
+ for digit in &mut self.digits {
+ let prod = *digit * base + carry;
+ *digit = prod % 10;
+ carry = prod / 10;
+ }
+ }
+}