Merge tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrlgrafted

Pull pin control updates from Linus Walleij:
 "Core changes:

   - Use the non-blocking mux_state_try_select() in the generic MUX pin
     control back-end

   - Free pin maps on pinctrl_generic_to_map() failure in the core
     helpers

  New hardware pin control:

   - Qualcomm Maili TLMM SoC, PMG1110 PMIC, and Eliza LPASS LPI TLMM SoC
     (this is for the low power audio, LPASS = Low Power Audio SubSystem
     portions)

   - Upboard support on top of the Intel pin controller

   - Apple T6030 and T6031 support (just compatible strings)

   - Samsung Exynos 8855 SoC

   - Mediatek MT6858 SoC

   - Rockchip RK3308B and RV1106 SoCs

   - Airoha EN7523 and AN7563 SoCs

  Improvements:

   - Qualcomm TLMM GPIOs are unconditionally marked as wakeup capable

   - Qualcomm improvements on top of the Qualcomm PDC (power domain
     controller) irqchip improvements from tglx:s tree

   - Qualcomm IPQ806x and IPQ9650 non-urgent pin grop fixups

   - The NPCM8xx driver has been put into shape fixing many pin and
     group definitions

   - Some non-urgent Tegra 264 pin assignments are fixed up

   - Some non-urgent fixups to Airoha AN7581 and AN7583 registers and
     pin assignments, missing features etc"

* tag 'pinctrl-v7.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (130 commits)
  dt-bindings: pinctrl: Convert TI DA850 pupd to DT schema
  pinctrl: meson: sync some modify from A4
  pinctrl: meson: a4: Add input enable pin configuration
  pinctrl: realtek: rtd1625: remove unused group name spdif_sel
  pinctrl: realtek: rtd1625: fix base_bit for VE4 GPIO 13
  dt-bindings: pinctrl: microchip,pic32mzda-pinctrl: Convert to DT schema
  Revert "Merge branch 'ib-rsk7204' into devel"
  pinctrl: rockchip: Add RV1106 pinctrl support
  dt-bindings: pinctrl: rockchip: Add RV1106 compatible
  pinctrl: rockchip: Decode drive strength in the get function
  pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable
  pinctrl: airoha: add support of an7563 SoC
  dt-bindings: pinctrl: airoha: add support of an7563 pin controller
  pinctrl: airoha: try to find chip scu node by phandle first
  pinctrl: airoha: add support of en7523 SoC
  dt-bindings: pinctrl: airoha: add support of en7523 pin controller
  pinctrl: airoha: an7583: add support for olt pinmux
  pinctrl: airoha: an7583: add support for pon_alt pinmux
  pinctrl: airoha: an7583: add support for npu_uart pinmux
  dt-bindings: pinctrl: airoha: an7583: add missed features
  ...

1 files changed, 161 insertions, 0 deletions

diff --git a/rust/helpers/io.c b/rust/helpers/io.c
new file mode 100644
index 000000000..308950aae
--- /dev/null
+++ b/rust/helpers/io.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/io.h>
+#include <linux/ioport.h>
+
+#ifdef CONFIG_HAS_IOMEM
+__rust_helper void __iomem *rust_helper_ioremap(phys_addr_t offset, size_t size)
+{
+	return ioremap(offset, size);
+}
+
+__rust_helper void __iomem *rust_helper_ioremap_np(phys_addr_t offset,
+						   size_t size)
+{
+	return ioremap_np(offset, size);
+}
+
+__rust_helper void rust_helper_iounmap(void __iomem *addr)
+{
+	iounmap(addr);
+}
+#endif /* CONFIG_HAS_IOMEM */
+
+__rust_helper void rust_helper_memcpy_fromio(void *dst,
+					     const volatile void __iomem *src,
+					     size_t count)
+{
+	memcpy_fromio(dst, src, count);
+}
+
+__rust_helper void rust_helper_memcpy_toio(volatile void __iomem *dst,
+					   const void *src, size_t count)
+{
+	memcpy_toio(dst, src, count);
+}
+
+__rust_helper u8 rust_helper_readb(const void __iomem *addr)
+{
+	return readb(addr);
+}
+
+__rust_helper u16 rust_helper_readw(const void __iomem *addr)
+{
+	return readw(addr);
+}
+
+__rust_helper u32 rust_helper_readl(const void __iomem *addr)
+{
+	return readl(addr);
+}
+
+#ifdef CONFIG_64BIT
+__rust_helper u64 rust_helper_readq(const void __iomem *addr)
+{
+	return readq(addr);
+}
+#endif
+
+__rust_helper void rust_helper_writeb(u8 value, void __iomem *addr)
+{
+	writeb(value, addr);
+}
+
+__rust_helper void rust_helper_writew(u16 value, void __iomem *addr)
+{
+	writew(value, addr);
+}
+
+__rust_helper void rust_helper_writel(u32 value, void __iomem *addr)
+{
+	writel(value, addr);
+}
+
+#ifdef CONFIG_64BIT
+__rust_helper void rust_helper_writeq(u64 value, void __iomem *addr)
+{
+	writeq(value, addr);
+}
+#endif
+
+__rust_helper u8 rust_helper_readb_relaxed(const void __iomem *addr)
+{
+	return readb_relaxed(addr);
+}
+
+__rust_helper u16 rust_helper_readw_relaxed(const void __iomem *addr)
+{
+	return readw_relaxed(addr);
+}
+
+__rust_helper u32 rust_helper_readl_relaxed(const void __iomem *addr)
+{
+	return readl_relaxed(addr);
+}
+
+#ifdef CONFIG_64BIT
+__rust_helper u64 rust_helper_readq_relaxed(const void __iomem *addr)
+{
+	return readq_relaxed(addr);
+}
+#endif
+
+__rust_helper void rust_helper_writeb_relaxed(u8 value, void __iomem *addr)
+{
+	writeb_relaxed(value, addr);
+}
+
+__rust_helper void rust_helper_writew_relaxed(u16 value, void __iomem *addr)
+{
+	writew_relaxed(value, addr);
+}
+
+__rust_helper void rust_helper_writel_relaxed(u32 value, void __iomem *addr)
+{
+	writel_relaxed(value, addr);
+}
+
+#ifdef CONFIG_64BIT
+__rust_helper void rust_helper_writeq_relaxed(u64 value, void __iomem *addr)
+{
+	writeq_relaxed(value, addr);
+}
+#endif
+
+__rust_helper resource_size_t rust_helper_resource_size(struct resource *res)
+{
+	return resource_size(res);
+}
+
+__rust_helper struct resource *
+rust_helper_request_mem_region(resource_size_t start, resource_size_t n,
+			       const char *name)
+{
+	return request_mem_region(start, n, name);
+}
+
+__rust_helper void rust_helper_release_mem_region(resource_size_t start,
+						  resource_size_t n)
+{
+	release_mem_region(start, n);
+}
+
+__rust_helper struct resource *rust_helper_request_region(resource_size_t start,
+							  resource_size_t n,
+							  const char *name)
+{
+	return request_region(start, n, name);
+}
+
+__rust_helper struct resource *
+rust_helper_request_muxed_region(resource_size_t start, resource_size_t n,
+				 const char *name)
+{
+	return request_muxed_region(start, n, name);
+}
+
+__rust_helper void rust_helper_release_region(resource_size_t start,
+					      resource_size_t n)
+{
+	release_region(start, n);
+}