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| author | Yazen Ghannam <yazen.ghannam@amd.com> | 2026-09-03 10:43:25 -0500 |
|---|---|---|
| committer | Borislav Petkov (AMD) <bp@alien8.de> | 2026-09-10 18:05:43 -0700 |
| commit | 27600805e62f800bacf990354632eae4e487d34c (patch) | |
| tree | e8aec0ddfaa0bc264d79af632e3de3f1b75ae4c8 /rust/helpers/io.c | |
| download | linux-stable-27600805e62f800bacf990354632eae4e487d34c.tar.gz linux-stable-27600805e62f800bacf990354632eae4e487d34c.zip | |
x86/amd_node: Fix PCI device reference counting in amd_smn_init()grafted
The local "root" pointer is a temporary variable used during the device
search. Therefore, refcount related to the search iterators should be cleaned
up after the search is complete.
Use the __free() cleanup macro to ensure the refcount is decremented when the
temporary pointer goes out of scope.
Additionally, increment the refcount when caching a root pointer. This ensures
the in-use refcount is separate from the temporary search refcounting.
Finally, drop the redundant "root = NULL" before the second search loop. The
pci_get_class() iterator always decrements the refcount of its "from"
argument, so the first loop can only fall through with "root" already NULL.
Fixes: 0a4b61d9c2e4 ("x86/amd_node: Fix AMD root device caching")
Closes: https://sashiko.dev/#/patchset/20260806160159.230453-1-jason.andryuk%40amd.com
Reported-by: Sashiko <sashiko-bot@kernel.org>
Assisted-by: LLM
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Cc: <stable@kernel.org>
Link: https://patch.msgid.link/20260903154325.74343-1-yazen.ghannam@amd.com
Diffstat (limited to 'rust/helpers/io.c')
| -rw-r--r-- | rust/helpers/io.c | 161 |
1 files changed, 161 insertions, 0 deletions
diff --git a/rust/helpers/io.c b/rust/helpers/io.c new file mode 100644 index 000000000..308950aae --- /dev/null +++ b/rust/helpers/io.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include <linux/io.h> +#include <linux/ioport.h> + +#ifdef CONFIG_HAS_IOMEM +__rust_helper void __iomem *rust_helper_ioremap(phys_addr_t offset, size_t size) +{ + return ioremap(offset, size); +} + +__rust_helper void __iomem *rust_helper_ioremap_np(phys_addr_t offset, + size_t size) +{ + return ioremap_np(offset, size); +} + +__rust_helper void rust_helper_iounmap(void __iomem *addr) +{ + iounmap(addr); +} +#endif /* CONFIG_HAS_IOMEM */ + +__rust_helper void rust_helper_memcpy_fromio(void *dst, + const volatile void __iomem *src, + size_t count) +{ + memcpy_fromio(dst, src, count); +} + +__rust_helper void rust_helper_memcpy_toio(volatile void __iomem *dst, + const void *src, size_t count) +{ + memcpy_toio(dst, src, count); +} + +__rust_helper u8 rust_helper_readb(const void __iomem *addr) +{ + return readb(addr); +} + +__rust_helper u16 rust_helper_readw(const void __iomem *addr) +{ + return readw(addr); +} + +__rust_helper u32 rust_helper_readl(const void __iomem *addr) +{ + return readl(addr); +} + +#ifdef CONFIG_64BIT +__rust_helper u64 rust_helper_readq(const void __iomem *addr) +{ + return readq(addr); +} +#endif + +__rust_helper void rust_helper_writeb(u8 value, void __iomem *addr) +{ + writeb(value, addr); +} + +__rust_helper void rust_helper_writew(u16 value, void __iomem *addr) +{ + writew(value, addr); +} + +__rust_helper void rust_helper_writel(u32 value, void __iomem *addr) +{ + writel(value, addr); +} + +#ifdef CONFIG_64BIT +__rust_helper void rust_helper_writeq(u64 value, void __iomem *addr) +{ + writeq(value, addr); +} +#endif + +__rust_helper u8 rust_helper_readb_relaxed(const void __iomem *addr) +{ + return readb_relaxed(addr); +} + +__rust_helper u16 rust_helper_readw_relaxed(const void __iomem *addr) +{ + return readw_relaxed(addr); +} + +__rust_helper u32 rust_helper_readl_relaxed(const void __iomem *addr) +{ + return readl_relaxed(addr); +} + +#ifdef CONFIG_64BIT +__rust_helper u64 rust_helper_readq_relaxed(const void __iomem *addr) +{ + return readq_relaxed(addr); +} +#endif + +__rust_helper void rust_helper_writeb_relaxed(u8 value, void __iomem *addr) +{ + writeb_relaxed(value, addr); +} + +__rust_helper void rust_helper_writew_relaxed(u16 value, void __iomem *addr) +{ + writew_relaxed(value, addr); +} + +__rust_helper void rust_helper_writel_relaxed(u32 value, void __iomem *addr) +{ + writel_relaxed(value, addr); +} + +#ifdef CONFIG_64BIT +__rust_helper void rust_helper_writeq_relaxed(u64 value, void __iomem *addr) +{ + writeq_relaxed(value, addr); +} +#endif + +__rust_helper resource_size_t rust_helper_resource_size(struct resource *res) +{ + return resource_size(res); +} + +__rust_helper struct resource * +rust_helper_request_mem_region(resource_size_t start, resource_size_t n, + const char *name) +{ + return request_mem_region(start, n, name); +} + +__rust_helper void rust_helper_release_mem_region(resource_size_t start, + resource_size_t n) +{ + release_mem_region(start, n); +} + +__rust_helper struct resource *rust_helper_request_region(resource_size_t start, + resource_size_t n, + const char *name) +{ + return request_region(start, n, name); +} + +__rust_helper struct resource * +rust_helper_request_muxed_region(resource_size_t start, resource_size_t n, + const char *name) +{ + return request_muxed_region(start, n, name); +} + +__rust_helper void rust_helper_release_region(resource_size_t start, + resource_size_t n) +{ + release_region(start, n); +} |
