summaryrefslogtreecommitdiffstats
path: root/rust/helpers/atomic_ext.c
diff options
context:
space:
mode:
authorYazen Ghannam <yazen.ghannam@amd.com>2026-09-03 10:43:25 -0500
committerBorislav Petkov (AMD) <bp@alien8.de>2026-09-10 18:05:43 -0700
commit27600805e62f800bacf990354632eae4e487d34c (patch)
treee8aec0ddfaa0bc264d79af632e3de3f1b75ae4c8 /rust/helpers/atomic_ext.c
downloadlinux-stable-27600805e62f800bacf990354632eae4e487d34c.tar.gz
linux-stable-27600805e62f800bacf990354632eae4e487d34c.zip
x86/amd_node: Fix PCI device reference counting in amd_smn_init()grafted
The local "root" pointer is a temporary variable used during the device search. Therefore, refcount related to the search iterators should be cleaned up after the search is complete. Use the __free() cleanup macro to ensure the refcount is decremented when the temporary pointer goes out of scope. Additionally, increment the refcount when caching a root pointer. This ensures the in-use refcount is separate from the temporary search refcounting. Finally, drop the redundant "root = NULL" before the second search loop. The pci_get_class() iterator always decrements the refcount of its "from" argument, so the first loop can only fall through with "root" already NULL. Fixes: 0a4b61d9c2e4 ("x86/amd_node: Fix AMD root device caching") Closes: https://sashiko.dev/#/patchset/20260806160159.230453-1-jason.andryuk%40amd.com Reported-by: Sashiko <sashiko-bot@kernel.org> Assisted-by: LLM Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Cc: <stable@kernel.org> Link: https://patch.msgid.link/20260903154325.74343-1-yazen.ghannam@amd.com
Diffstat (limited to 'rust/helpers/atomic_ext.c')
-rw-r--r--rust/helpers/atomic_ext.c87
1 files changed, 87 insertions, 0 deletions
diff --git a/rust/helpers/atomic_ext.c b/rust/helpers/atomic_ext.c
new file mode 100644
index 000000000..c267d5190
--- /dev/null
+++ b/rust/helpers/atomic_ext.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/barrier.h>
+#include <asm/rwonce.h>
+#include <linux/atomic.h>
+
+#define GEN_READ_HELPER(tname, type) \
+__rust_helper type rust_helper_atomic_##tname##_read(type *ptr) \
+{ \
+ return READ_ONCE(*ptr); \
+}
+
+#define GEN_SET_HELPER(tname, type) \
+__rust_helper void rust_helper_atomic_##tname##_set(type *ptr, type val) \
+{ \
+ WRITE_ONCE(*ptr, val); \
+}
+
+#define GEN_READ_ACQUIRE_HELPER(tname, type) \
+__rust_helper type rust_helper_atomic_##tname##_read_acquire(type *ptr) \
+{ \
+ return smp_load_acquire(ptr); \
+}
+
+#define GEN_SET_RELEASE_HELPER(tname, type) \
+__rust_helper void rust_helper_atomic_##tname##_set_release(type *ptr, type val)\
+{ \
+ smp_store_release(ptr, val); \
+}
+
+#define GEN_READ_SET_HELPERS(tname, type) \
+ GEN_READ_HELPER(tname, type) \
+ GEN_SET_HELPER(tname, type) \
+ GEN_READ_ACQUIRE_HELPER(tname, type) \
+ GEN_SET_RELEASE_HELPER(tname, type) \
+
+GEN_READ_SET_HELPERS(i8, s8)
+GEN_READ_SET_HELPERS(i16, s16)
+GEN_READ_SET_HELPERS(ptr, const void *)
+
+/*
+ * xchg helpers depend on ARCH_SUPPORTS_ATOMIC_RMW and on the
+ * architecture provding xchg() support for i8 and i16.
+ *
+ * The architectures that currently support Rust (x86_64, armv7,
+ * arm64, riscv, and loongarch) satisfy these requirements.
+ */
+#define GEN_XCHG_HELPER(tname, type, suffix) \
+__rust_helper type \
+rust_helper_atomic_##tname##_xchg##suffix(type *ptr, type new) \
+{ \
+ return xchg##suffix(ptr, new); \
+}
+
+#define GEN_XCHG_HELPERS(tname, type) \
+ GEN_XCHG_HELPER(tname, type, ) \
+ GEN_XCHG_HELPER(tname, type, _acquire) \
+ GEN_XCHG_HELPER(tname, type, _release) \
+ GEN_XCHG_HELPER(tname, type, _relaxed) \
+
+GEN_XCHG_HELPERS(i8, s8)
+GEN_XCHG_HELPERS(i16, s16)
+GEN_XCHG_HELPERS(ptr, const void *)
+
+/*
+ * try_cmpxchg helpers depend on ARCH_SUPPORTS_ATOMIC_RMW and on the
+ * architecture provding try_cmpxchg() support for i8 and i16.
+ *
+ * The architectures that currently support Rust (x86_64, armv7,
+ * arm64, riscv, and loongarch) satisfy these requirements.
+ */
+#define GEN_TRY_CMPXCHG_HELPER(tname, type, suffix) \
+__rust_helper bool \
+rust_helper_atomic_##tname##_try_cmpxchg##suffix(type *ptr, type *old, type new)\
+{ \
+ return try_cmpxchg##suffix(ptr, old, new); \
+}
+
+#define GEN_TRY_CMPXCHG_HELPERS(tname, type) \
+ GEN_TRY_CMPXCHG_HELPER(tname, type, ) \
+ GEN_TRY_CMPXCHG_HELPER(tname, type, _acquire) \
+ GEN_TRY_CMPXCHG_HELPER(tname, type, _release) \
+ GEN_TRY_CMPXCHG_HELPER(tname, type, _relaxed) \
+
+GEN_TRY_CMPXCHG_HELPERS(i8, s8)
+GEN_TRY_CMPXCHG_HELPERS(i16, s16)
+GEN_TRY_CMPXCHG_HELPERS(ptr, const void *)