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authorXie Yuanbin <xieyuanbin1@huawei.com>2026-07-28 03:16:42 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2026-08-05 16:15:51 +0100
commit1039bffd6ae9c75b42b7d148d6c1106134107b66 (patch)
treee8ee4ac80f87e2ad1b6b0c877eccbb62b0915c02 /rust/helpers/atomic_ext.c
downloadlinux-stable-1039bffd6ae9c75b42b7d148d6c1106134107b66.tar.gz
linux-stable-1039bffd6ae9c75b42b7d148d6c1106134107b66.zip
ARM: 9485/1: mm: acquire mmap write lock around show_pte() for user faultsgrafted
When CONFIG_DEBUG_USER=y, and cmdline "user_debug=31" is set, a user fault may trigger show_pte() without any lock. If another thread in the same process concurrently calls munmap(), the page table pages may be freed while show_pte() is still traversing them, causing a use-after-free in show_pte(). If CONFIG_ARM_LPAE=y, this may cause a kernel panic if the pages table of PMD are freed when show_pte() is running. Acquire mmap_write_lock() around show_pte() for user faults to fix the contention. For user faults, additionally restrict that show_pte() is called only when the addr is a user-space address (addr < TASK_SIZE). This is because the lock of tsk->mm only protects the virtual memory of user address space, furthermore, dumping the page tables of a kernel-space address for user faults is unnecessary and may have security implications. Keep everything unchanged for kernel faults, because the kernel is already in the "oops" state, acquiring a lock may risk a deadlock. Co-developed-by: Qi Xi <xiqi2@huawei.com> Fixes: 6d021b724481 ("ARM: dump pgd, pmd and pte states on unhandled data abort faults") Link: https://lore.kernel.org/20260716014022.2823-1-xieyuanbin1@huawei.com Acked-by: Lorenzo Stoakes (ARM) <ljs@kernel.org> Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Qi Xi <xiqi2@huawei.com> Signed-off-by: Xie Yuanbin <xieyuanbin1@huawei.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'rust/helpers/atomic_ext.c')
-rw-r--r--rust/helpers/atomic_ext.c87
1 files changed, 87 insertions, 0 deletions
diff --git a/rust/helpers/atomic_ext.c b/rust/helpers/atomic_ext.c
new file mode 100644
index 000000000..c267d5190
--- /dev/null
+++ b/rust/helpers/atomic_ext.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <asm/barrier.h>
+#include <asm/rwonce.h>
+#include <linux/atomic.h>
+
+#define GEN_READ_HELPER(tname, type) \
+__rust_helper type rust_helper_atomic_##tname##_read(type *ptr) \
+{ \
+ return READ_ONCE(*ptr); \
+}
+
+#define GEN_SET_HELPER(tname, type) \
+__rust_helper void rust_helper_atomic_##tname##_set(type *ptr, type val) \
+{ \
+ WRITE_ONCE(*ptr, val); \
+}
+
+#define GEN_READ_ACQUIRE_HELPER(tname, type) \
+__rust_helper type rust_helper_atomic_##tname##_read_acquire(type *ptr) \
+{ \
+ return smp_load_acquire(ptr); \
+}
+
+#define GEN_SET_RELEASE_HELPER(tname, type) \
+__rust_helper void rust_helper_atomic_##tname##_set_release(type *ptr, type val)\
+{ \
+ smp_store_release(ptr, val); \
+}
+
+#define GEN_READ_SET_HELPERS(tname, type) \
+ GEN_READ_HELPER(tname, type) \
+ GEN_SET_HELPER(tname, type) \
+ GEN_READ_ACQUIRE_HELPER(tname, type) \
+ GEN_SET_RELEASE_HELPER(tname, type) \
+
+GEN_READ_SET_HELPERS(i8, s8)
+GEN_READ_SET_HELPERS(i16, s16)
+GEN_READ_SET_HELPERS(ptr, const void *)
+
+/*
+ * xchg helpers depend on ARCH_SUPPORTS_ATOMIC_RMW and on the
+ * architecture provding xchg() support for i8 and i16.
+ *
+ * The architectures that currently support Rust (x86_64, armv7,
+ * arm64, riscv, and loongarch) satisfy these requirements.
+ */
+#define GEN_XCHG_HELPER(tname, type, suffix) \
+__rust_helper type \
+rust_helper_atomic_##tname##_xchg##suffix(type *ptr, type new) \
+{ \
+ return xchg##suffix(ptr, new); \
+}
+
+#define GEN_XCHG_HELPERS(tname, type) \
+ GEN_XCHG_HELPER(tname, type, ) \
+ GEN_XCHG_HELPER(tname, type, _acquire) \
+ GEN_XCHG_HELPER(tname, type, _release) \
+ GEN_XCHG_HELPER(tname, type, _relaxed) \
+
+GEN_XCHG_HELPERS(i8, s8)
+GEN_XCHG_HELPERS(i16, s16)
+GEN_XCHG_HELPERS(ptr, const void *)
+
+/*
+ * try_cmpxchg helpers depend on ARCH_SUPPORTS_ATOMIC_RMW and on the
+ * architecture provding try_cmpxchg() support for i8 and i16.
+ *
+ * The architectures that currently support Rust (x86_64, armv7,
+ * arm64, riscv, and loongarch) satisfy these requirements.
+ */
+#define GEN_TRY_CMPXCHG_HELPER(tname, type, suffix) \
+__rust_helper bool \
+rust_helper_atomic_##tname##_try_cmpxchg##suffix(type *ptr, type *old, type new)\
+{ \
+ return try_cmpxchg##suffix(ptr, old, new); \
+}
+
+#define GEN_TRY_CMPXCHG_HELPERS(tname, type) \
+ GEN_TRY_CMPXCHG_HELPER(tname, type, ) \
+ GEN_TRY_CMPXCHG_HELPER(tname, type, _acquire) \
+ GEN_TRY_CMPXCHG_HELPER(tname, type, _release) \
+ GEN_TRY_CMPXCHG_HELPER(tname, type, _relaxed) \
+
+GEN_TRY_CMPXCHG_HELPERS(i8, s8)
+GEN_TRY_CMPXCHG_HELPERS(i16, s16)
+GEN_TRY_CMPXCHG_HELPERS(ptr, const void *)