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authorPaul Mbewe <paultyson.mbewe@ziehl-abegg.de>2026-09-30 16:56:28 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2026-10-01 11:07:24 +0200
commitd9feaa93328a6f885afb8ac6374897fafc294222 (patch)
tree3731901e196d1edfc1db773c1524d4acbdbf6739 /lib/dynamic_debug.c
parent527484911a40f6e84cf47e8bc490f7da61ab4151 (diff)
downloadlinux-stable-d9feaa93328a6f885afb8ac6374897fafc294222.tar.gz
linux-stable-d9feaa93328a6f885afb8ac6374897fafc294222.zip
serial: sc16is7xx: reduce TX refill rate with half-FIFO trigger
With the TX trigger set to 8 free spaces, THRI is generated roughly once per 8 transmitted bytes. At 115200 baud 8N1, this corresponds to approximately 0.7 ms between TX refill events. Set the TX trigger to 32 free spaces via TLR[3:0]. This makes each refill larger and reduces the refill rate by about 4x. At 115200 baud 8N1, the refill cadence becomes approximately 2.8 ms. The trade-off is that the time-to-empty after THRI asserts is reduced from 56 to 32 byte times. The fresh-TXLVL refill loop fills the hardware TX FIFO strictly below whichever trigger is selected. This patch changes only the refill frequency and the associated latency trade-off. With the two TX gap fixes applied in both configurations, changing the trigger from 8 to 32 free spaces produced the following median values from repeated top snapshots under the same continuous Modbus RTU load. Each transaction used an 8-byte RX request and a 255-byte TX response, so the workload was dominated by TX traffic: trigger=8 trigger=32 SPI IRQ thread CPU 15% 5% system CPU 44% 29% idle CPU 40% 52% one-minute load 2.02 0.99 The datasets contain 547 snapshots with trigger=8 and 535 snapshots with trigger=32. Only TLR[3:0] is changed. TLR[7:4] remains zero so the RX trigger retains its FCR setting. RX trigger tuning may also be useful, but generic RX/TX trigger configuration is left for follow-up work. SC16IS7XX_TX_TRIGGER_LEVEL is used for both the programmed TLR value and the TXLVL refill-loop threshold, keeping the hardware trigger and the software refill condition synchronized. TCR/TLR access requires EFR[4] and MCR[2], which are already enabled by the TCR setup immediately preceding the TLR write. Reviewed-by: Joachim Knorr <joachim.knorr@ziehl-abegg.de> Link: https://lore.kernel.org/linux-serial/20260623112225.82386-3-paultyson.mbewe@ziehl-abegg.de/ Signed-off-by: Paul Mbewe <paultyson.mbewe@ziehl-abegg.de> Link: https://patch.msgid.link/20260930145628.566535-3-paultyson.mbewe@ziehl-abegg.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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