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| author | Fuad Tabba <fuad.tabba@linux.dev> | 2026-09-22 19:14:30 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-09-23 12:34:30 +0000 |
| commit | 2bc6b218717b9d08f466f88209251d54bc09b207 (patch) | |
| tree | cb91c941eccb15f94cbec4e96aa3a9c8736b5d66 /include/uapi/video/uvesafb.h | |
| download | linux-stable-2bc6b218717b9d08f466f88209251d54bc09b207.tar.gz linux-stable-2bc6b218717b9d08f466f88209251d54bc09b207.zip | |
arm64/boot: Disable trapping of PMZR_EL0 writes to EL2grafted
__init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2.
PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in
HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host
traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The
kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU
driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a
write from EL0 reaches the trap and takes the host down without a panic
message.
Accumulate the HDFGWTR2_EL2 bits separately, as __init_el2_fgt() already
does for HDFGWTR_EL2, and set nPMZR_EL0 with the other FEAT_PMUv3p9
bits.
Fixes: 858c7bfcb35e1 ("arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9")
Cc: stable@vger.kernel.org
Signed-off-by: Fuad Tabba <fuad.tabba@linux.dev>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Oliver Upton <oupton@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'include/uapi/video/uvesafb.h')
| -rw-r--r-- | include/uapi/video/uvesafb.h | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/include/uapi/video/uvesafb.h b/include/uapi/video/uvesafb.h new file mode 100644 index 000000000..a0d5c9213 --- /dev/null +++ b/include/uapi/video/uvesafb.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_UVESAFB_H +#define _UAPI_UVESAFB_H + +#include <linux/types.h> + +struct v86_regs { + __u32 ebx; + __u32 ecx; + __u32 edx; + __u32 esi; + __u32 edi; + __u32 ebp; + __u32 eax; + __u32 eip; + __u32 eflags; + __u32 esp; + __u16 cs; + __u16 ss; + __u16 es; + __u16 ds; + __u16 fs; + __u16 gs; +}; + +/* Task flags */ +#define TF_VBEIB 0x01 +#define TF_BUF_ESDI 0x02 +#define TF_BUF_ESBX 0x04 +#define TF_BUF_RET 0x08 +#define TF_EXIT 0x10 + +struct uvesafb_task { + __u8 flags; + int buf_len; + struct v86_regs regs; +}; + +/* Constants for the capabilities field + * in vbe_ib */ +#define VBE_CAP_CAN_SWITCH_DAC 0x01 +#define VBE_CAP_VGACOMPAT 0x02 + +/* The VBE Info Block */ +struct vbe_ib { + char vbe_signature[4]; + __u16 vbe_version; + __u32 oem_string_ptr; + __u32 capabilities; + __u32 mode_list_ptr; + __u16 total_memory; + __u16 oem_software_rev; + __u32 oem_vendor_name_ptr; + __u32 oem_product_name_ptr; + __u32 oem_product_rev_ptr; + __u8 reserved[222]; + char oem_data[256]; + char misc_data[512]; +} __attribute__ ((packed)); + +#endif /* _UAPI_UVESAFB_H */ |
