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| author | Fuad Tabba <fuad.tabba@linux.dev> | 2026-09-22 19:14:30 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-09-23 12:34:30 +0000 |
| commit | 2bc6b218717b9d08f466f88209251d54bc09b207 (patch) | |
| tree | cb91c941eccb15f94cbec4e96aa3a9c8736b5d66 /include/uapi/asm-generic/termbits-common.h | |
| download | linux-stable-2bc6b218717b9d08f466f88209251d54bc09b207.tar.gz linux-stable-2bc6b218717b9d08f466f88209251d54bc09b207.zip | |
arm64/boot: Disable trapping of PMZR_EL0 writes to EL2grafted
__init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2.
PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in
HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host
traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The
kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU
driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a
write from EL0 reaches the trap and takes the host down without a panic
message.
Accumulate the HDFGWTR2_EL2 bits separately, as __init_el2_fgt() already
does for HDFGWTR_EL2, and set nPMZR_EL0 with the other FEAT_PMUv3p9
bits.
Fixes: 858c7bfcb35e1 ("arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9")
Cc: stable@vger.kernel.org
Signed-off-by: Fuad Tabba <fuad.tabba@linux.dev>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Oliver Upton <oupton@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'include/uapi/asm-generic/termbits-common.h')
| -rw-r--r-- | include/uapi/asm-generic/termbits-common.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/include/uapi/asm-generic/termbits-common.h b/include/uapi/asm-generic/termbits-common.h new file mode 100644 index 000000000..4a6a79f28 --- /dev/null +++ b/include/uapi/asm-generic/termbits-common.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef __ASM_GENERIC_TERMBITS_COMMON_H +#define __ASM_GENERIC_TERMBITS_COMMON_H + +typedef unsigned char cc_t; +typedef unsigned int speed_t; + +/* c_iflag bits */ +#define IGNBRK 0x001 /* Ignore break condition */ +#define BRKINT 0x002 /* Signal interrupt on break */ +#define IGNPAR 0x004 /* Ignore characters with parity errors */ +#define PARMRK 0x008 /* Mark parity and framing errors */ +#define INPCK 0x010 /* Enable input parity check */ +#define ISTRIP 0x020 /* Strip 8th bit off characters */ +#define INLCR 0x040 /* Map NL to CR on input */ +#define IGNCR 0x080 /* Ignore CR */ +#define ICRNL 0x100 /* Map CR to NL on input */ +#define IXANY 0x800 /* Any character will restart after stop */ + +/* c_oflag bits */ +#define OPOST 0x01 /* Perform output processing */ +#define OCRNL 0x08 +#define ONOCR 0x10 +#define ONLRET 0x20 +#define OFILL 0x40 +#define OFDEL 0x80 + +/* c_cflag bit meaning */ +/* Common CBAUD rates */ +#define B0 0x00000000 /* hang up */ +#define B50 0x00000001 +#define B75 0x00000002 +#define B110 0x00000003 +#define B134 0x00000004 +#define B150 0x00000005 +#define B200 0x00000006 +#define B300 0x00000007 +#define B600 0x00000008 +#define B1200 0x00000009 +#define B1800 0x0000000a +#define B2400 0x0000000b +#define B4800 0x0000000c +#define B9600 0x0000000d +#define B19200 0x0000000e +#define B38400 0x0000000f +#define EXTA B19200 +#define EXTB B38400 + +#define ADDRB 0x20000000 /* address bit */ +#define CMSPAR 0x40000000 /* mark or space (stick) parity */ +#define CRTSCTS 0x80000000 /* flow control */ + +#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */ + +/* tcflow() ACTION argument and TCXONC use these */ +#define TCOOFF 0 /* Suspend output */ +#define TCOON 1 /* Restart suspended output */ +#define TCIOFF 2 /* Send a STOP character */ +#define TCION 3 /* Send a START character */ + +/* tcflush() QUEUE_SELECTOR argument and TCFLSH use these */ +#define TCIFLUSH 0 /* Discard data received but not yet read */ +#define TCOFLUSH 1 /* Discard data written but not yet sent */ +#define TCIOFLUSH 2 /* Discard all pending data */ + +#endif /* __ASM_GENERIC_TERMBITS_COMMON_H */ |
