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| author | Fuad Tabba <fuad.tabba@linux.dev> | 2026-09-22 19:14:30 +0100 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2026-09-23 12:34:30 +0000 |
| commit | 2bc6b218717b9d08f466f88209251d54bc09b207 (patch) | |
| tree | cb91c941eccb15f94cbec4e96aa3a9c8736b5d66 /include/uapi/asm-generic/statfs.h | |
| download | linux-stable-2bc6b218717b9d08f466f88209251d54bc09b207.tar.gz linux-stable-2bc6b218717b9d08f466f88209251d54bc09b207.zip | |
arm64/boot: Disable trapping of PMZR_EL0 writes to EL2grafted
__init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2.
PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in
HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host
traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The
kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU
driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a
write from EL0 reaches the trap and takes the host down without a panic
message.
Accumulate the HDFGWTR2_EL2 bits separately, as __init_el2_fgt() already
does for HDFGWTR_EL2, and set nPMZR_EL0 with the other FEAT_PMUv3p9
bits.
Fixes: 858c7bfcb35e1 ("arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9")
Cc: stable@vger.kernel.org
Signed-off-by: Fuad Tabba <fuad.tabba@linux.dev>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Oliver Upton <oupton@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'include/uapi/asm-generic/statfs.h')
| -rw-r--r-- | include/uapi/asm-generic/statfs.h | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/include/uapi/asm-generic/statfs.h b/include/uapi/asm-generic/statfs.h new file mode 100644 index 000000000..bd35c7619 --- /dev/null +++ b/include/uapi/asm-generic/statfs.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +#ifndef _UAPI_GENERIC_STATFS_H +#define _UAPI_GENERIC_STATFS_H + +#include <linux/types.h> + + +/* + * Most 64-bit platforms use 'long', while most 32-bit platforms use '__u32'. + * Yes, they differ in signedness as well as size. + * Special cases can override it for themselves -- except for S390x, which + * is just a little too special for us. And MIPS, which I'm not touching + * with a 10' pole. + */ +#ifndef __statfs_word +#if __BITS_PER_LONG == 64 +#define __statfs_word __kernel_long_t +#else +#define __statfs_word __u32 +#endif +#endif + +struct statfs { + __statfs_word f_type; + __statfs_word f_bsize; + __statfs_word f_blocks; + __statfs_word f_bfree; + __statfs_word f_bavail; + __statfs_word f_files; + __statfs_word f_ffree; + __kernel_fsid_t f_fsid; + __statfs_word f_namelen; + __statfs_word f_frsize; + __statfs_word f_flags; + __statfs_word f_spare[4]; +}; + +/* + * ARM needs to avoid the 32-bit padding at the end, for consistency + * between EABI and OABI + */ +#ifndef ARCH_PACK_STATFS64 +#define ARCH_PACK_STATFS64 +#endif + +struct statfs64 { + __statfs_word f_type; + __statfs_word f_bsize; + __u64 f_blocks; + __u64 f_bfree; + __u64 f_bavail; + __u64 f_files; + __u64 f_ffree; + __kernel_fsid_t f_fsid; + __statfs_word f_namelen; + __statfs_word f_frsize; + __statfs_word f_flags; + __statfs_word f_spare[4]; +} ARCH_PACK_STATFS64; + +/* + * IA64 and x86_64 need to avoid the 32-bit padding at the end, + * to be compatible with the i386 ABI + */ +#ifndef ARCH_PACK_COMPAT_STATFS64 +#define ARCH_PACK_COMPAT_STATFS64 +#endif + +struct compat_statfs64 { + __u32 f_type; + __u32 f_bsize; + __u64 f_blocks; + __u64 f_bfree; + __u64 f_bavail; + __u64 f_files; + __u64 f_ffree; + __kernel_fsid_t f_fsid; + __u32 f_namelen; + __u32 f_frsize; + __u32 f_flags; + __u32 f_spare[4]; +} ARCH_PACK_COMPAT_STATFS64; + +#endif /* _UAPI_GENERIC_STATFS_H */ |
