arm64/boot: Disable trapping of PMZR_EL0 writes to EL2grafted

__init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2.
PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in
HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host
traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The
kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU
driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a
write from EL0 reaches the trap and takes the host down without a panic
message.

Accumulate the HDFGWTR2_EL2 bits separately, as __init_el2_fgt() already
does for HDFGWTR_EL2, and set nPMZR_EL0 with the other FEAT_PMUv3p9
bits.

Fixes: 858c7bfcb35e1 ("arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9")
Cc: stable@vger.kernel.org
Signed-off-by: Fuad Tabba <fuad.tabba@linux.dev>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Oliver Upton <oupton@kernel.org>
Signed-off-by: Will Deacon <will@kernel.org>

1 files changed, 66 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/r8a73a4-clock.h b/include/dt-bindings/clock/r8a73a4-clock.h
new file mode 100644
index 000000000..028ecef81
--- /dev/null
+++ b/include/dt-bindings/clock/r8a73a4-clock.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2014 Ulrich Hecht
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A73A4_H__
+#define __DT_BINDINGS_CLOCK_R8A73A4_H__
+
+/* CPG */
+#define R8A73A4_CLK_MAIN	0
+#define R8A73A4_CLK_PLL0	1
+#define R8A73A4_CLK_PLL1	2
+#define R8A73A4_CLK_PLL2	3
+#define R8A73A4_CLK_PLL2S	4
+#define R8A73A4_CLK_PLL2H	5
+#define R8A73A4_CLK_Z		6
+#define R8A73A4_CLK_Z2		7
+#define R8A73A4_CLK_I		8
+#define R8A73A4_CLK_M3		9
+#define R8A73A4_CLK_B		10
+#define R8A73A4_CLK_M1		11
+#define R8A73A4_CLK_M2		12
+#define R8A73A4_CLK_ZX		13
+#define R8A73A4_CLK_ZS		14
+#define R8A73A4_CLK_HP		15
+#define R8A73A4_CLK_ZTR		16
+#define R8A73A4_CLK_ZT		17
+
+/* MSTP1 */
+#define R8A73A4_CLK_TMU0	25
+#define R8A73A4_CLK_TMU3	21
+
+/* MSTP2 */
+#define R8A73A4_CLK_DMAC	18
+#define R8A73A4_CLK_SCIFB3	17
+#define R8A73A4_CLK_SCIFB2	16
+#define R8A73A4_CLK_SCIFB1	7
+#define R8A73A4_CLK_SCIFB0	6
+#define R8A73A4_CLK_SCIFA0	4
+#define R8A73A4_CLK_SCIFA1	3
+
+/* MSTP3 */
+#define R8A73A4_CLK_CMT1	29
+#define R8A73A4_CLK_IIC1	23
+#define R8A73A4_CLK_IIC0	18
+#define R8A73A4_CLK_IIC7	17
+#define R8A73A4_CLK_IIC6	16
+#define R8A73A4_CLK_MMCIF0	15
+#define R8A73A4_CLK_SDHI0	14
+#define R8A73A4_CLK_SDHI1	13
+#define R8A73A4_CLK_SDHI2	12
+#define R8A73A4_CLK_MMCIF1	5
+#define R8A73A4_CLK_IIC2	0
+
+/* MSTP4 */
+#define R8A73A4_CLK_IIC3	11
+#define R8A73A4_CLK_IIC4	10
+#define R8A73A4_CLK_IIC5	9
+#define R8A73A4_CLK_INTC_SYS	8
+#define R8A73A4_CLK_IRQC	7
+
+/* MSTP5 */
+#define R8A73A4_CLK_THERMAL	22
+#define R8A73A4_CLK_IIC8	15
+
+#endif /* __DT_BINDINGS_CLOCK_R8A73A4_H__ */