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authorJinke Han <jinkehan@didiglobal.com>2026-09-08 15:37:42 +0800
committerIngo Molnar <mingo@kernel.org>2026-09-17 09:48:42 +0200
commita5f7a5bb3b7f28ba7e4fa246775b29a0e5537255 (patch)
tree73fef824f9a846cf935869d0dbc5070ef6e2f741 /drivers/pinctrl/sunxi/Kconfig
downloadlinux-stable-a5f7a5bb3b7f28ba7e4fa246775b29a0e5537255.tar.gz
linux-stable-a5f7a5bb3b7f28ba7e4fa246775b29a0e5537255.zip
x86/kprobes: Fix crash when probing CS CALL instructionsgrafted
When using eBPF to probe CS CALL instructions within a function, a crash can be triggered. The eBPF tool probes offset 257 of the __hrtimer_run_queues() function: <__hrtimer_run_queues+249>: nopl 0x0(%rax,%rax,1) <__hrtimer_run_queues+254>: mov %r14,%rdi <__hrtimer_run_queues+257>: cs call <__x86_indirect_thunk_r12> <__hrtimer_run_queues+263>: mov %eax,%r12d <__hrtimer_run_queues+266>: xchg %ax,%ax <__hrtimer_run_queues+268>: mov %r13,%rdi Which triggers this crash: BUG: unable to handle page fault for address: 00000000000f41c9 #PF: supervisor write access in kernel mode #PF: error_code(0x0002) - not-present page PGD 0 P4D 0 Oops: 0002 [#1] SMP NOPTI CPU: 1 PID: 0 Comm: swapper/1 Kdump: loaded Tainted: P RIP: 0010:__hrtimer_run_queues+0x106/0x230 Note that __hrtimer_run_queues+0x106 is __hrtimer_run_queues+262, which is at the 6th byte of the above CS CALL instruction. Since the CS CALL instruction occupies 6 bytes, the exception occurred in the middle of that call instruction. The root cause is that when using eBPF tools to probe in the middle of a function, a kprobe with INT3 is used as the underlying implementation. During single-step emulation of the original CALL instruction, int3_emulate_call() assumes that the probed CALL instruction is 5 bytes long. However, the actual CS-prefixed CALL instruction occupies 6 bytes, so it constructs an incorrect exception return address. When the CPU returns from the kprobe handler, the next instruction to be executed is at the address of the last byte of that CS CALL instruction. Coincidentally, starting from that address, the CPU fetches and decodes a completely different instruction, which ultimately triggers a kernel crash. Fix the issue by using the actual instruction length obtained from the instruction decoder when constructing the exception return address, rather than relying on the hardcoded CALL_INSN_SIZE macro. [ mingo: Refined the changelog ] Fixes: 6256e668b7af ("x86/kprobes: Use int3 instead of debug trap for single-step") Suggested-by: Masami Hiramatsu (Google) <mhiramat@kernel.org> Signed-off-by: Jinke Han <jinkehan@didiglobal.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Masami Hiramatsu (Google) <mhiramat@kernel.org> Acked-by: Yafang Shao <laoar.shao@gmail.com> Acked-by: Borislav Petkov <bp@alien8.de> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://patch.msgid.link/20260908073742.GA10517@didi-ThinkCentre-M920t-N000
Diffstat (limited to 'drivers/pinctrl/sunxi/Kconfig')
-rw-r--r--drivers/pinctrl/sunxi/Kconfig144
1 files changed, 144 insertions, 0 deletions
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
new file mode 100644
index 000000000..dc62eba96
--- /dev/null
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -0,0 +1,144 @@
+# SPDX-License-Identifier: GPL-2.0-only
+if ARCH_SUNXI
+
+config PINCTRL_SUNXI
+ bool
+ select PINMUX
+ select GENERIC_PINCONF
+ select GPIOLIB
+
+config PINCTRL_SUNIV_F1C100S
+ def_bool MACH_SUNIV
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN4I_A10
+ bool "Support for the Allwinner A10, A20 and R40 PIO"
+ default MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN5I
+ bool "Support for the Allwinner A10s, A13, R8 and NextThing GR8 PIO"
+ default MACH_SUN5I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN6I_A31
+ bool "Support for the Allwinner A31 PIO"
+ default MACH_SUN6I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN6I_A31_R
+ bool "Support for the Allwinner A31 R-PIO"
+ default MACH_SUN6I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A23
+ bool "Support for the Allwinner A23 PIO"
+ default MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A33
+ bool "Support for the Allwinner A33 PIO"
+ default MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A83T
+ bool "Support for the Allwinner A83T PIO"
+ default MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A83T_R
+ bool "Support for the Allwinner A83T R-PIO"
+ default MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_A23_R
+ bool "Support for the Allwinner A23 and A33 R-PIO"
+ default MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_H3
+ bool "Support for the Allwinner H3 PIO"
+ default MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_H3_R
+ bool "Support for the Allwinner H3 and H5 R-PIO"
+ default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN8I_V3S
+ bool "Support for the Allwinner V3s PIO"
+ default MACH_SUN8I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN9I_A80
+ bool "Support for the Allwinner A80 PIO"
+ default MACH_SUN9I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN9I_A80_R
+ bool "Support for the Allwinner A80 R-PIO"
+ default MACH_SUN9I
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN20I_D1
+ bool "Support for the Allwinner D1 PIO"
+ default MACH_SUN8I || (RISCV && ARCH_SUNXI)
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64
+ bool "Support for the Allwinner A64 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A64_R
+ bool "Support for the Allwinner A64 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100
+ bool "Support for the Allwinner A100 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_A100_R
+ bool "Support for the Allwinner A100 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H5
+ bool "Support for the Allwinner H5 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H6
+ bool "Support for the Allwinner H6 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H6_R
+ bool "Support for the Allwinner H6 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H616
+ bool "Support for the Allwinner H616 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN50I_H616_R
+ bool "Support for the Allwinner H616 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN55I_A523
+ bool "Support for the Allwinner A523 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+config PINCTRL_SUN55I_A523_R
+ bool "Support for the Allwinner A523 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
+endif