Merge tag 'io_uring-7.3-20261002' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linuxgrafted

Pull io_uring fixes from Jens Axboe:

 - Fix a task_work add use-after-free with SQPOLL.

   The sqpoll thread could pop and complete the last request while
   io_req_normal_work_add() was still looking at them after the mpscq
   push.

   Use the same approach as DEFER_TASKRUN to protect from that, holding
   an RCU read lock across the add, and have exit wait for an RCU grace
   period for SQPOLL rings as well.

 - CQE32 ring fixes: correct the free entry check for 32b CQEs, zero the
   big_cqe for aux CQEs, and only post the dummy skip CQE on CQE_MIXED
   rings

 - Mark the source filter table as COW when cloning bpf filters, so
   registering another filter on the source doesn't modify the shared
   table in place

 - Initialize the task context before running the BPF loop

 - Requeue zcrx multishot receives stopped by a local resource

 - End a TX_TIMESTAMP multishot cmd when the CQ is full (lollipopkit)

* tag 'io_uring-7.3-20261002' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux:
  io_uring: fix task_work add use-after-free with SQPOLL
  io_uring/cmd_net: end TX_TIMESTAMP multishot when the CQ is full
  io_uring/zcrx: requeue multishot receives stopped by a local resource
  io_uring: initialize task context before running the BPF loop
  io_uring: zero big_cqe for aux CQEs on CQE32 rings
  io_uring: fix free entry check for 32b CQEs on CQE32 rings
  io_uring: only post the dummy skip CQE on CQE_MIXED rings
  io_uring/bpf_filter: mark source as COW when cloning filters

8 files changed, 8760 insertions, 0 deletions

diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig
new file mode 100644
index 000000000..a156c4ef5
--- /dev/null
+++ b/drivers/pinctrl/realtek/Kconfig
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config PINCTRL_RTD
+	tristate "Realtek DHC core pin controller driver"
+	depends on ARCH_REALTEK || (COMPILE_TEST && OF)
+	default ARCH_REALTEK
+	select PINMUX
+	select GENERIC_PINCONF
+	select REGMAP_MMIO
+
+config PINCTRL_RTD1619B
+	tristate "Realtek DHC 1619B pin controller driver"
+	depends on PINCTRL_RTD
+	default ARCH_REALTEK
+
+config PINCTRL_RTD1319D
+	tristate "Realtek DHC 1319D pin controller driver"
+	depends on PINCTRL_RTD
+	default ARCH_REALTEK
+
+config PINCTRL_RTD1315E
+	tristate "Realtek DHC 1315E pin controller driver"
+	depends on PINCTRL_RTD
+	default ARCH_REALTEK
+
+config PINCTRL_RTD1625
+	tristate "Realtek DHC 1625 pin controller driver"
+	depends on PINCTRL_RTD
+	default ARCH_REALTEK
+	help
+	  This driver enables support for the pin controller on the Realtek
+	  RTD1625 SoCs.
+
+	  It implements pin multiplexing for function selection and GPIO enabling.
+	  It also utilizes the generic pin configuration interface to manage
+	  electrical properties for both individual pins and pin groups.
+
+	  Say Y here to enable the pinctrl driver for RTD1625 SoCs
\ No newline at end of file
diff --git a/drivers/pinctrl/realtek/Makefile b/drivers/pinctrl/realtek/Makefile
new file mode 100644
index 000000000..595625433
--- /dev/null
+++ b/drivers/pinctrl/realtek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Realtek DHC pin control drivers
+obj-$(CONFIG_PINCTRL_RTD)		+= pinctrl-rtd.o
+obj-$(CONFIG_PINCTRL_RTD1619B)		+= pinctrl-rtd1619b.o
+obj-$(CONFIG_PINCTRL_RTD1319D)		+= pinctrl-rtd1319d.o
+obj-$(CONFIG_PINCTRL_RTD1315E)		+= pinctrl-rtd1315e.o
+obj-$(CONFIG_PINCTRL_RTD1625)		+= pinctrl-rtd1625.o
\ No newline at end of file
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c
new file mode 100644
index 000000000..602223397
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.c
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ */
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include "../core.h"
+#include "../pinctrl-utils.h"
+#include "pinctrl-rtd.h"
+
+struct rtd_pinctrl {
+	struct device *dev;
+	struct pinctrl_dev *pcdev;
+	void __iomem *base;
+	struct pinctrl_desc desc;
+	const struct rtd_pinctrl_desc *info;
+	struct regmap *regmap_pinctrl;
+	u32 **saved_regs;
+};
+
+/* custom pinconf parameters */
+#define RTD_DRIVE_STRENGTH_P (PIN_CONFIG_END + 1)
+#define RTD_DRIVE_STRENGTH_N (PIN_CONFIG_END + 2)
+#define RTD_DUTY_CYCLE (PIN_CONFIG_END + 3)
+#define RTD_HIGH_VIL (PIN_CONFIG_END + 4)
+
+static const struct pinconf_generic_params rtd_custom_bindings[] = {
+	{"realtek,drive-strength-p", RTD_DRIVE_STRENGTH_P, 0},
+	{"realtek,drive-strength-n", RTD_DRIVE_STRENGTH_N, 0},
+	{"realtek,duty-cycle", RTD_DUTY_CYCLE, 0},
+	{"realtek,high-vil-microvolt", RTD_HIGH_VIL, 0},
+};
+
+static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+	return data->info->num_groups;
+}
+
+static const char *rtd_pinctrl_get_group_name(struct pinctrl_dev *pcdev,
+					      unsigned int selector)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+	return data->info->groups[selector].name;
+}
+
+static int rtd_pinctrl_get_group_pins(struct pinctrl_dev *pcdev,
+				      unsigned int selector,
+				      const unsigned int **pins,
+				      unsigned int *num_pins)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+	*pins = data->info->groups[selector].pins;
+	*num_pins = data->info->groups[selector].num_pins;
+
+	return 0;
+}
+
+static void rtd_pinctrl_dbg_show(struct pinctrl_dev *pcdev,
+				 struct seq_file *s,
+				 unsigned int offset)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+	const struct rtd_pin_desc *mux = &data->info->muxes[offset];
+	const struct rtd_pin_mux_desc *func;
+	u32 val;
+	u32 mask;
+	u32 pin_val;
+	int is_map;
+
+	if (!mux->name) {
+		seq_puts(s, "[not defined]");
+		return;
+	}
+	val = readl_relaxed(data->base + mux->mux_offset);
+	mask = mux->mux_mask;
+	pin_val = val & mask;
+
+	is_map = 0;
+	func = &mux->functions[0];
+	seq_puts(s, "function: ");
+	while (func->name) {
+		if (func->mux_value == pin_val) {
+			is_map = 1;
+			seq_printf(s, "[%s] ", func->name);
+		} else {
+			seq_printf(s, "%s ", func->name);
+		}
+		func++;
+	}
+	if (!is_map)
+		seq_puts(s, "[not defined]");
+}
+
+static const struct pinctrl_ops rtd_pinctrl_ops = {
+	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+	.dt_free_map = pinctrl_utils_free_map,
+	.get_groups_count = rtd_pinctrl_get_groups_count,
+	.get_group_name = rtd_pinctrl_get_group_name,
+	.get_group_pins = rtd_pinctrl_get_group_pins,
+	.pin_dbg_show = rtd_pinctrl_dbg_show,
+};
+
+static int rtd_pinctrl_get_functions_count(struct pinctrl_dev *pcdev)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+	return data->info->num_functions;
+}
+
+static const char *rtd_pinctrl_get_function_name(struct pinctrl_dev *pcdev,
+						 unsigned int selector)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+	return data->info->functions[selector].name;
+}
+
+static int rtd_pinctrl_get_function_groups(struct pinctrl_dev *pcdev,
+					   unsigned int selector,
+					   const char * const **groups,
+					   unsigned int * const num_groups)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+
+	*groups = data->info->functions[selector].groups;
+	*num_groups = data->info->functions[selector].num_groups;
+
+	return 0;
+}
+
+static const struct rtd_pin_desc *rtd_pinctrl_find_mux(struct rtd_pinctrl *data, unsigned int pin)
+{
+	if (data->info->muxes[pin].name)
+		return &data->info->muxes[pin];
+
+	return NULL;
+}
+
+static int rtd_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
+				   unsigned int pin, const char *func_name)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+	const struct rtd_pin_desc *mux;
+	int ret = 0;
+	int i;
+
+	mux = rtd_pinctrl_find_mux(data, pin);
+	if (!mux)
+		return 0;
+
+	if (!mux->functions) {
+		if (!mux->name)
+			dev_err(pcdev->dev, "NULL pin has no functions\n");
+		else
+			dev_err(pcdev->dev, "No functions available for pin %s\n", mux->name);
+		return -ENOTSUPP;
+	}
+
+	for (i = 0; mux->functions[i].name; i++) {
+		if (strcmp(mux->functions[i].name, func_name) != 0)
+			continue;
+		ret = regmap_update_bits(data->regmap_pinctrl, mux->mux_offset, mux->mux_mask,
+					mux->functions[i].mux_value);
+		return ret;
+	}
+
+	if (!mux->name) {
+		dev_err(pcdev->dev, "NULL pin provided for function %s\n", func_name);
+		return -EINVAL;
+	}
+
+	dev_err(pcdev->dev, "No function %s available for pin %s\n", func_name, mux->name);
+
+	return -EINVAL;
+}
+
+static int rtd_pinctrl_set_mux(struct pinctrl_dev *pcdev,
+			       unsigned int function, unsigned int group)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+	const unsigned int *pins;
+	unsigned int num_pins;
+	const char *func_name;
+	const char *group_name;
+	int i, ret;
+
+	func_name = data->info->functions[function].name;
+	group_name = data->info->groups[group].name;
+
+	ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins);
+	if (ret) {
+		dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name);
+		return ret;
+	}
+
+	for (i = 0; i < num_pins; i++) {
+		ret = rtd_pinctrl_set_one_mux(pcdev, pins[i], func_name);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int rtd_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev,
+					   struct pinctrl_gpio_range *range,
+					   unsigned int offset)
+{
+	return rtd_pinctrl_set_one_mux(pcdev, offset, "gpio");
+}
+
+static const struct pinmux_ops rtd_pinmux_ops = {
+	.get_functions_count = rtd_pinctrl_get_functions_count,
+	.get_function_name = rtd_pinctrl_get_function_name,
+	.get_function_groups = rtd_pinctrl_get_function_groups,
+	.set_mux = rtd_pinctrl_set_mux,
+	.gpio_request_enable = rtd_pinctrl_gpio_request_enable,
+};
+
+static const struct pinctrl_pin_desc
+	*rtd_pinctrl_get_pin_by_number(struct rtd_pinctrl *data, int number)
+{
+	int i;
+
+	for (i = 0; i < data->info->num_pins; i++) {
+		if (data->info->pins[i].number == number)
+			return &data->info->pins[i];
+	}
+
+	return NULL;
+}
+
+static const struct rtd_pin_config_desc
+	*rtd_pinctrl_find_config(struct rtd_pinctrl *data, unsigned int pin)
+{
+	if (data->info->configs[pin].name)
+		return &data->info->configs[pin];
+
+	return NULL;
+}
+
+static const struct rtd_pin_sconfig_desc *rtd_pinctrl_find_sconfig(struct rtd_pinctrl *data,
+								   unsigned int pin)
+{
+	int i;
+	const struct pinctrl_pin_desc *pin_desc;
+	const char *pin_name;
+
+	pin_desc = rtd_pinctrl_get_pin_by_number(data, pin);
+	if (!pin_desc)
+		return NULL;
+
+	pin_name = pin_desc->name;
+
+	for (i = 0; i < data->info->num_sconfigs; i++) {
+		if (strcmp(data->info->sconfigs[i].name, pin_name) == 0)
+			return &data->info->sconfigs[i];
+	}
+
+	return NULL;
+}
+
+static int rtd_pconf_parse_conf(struct rtd_pinctrl *data,
+				unsigned int pinnr,
+				enum pin_config_param param,
+				unsigned int arg)
+{
+	const struct rtd_pin_config_desc *config_desc;
+	const struct rtd_pin_sconfig_desc *sconfig_desc;
+	u8 set_val = 0;
+	u16 strength;
+	u32 val;
+	u32 mask;
+	u32 pulsel_off, pulen_off, smt_off, curr_off, pow_off, reg_off, p_off, n_off,
+	    input_volt_off, sr_off, hvil_off;
+	const char *name = data->info->pins[pinnr].name;
+	int ret = 0;
+
+	config_desc = rtd_pinctrl_find_config(data, pinnr);
+	if (!config_desc) {
+		dev_err(data->dev, "Pin config unsupported for pin: %s\n", name);
+		return -ENOTSUPP;
+	}
+	switch ((u32)param) {
+	case PIN_CONFIG_INPUT_SCHMITT:
+	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+		if (config_desc->smt_offset == NA) {
+			dev_err(data->dev, "Input schmitt unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+		smt_off = config_desc->base_bit + config_desc->smt_offset;
+		reg_off = config_desc->reg_offset;
+		set_val = arg;
+
+		mask = BIT(smt_off);
+		val = set_val ? BIT(smt_off) : 0;
+		break;
+
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
+		if (config_desc->pud_en_offset == NA) {
+			dev_err(data->dev, "Push pull unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+		pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+		reg_off = config_desc->reg_offset;
+
+		mask =  BIT(pulen_off);
+		val = 0;
+		break;
+
+	case PIN_CONFIG_BIAS_DISABLE:
+		if (config_desc->pud_en_offset == NA) {
+			dev_err(data->dev, "Bias disable unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+		pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+		reg_off = config_desc->reg_offset;
+
+		mask =  BIT(pulen_off);
+		val = 0;
+		break;
+
+	case PIN_CONFIG_BIAS_PULL_UP:
+		if (config_desc->pud_en_offset == NA) {
+			dev_err(data->dev, "Bias pull up unsupported for pin:%s\n", name);
+			return -ENOTSUPP;
+		}
+		pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+		pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset;
+		reg_off = config_desc->reg_offset;
+
+		mask = BIT(pulen_off) | BIT(pulsel_off);
+		val = mask;
+		break;
+
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		if (config_desc->pud_en_offset == NA) {
+			dev_err(data->dev, "Bias pull down unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+		pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+		pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset;
+		reg_off = config_desc->reg_offset;
+
+		mask = BIT(pulen_off) | BIT(pulsel_off);
+		val = BIT(pulen_off);
+		break;
+
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		curr_off = config_desc->base_bit + config_desc->curr_offset;
+		reg_off = config_desc->reg_offset;
+		strength = arg;
+		val = 0;
+		switch (config_desc->curr_type) {
+		case PADDRI_4_8:
+			if (strength == 4)
+				val = 0;
+			else if (strength == 8)
+				val = BIT(curr_off);
+			else
+				return -EINVAL;
+			break;
+		case PADDRI_2_4:
+			if (strength == 2)
+				val = 0;
+			else if (strength == 4)
+				val = BIT(curr_off);
+			else
+				return -EINVAL;
+			break;
+		case NA:
+			dev_err(data->dev, "Drive strength unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		default:
+			return -EINVAL;
+		}
+		mask = BIT(curr_off);
+		break;
+
+	case PIN_CONFIG_POWER_SOURCE:
+		if (config_desc->power_offset == NA) {
+			dev_err(data->dev, "Power source unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+		reg_off = config_desc->reg_offset;
+		pow_off = config_desc->base_bit + config_desc->power_offset;
+		if (pow_off >= 32) {
+			reg_off += 0x4;
+			pow_off -= 32;
+		}
+		set_val = arg;
+		mask = BIT(pow_off);
+		val = set_val ? mask : 0;
+		break;
+
+	case PIN_CONFIG_SLEW_RATE:
+		if (config_desc->slew_rate_offset == NA) {
+			dev_err(data->dev, "Slew rate setting unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+
+		switch (arg) {
+		case 1:
+			set_val = 0;
+			break;
+		case 10:
+			set_val = 1;
+			break;
+		case 20:
+			set_val = 2;
+			break;
+		case 30:
+			set_val = 3;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		sr_off = config_desc->base_bit + config_desc->slew_rate_offset;
+		reg_off = config_desc->reg_offset;
+		mask = 0x3 << sr_off;
+		val = arg << sr_off;
+		break;
+
+	case PIN_CONFIG_INPUT_VOLTAGE_UV:
+		if (config_desc->input_volt_offset == NA) {
+			dev_err(data->dev, "Input voltage level setting unsupported for pin:%s\n",
+				name);
+			return -ENOTSUPP;
+		}
+
+		if (arg == 3300000)
+			set_val = 1;
+		else if (arg == 1800000)
+			set_val = 0;
+		else
+			return -EINVAL;
+
+		input_volt_off = config_desc->base_bit + config_desc->input_volt_offset;
+		reg_off = config_desc->reg_offset;
+
+		mask = BIT(input_volt_off);
+		val = set_val ? BIT(input_volt_off) : 0;
+		break;
+
+	case RTD_HIGH_VIL:
+		if (config_desc->hvil_offset == NA) {
+			dev_err(data->dev, "High vil setting unsupported for pin:%s\n", name);
+			return -ENOTSUPP;
+		}
+		hvil_off = config_desc->base_bit + config_desc->hvil_offset;
+		reg_off = config_desc->reg_offset;
+		mask = BIT(hvil_off);
+		val = 1;
+		break;
+
+	case RTD_DRIVE_STRENGTH_P:
+		sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
+		if (!sconfig_desc) {
+			dev_err(data->dev, "P driving unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+		set_val = arg;
+		reg_off = sconfig_desc->reg_offset;
+		p_off = sconfig_desc->pdrive_offset;
+		if (p_off >= 32) {
+			reg_off += 0x4;
+			p_off -= 32;
+		}
+		mask = GENMASK(p_off + sconfig_desc->pdrive_maskbits - 1, p_off);
+		val = set_val << p_off;
+		break;
+
+	case RTD_DRIVE_STRENGTH_N:
+		sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
+		if (!sconfig_desc) {
+			dev_err(data->dev, "N driving unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+		set_val = arg;
+		reg_off = sconfig_desc->reg_offset;
+		n_off = sconfig_desc->ndrive_offset;
+		if (n_off >= 32) {
+			reg_off += 0x4;
+			n_off -= 32;
+		}
+		mask = GENMASK(n_off + sconfig_desc->ndrive_maskbits - 1, n_off);
+		val = set_val << n_off;
+		break;
+
+	case RTD_DUTY_CYCLE:
+		sconfig_desc = rtd_pinctrl_find_sconfig(data, pinnr);
+		if (!sconfig_desc || sconfig_desc->dcycle_offset == NA) {
+			dev_err(data->dev, "Duty cycle unsupported for pin: %s\n", name);
+			return -ENOTSUPP;
+		}
+		set_val = arg;
+		reg_off = config_desc->reg_offset;
+		mask = GENMASK(sconfig_desc->dcycle_offset +
+		sconfig_desc->dcycle_maskbits - 1, sconfig_desc->dcycle_offset);
+		val = set_val << sconfig_desc->dcycle_offset;
+		break;
+
+	default:
+		dev_dbg(data->dev, "unsupported pinconf: %d\n", (u32)param);
+		return -ENOTSUPP;
+	}
+
+	ret = regmap_update_bits(data->regmap_pinctrl, reg_off, mask, val);
+	if (ret)
+		dev_err(data->dev, "could not update pinconf(%d) for pin(%s)\n", (u32)param, name);
+
+	return ret;
+}
+
+static int rtd_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr,
+			      unsigned long *config)
+{
+	unsigned int param = pinconf_to_config_param(*config);
+	unsigned int arg = 0;
+
+	switch (param) {
+	default:
+		return -ENOTSUPP;
+	}
+
+	*config = pinconf_to_config_packed(param, arg);
+	return 0;
+}
+
+static int rtd_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr,
+			      unsigned long *configs, unsigned int num_configs)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < num_configs; i++) {
+		ret = rtd_pconf_parse_conf(data, pinnr,
+					   pinconf_to_config_param(configs[i]),
+					   pinconf_to_config_argument(configs[i]));
+		if (ret < 0)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int rtd_pin_config_group_set(struct pinctrl_dev *pcdev, unsigned int group,
+				    unsigned long *configs, unsigned int num_configs)
+{
+	struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+	const unsigned int *pins;
+	unsigned int num_pins;
+	const char *group_name;
+	int i, ret;
+
+	group_name = data->info->groups[group].name;
+
+	ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins);
+	if (ret) {
+		dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name);
+		return ret;
+	}
+
+	for (i = 0; i < num_pins; i++) {
+		ret = rtd_pin_config_set(pcdev, pins[i], configs, num_configs);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static const struct pinconf_ops rtd_pinconf_ops = {
+	.is_generic = true,
+	.pin_config_get = rtd_pin_config_get,
+	.pin_config_set = rtd_pin_config_set,
+	.pin_config_group_set = rtd_pin_config_group_set,
+};
+
+static const struct regmap_config rtd_pinctrl_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.reg_stride = 4,
+	.use_relaxed_mmio = true,
+};
+
+static int rtd_pinctrl_init_pm(struct rtd_pinctrl *data)
+{
+	const struct rtd_pin_range *pin_range = data->info->pin_range;
+	struct device *dev = data->pcdev->dev;
+	const struct rtd_reg_range *range;
+	size_t num_entries;
+	int i;
+
+	data->saved_regs = devm_kcalloc(dev, pin_range->num_ranges, sizeof(u32 *), GFP_KERNEL);
+	if (!data->saved_regs)
+		return -ENOMEM;
+
+	for (i = 0; i < pin_range->num_ranges; i++) {
+		range = &pin_range->ranges[i];
+		num_entries = range->len / 4;
+
+		data->saved_regs[i] = devm_kzalloc(dev, num_entries * sizeof(u32), GFP_KERNEL);
+		if (!data->saved_regs[i])
+			return -ENOMEM;
+	}
+
+	return 0;
+}
+
+int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc)
+{
+	struct rtd_pinctrl *data;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	data->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(data->base))
+		return dev_err_probe(&pdev->dev, PTR_ERR(data->base),
+				     "Failed to ioremap resource\n");
+
+	data->dev = &pdev->dev;
+	data->info = desc;
+	data->desc.name = dev_name(&pdev->dev);
+	data->desc.pins = data->info->pins;
+	data->desc.npins = data->info->num_pins;
+	data->desc.pctlops = &rtd_pinctrl_ops;
+	data->desc.pmxops = &rtd_pinmux_ops;
+	data->desc.confops = &rtd_pinconf_ops;
+	data->desc.custom_params = rtd_custom_bindings;
+	data->desc.num_custom_params = ARRAY_SIZE(rtd_custom_bindings);
+	data->desc.owner = THIS_MODULE;
+	data->regmap_pinctrl = devm_regmap_init_mmio(data->dev, data->base,
+						     &rtd_pinctrl_regmap_config);
+
+	if (IS_ERR(data->regmap_pinctrl))
+		return dev_err_probe(data->dev, PTR_ERR(data->regmap_pinctrl),
+				     "Failed to init regmap\n");
+
+	data->pcdev = devm_pinctrl_register(&pdev->dev, &data->desc, data);
+	if (IS_ERR(data->pcdev))
+		return dev_err_probe(data->dev, PTR_ERR(data->pcdev),
+				     "Failed to register pinctrl\n");
+
+	platform_set_drvdata(pdev, data);
+
+	dev_dbg(&pdev->dev, "probed\n");
+
+	if (data->info->pin_range) {
+		if (rtd_pinctrl_init_pm(data))
+			return -ENOMEM;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(rtd_pinctrl_probe);
+
+static int realtek_pinctrl_suspend(struct device *dev)
+{
+	struct rtd_pinctrl *data = dev_get_drvdata(dev);
+	const struct rtd_pin_range *pin_range = data->info->pin_range;
+	const struct rtd_reg_range *range;
+	u32 *range_regs;
+	int count;
+	int i, j;
+	int ret;
+
+	if (!data->saved_regs)
+		return 0;
+
+	for (i = 0; i < pin_range->num_ranges; i++) {
+		range = &pin_range->ranges[i];
+		range_regs = data->saved_regs[i];
+		count = range->len / 4;
+
+		for (j = 0; j < count; j++) {
+			ret = regmap_read(data->regmap_pinctrl, range->offset + (j * 4),
+					  &range_regs[j]);
+			if (ret) {
+				dev_err(dev, "failed to store register 0x%x: %d\n",
+					range->offset + (j * 4), ret);
+				return ret;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int realtek_pinctrl_resume(struct device *dev)
+{
+	struct rtd_pinctrl *data = dev_get_drvdata(dev);
+	const struct rtd_pin_range *pin_range = data->info->pin_range;
+	const struct rtd_reg_range *range;
+	u32 *range_regs;
+	int count;
+	int i, j;
+	int ret;
+
+	if (!data->saved_regs)
+		return 0;
+
+	for (i = 0; i < pin_range->num_ranges; i++) {
+		range = &pin_range->ranges[i];
+		range_regs = data->saved_regs[i];
+		count = range->len / 4;
+
+		for (j = 0; j < count; j++) {
+			ret = regmap_write(data->regmap_pinctrl, range->offset + (j * 4),
+					   range_regs[j]);
+			if (ret) {
+				dev_err(dev, "failed to restore register 0x%x: %d\n",
+					range->offset + (j * 4), ret);
+				return ret;
+			}
+		}
+	}
+	return 0;
+}
+
+const struct dev_pm_ops realtek_pinctrl_pm_ops = {
+	NOIRQ_SYSTEM_SLEEP_PM_OPS(realtek_pinctrl_suspend, realtek_pinctrl_resume)
+};
+EXPORT_SYMBOL_GPL(realtek_pinctrl_pm_ops);
+
+MODULE_DESCRIPTION("Realtek DHC SoC pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.h b/drivers/pinctrl/realtek/pinctrl-rtd.h
new file mode 100644
index 000000000..77c30ea76
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ */
+
+#define NA 0xffffffff
+#define PADDRI_4_8 1
+#define PADDRI_2_4 0
+
+struct rtd_pin_group_desc {
+	const char *name;
+	const unsigned int *pins;
+	unsigned int num_pins;
+};
+
+struct rtd_pin_func_desc {
+	const char *name;
+	const char * const *groups;
+	unsigned int num_groups;
+};
+
+struct rtd_pin_mux_desc {
+	const char *name;
+	u32 mux_value;
+};
+
+struct rtd_pin_config_desc {
+	const char *name;
+	unsigned int reg_offset;
+	unsigned int base_bit;
+	unsigned int pud_en_offset;
+	unsigned int pud_sel_offset;
+	unsigned int curr_offset;
+	unsigned int smt_offset;
+	unsigned int power_offset;
+	unsigned int curr_type;
+	unsigned int input_volt_offset;
+	unsigned int slew_rate_offset;
+	unsigned int hvil_offset;
+};
+
+struct rtd_pin_sconfig_desc {
+	const char *name;
+	unsigned int reg_offset;
+	unsigned int dcycle_offset;
+	unsigned int dcycle_maskbits;
+	unsigned int ndrive_offset;
+	unsigned int ndrive_maskbits;
+	unsigned int pdrive_offset;
+	unsigned int pdrive_maskbits;
+};
+
+struct rtd_reg_range {
+	unsigned int offset;
+	size_t len;
+};
+
+struct rtd_pin_range {
+	const struct rtd_reg_range *ranges;
+	const int num_ranges;
+};
+
+struct rtd_pin_desc {
+	const char *name;
+	unsigned int mux_offset;
+	u32 mux_mask;
+	const struct rtd_pin_mux_desc *functions;
+};
+
+struct rtd_pin_reg_list {
+	unsigned int reg_offset;
+	unsigned int val;
+};
+
+#define SHIFT_LEFT(_val, _shift) ((_val) << (_shift))
+
+#define RTK_PIN_MUX(_name, _mux_off, _mux_mask, ...) \
+	{ \
+		.name = # _name, \
+		.mux_offset = _mux_off, \
+		.mux_mask = _mux_mask, \
+		.functions = (const struct rtd_pin_mux_desc []) { \
+			__VA_ARGS__, { } \
+		}, \
+	}
+
+#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \
+		       _pud_sel_off, _curr_off, _smt_off, _pow_off, _curr_type) \
+	{ \
+		.name = # _name, \
+		.reg_offset = _reg_off, \
+		.base_bit = _base_bit, \
+		.pud_en_offset = _pud_en_off, \
+		.pud_sel_offset = _pud_sel_off, \
+		.curr_offset = _curr_off, \
+		.smt_offset = _smt_off, \
+		.power_offset = _pow_off, \
+		.curr_type = _curr_type, \
+	}
+
+#define RTK_PIN_CONFIG_V2(_name, _reg_off, _base_bit, _pud_en_off, \
+			  _pud_sel_off, _curr_off, _smt_off, _pow_off, _input_volt_off, \
+			  _curr_type) \
+	{ \
+		.name = # _name, \
+		.reg_offset = _reg_off, \
+		.base_bit = _base_bit, \
+		.pud_en_offset = _pud_en_off, \
+		.pud_sel_offset = _pud_sel_off, \
+		.curr_offset = _curr_off, \
+		.smt_offset = _smt_off, \
+		.power_offset = _pow_off, \
+		.input_volt_offset = _input_volt_off, \
+		.curr_type = _curr_type, \
+	}
+
+#define RTK_PIN_CONFIG_I2C(_name, _reg_off, _base_bit, _pud_en_off, \
+			   _pud_sel_off, _curr_off, _smt_off, _hvil_off, _sr_off, _pow_off, \
+			   _input_volt_off, _curr_type) \
+	{ \
+		.name = # _name, \
+		.reg_offset = _reg_off, \
+		.base_bit = _base_bit, \
+		.pud_en_offset = _pud_en_off, \
+		.pud_sel_offset = _pud_sel_off, \
+		.curr_offset = _curr_off, \
+		.smt_offset = _smt_off, \
+		.hvil_offset = _hvil_off, \
+		.slew_rate_offset = _sr_off, \
+		.power_offset = _pow_off, \
+		.input_volt_offset = _input_volt_off, \
+		.curr_type = _curr_type, \
+	}
+
+#define RTK_PIN_SCONFIG(_name, _reg_off, _d_offset, _d_mask, \
+			_n_offset, _n_mask, _p_offset, _p_mask) \
+	{ \
+		.name = # _name, \
+		.reg_offset = _reg_off, \
+		.dcycle_offset = _d_offset, \
+		.dcycle_maskbits = _d_mask, \
+		.ndrive_offset = _n_offset, \
+		.ndrive_maskbits = _n_mask, \
+		.pdrive_offset = _p_offset, \
+		.pdrive_maskbits = _p_mask, \
+	}
+
+#define RTK_PIN_FUNC(_mux_val, _name) \
+	{ \
+		.name = _name, \
+		.mux_value = _mux_val, \
+	}
+
+struct rtd_pinctrl_desc {
+	const struct pinctrl_pin_desc *pins;
+	unsigned int num_pins;
+	const struct rtd_pin_group_desc *groups;
+	unsigned int num_groups;
+	const struct rtd_pin_func_desc *functions;
+	unsigned int num_functions;
+	const struct rtd_pin_desc *muxes;
+	unsigned int num_muxes;
+	const struct rtd_pin_config_desc *configs;
+	unsigned int num_configs;
+	const struct rtd_pin_sconfig_desc *sconfigs;
+	unsigned int num_sconfigs;
+	struct rtd_pin_reg_list *lists;
+	unsigned int num_regs;
+	const struct rtd_pin_range *pin_range;
+};
+
+int rtd_pinctrl_probe(struct platform_device *pdev, const struct rtd_pinctrl_desc *desc);
+
+extern const struct dev_pm_ops realtek_pinctrl_pm_ops;
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1315e.c b/drivers/pinctrl/realtek/pinctrl-rtd1315e.c
new file mode 100644
index 000000000..86f919122
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1315e.c
@@ -0,0 +1,1441 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC 1315E pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-rtd.h"
+
+enum rtd13xxe_iso_pins {
+	RTD1315E_ISO_GPIO_0 = 0,
+	RTD1315E_ISO_GPIO_1,
+	RTD1315E_ISO_EMMC_RST_N,
+	RTD1315E_ISO_EMMC_DD_SB,
+	RTD1315E_ISO_EMMC_CLK,
+	RTD1315E_ISO_EMMC_CMD,
+	RTD1315E_ISO_GPIO_6,
+	RTD1315E_ISO_GPIO_7,
+	RTD1315E_ISO_GPIO_8,
+	RTD1315E_ISO_GPIO_9,
+	RTD1315E_ISO_GPIO_10,
+	RTD1315E_ISO_GPIO_11,
+	RTD1315E_ISO_GPIO_12,
+	RTD1315E_ISO_GPIO_13,
+	RTD1315E_ISO_GPIO_14,
+	RTD1315E_ISO_GPIO_15,
+	RTD1315E_ISO_GPIO_16,
+	RTD1315E_ISO_GPIO_17,
+	RTD1315E_ISO_GPIO_18,
+	RTD1315E_ISO_GPIO_19,
+	RTD1315E_ISO_GPIO_20,
+	RTD1315E_ISO_EMMC_DATA_0,
+	RTD1315E_ISO_EMMC_DATA_1,
+	RTD1315E_ISO_EMMC_DATA_2,
+	RTD1315E_ISO_USB_CC2,
+	RTD1315E_ISO_GPIO_25,
+	RTD1315E_ISO_GPIO_26,
+	RTD1315E_ISO_GPIO_27,
+	RTD1315E_ISO_GPIO_28,
+	RTD1315E_ISO_GPIO_29,
+	RTD1315E_ISO_GPIO_30,
+	RTD1315E_ISO_GPIO_31,
+	RTD1315E_ISO_GPIO_32,
+	RTD1315E_ISO_GPIO_33,
+	RTD1315E_ISO_GPIO_34,
+	RTD1315E_ISO_GPIO_35,
+	RTD1315E_ISO_HIF_DATA,
+	RTD1315E_ISO_HIF_EN,
+	RTD1315E_ISO_HIF_RDY,
+	RTD1315E_ISO_HIF_CLK,
+	RTD1315E_ISO_GPIO_DUMMY_40,
+	RTD1315E_ISO_GPIO_DUMMY_41,
+	RTD1315E_ISO_GPIO_DUMMY_42,
+	RTD1315E_ISO_GPIO_DUMMY_43,
+	RTD1315E_ISO_GPIO_DUMMY_44,
+	RTD1315E_ISO_GPIO_DUMMY_45,
+	RTD1315E_ISO_GPIO_46,
+	RTD1315E_ISO_GPIO_47,
+	RTD1315E_ISO_GPIO_48,
+	RTD1315E_ISO_GPIO_49,
+	RTD1315E_ISO_GPIO_50,
+	RTD1315E_ISO_USB_CC1,
+	RTD1315E_ISO_EMMC_DATA_3,
+	RTD1315E_ISO_EMMC_DATA_4,
+	RTD1315E_ISO_IR_RX,
+	RTD1315E_ISO_UR0_RX,
+	RTD1315E_ISO_UR0_TX,
+	RTD1315E_ISO_GPIO_57,
+	RTD1315E_ISO_GPIO_58,
+	RTD1315E_ISO_GPIO_59,
+	RTD1315E_ISO_GPIO_60,
+	RTD1315E_ISO_GPIO_61,
+	RTD1315E_ISO_GPIO_62,
+	RTD1315E_ISO_GPIO_DUMMY_63,
+	RTD1315E_ISO_GPIO_DUMMY_64,
+	RTD1315E_ISO_GPIO_DUMMY_65,
+	RTD1315E_ISO_GPIO_66,
+	RTD1315E_ISO_GPIO_67,
+	RTD1315E_ISO_GPIO_68,
+	RTD1315E_ISO_GPIO_69,
+	RTD1315E_ISO_GPIO_70,
+	RTD1315E_ISO_GPIO_71,
+	RTD1315E_ISO_GPIO_72,
+	RTD1315E_ISO_GPIO_DUMMY_73,
+	RTD1315E_ISO_EMMC_DATA_5,
+	RTD1315E_ISO_EMMC_DATA_6,
+	RTD1315E_ISO_EMMC_DATA_7,
+	RTD1315E_ISO_GPIO_DUMMY_77,
+	RTD1315E_ISO_GPIO_78,
+	RTD1315E_ISO_GPIO_79,
+	RTD1315E_ISO_GPIO_80,
+	RTD1315E_ISO_GPIO_81,
+	RTD1315E_ISO_UR2_LOC,
+	RTD1315E_ISO_GSPI_LOC,
+	RTD1315E_ISO_HI_WIDTH,
+	RTD1315E_ISO_SF_EN,
+	RTD1315E_ISO_ARM_TRACE_DBG_EN,
+	RTD1315E_ISO_EJTAG_AUCPU_LOC,
+	RTD1315E_ISO_EJTAG_ACPU_LOC,
+	RTD1315E_ISO_EJTAG_VCPU_LOC,
+	RTD1315E_ISO_EJTAG_SCPU_LOC,
+	RTD1315E_ISO_DMIC_LOC,
+	RTD1315E_ISO_VTC_DMIC_LOC,
+	RTD1315E_ISO_VTC_TDM_LOC,
+	RTD1315E_ISO_VTC_I2SI_LOC,
+	RTD1315E_ISO_TDM_AI_LOC,
+	RTD1315E_ISO_AI_LOC,
+	RTD1315E_ISO_SPDIF_LOC,
+	RTD1315E_ISO_HIF_EN_LOC,
+	RTD1315E_ISO_SCAN_SWITCH,
+	RTD1315E_ISO_WD_RSET,
+	RTD1315E_ISO_BOOT_SEL,
+	RTD1315E_ISO_RESET_N,
+	RTD1315E_ISO_TESTMODE,
+};
+
+static const struct pinctrl_pin_desc rtd1315e_iso_pins[] = {
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_0, "gpio_0"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_1, "gpio_1"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_RST_N, "emmc_rst_n"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DD_SB, "emmc_dd_sb"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_CLK, "emmc_clk"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_CMD, "emmc_cmd"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_6, "gpio_6"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_7, "gpio_7"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_8, "gpio_8"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_9, "gpio_9"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_10, "gpio_10"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_11, "gpio_11"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_12, "gpio_12"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_13, "gpio_13"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_14, "gpio_14"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_15, "gpio_15"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_16, "gpio_16"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_17, "gpio_17"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_18, "gpio_18"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_19, "gpio_19"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_20, "gpio_20"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_0, "emmc_data_0"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_1, "emmc_data_1"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_2, "emmc_data_2"),
+	PINCTRL_PIN(RTD1315E_ISO_USB_CC2, "usb_cc2"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_25, "gpio_25"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_26, "gpio_26"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_27, "gpio_27"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_28, "gpio_28"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_29, "gpio_29"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_30, "gpio_30"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_31, "gpio_31"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_32, "gpio_32"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_33, "gpio_33"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_34, "gpio_34"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_35, "gpio_35"),
+	PINCTRL_PIN(RTD1315E_ISO_HIF_DATA, "hif_data"),
+	PINCTRL_PIN(RTD1315E_ISO_HIF_EN, "hif_en"),
+	PINCTRL_PIN(RTD1315E_ISO_HIF_RDY, "hif_rdy"),
+	PINCTRL_PIN(RTD1315E_ISO_HIF_CLK, "hif_clk"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_40, "gpio_dummy_40"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_41, "gpio_dummy_41"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_42, "gpio_dummy_42"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_43, "gpio_dummy_43"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_44, "gpio_dummy_44"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_45, "gpio_dummy_45"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_46, "gpio_46"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_47, "gpio_47"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_48, "gpio_48"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_49, "gpio_49"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_50, "gpio_50"),
+	PINCTRL_PIN(RTD1315E_ISO_USB_CC1, "usb_cc1"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_3, "emmc_data_3"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_4, "emmc_data_4"),
+	PINCTRL_PIN(RTD1315E_ISO_IR_RX, "ir_rx"),
+	PINCTRL_PIN(RTD1315E_ISO_UR0_RX, "ur0_rx"),
+	PINCTRL_PIN(RTD1315E_ISO_UR0_TX, "ur0_tx"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_57, "gpio_57"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_58, "gpio_58"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_59, "gpio_59"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_60, "gpio_60"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_61, "gpio_61"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_62, "gpio_62"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_63, "gpio_dummy_63"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_64, "gpio_dummy_64"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_65, "gpio_dummy_65"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_66, "gpio_66"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_67, "gpio_67"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_68, "gpio_68"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_69, "gpio_69"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_70, "gpio_70"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_71, "gpio_71"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_72, "gpio_72"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_73, "gpio_dummy_73"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_5, "emmc_data_5"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_6, "emmc_data_6"),
+	PINCTRL_PIN(RTD1315E_ISO_EMMC_DATA_7, "emmc_data_7"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_DUMMY_77, "gpio_dummy_77"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_78, "gpio_78"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_79, "gpio_79"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_80, "gpio_80"),
+	PINCTRL_PIN(RTD1315E_ISO_GPIO_81, "gpio_81"),
+	PINCTRL_PIN(RTD1315E_ISO_UR2_LOC, "ur2_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_GSPI_LOC, "gspi_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_HI_WIDTH, "hi_width"),
+	PINCTRL_PIN(RTD1315E_ISO_SF_EN, "sf_en"),
+	PINCTRL_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"),
+	PINCTRL_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_DMIC_LOC, "dmic_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_VTC_TDM_LOC, "vtc_tdm_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_TDM_AI_LOC, "tdm_ai_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_AI_LOC, "ai_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_SPDIF_LOC, "spdif_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_HIF_EN_LOC, "hif_en_loc"),
+	PINCTRL_PIN(RTD1315E_ISO_SCAN_SWITCH, "scan_switch"),
+	PINCTRL_PIN(RTD1315E_ISO_WD_RSET, "wd_rset"),
+	PINCTRL_PIN(RTD1315E_ISO_BOOT_SEL, "boot_sel"),
+	PINCTRL_PIN(RTD1315E_ISO_RESET_N, "reset_n"),
+	PINCTRL_PIN(RTD1315E_ISO_TESTMODE, "testmode"),
+};
+
+/* Tagged as __maybe_unused since there are pins we may use in the future */
+#define DECLARE_RTD1315E_PIN(_pin, _name) \
+	static const unsigned int rtd1315e_## _name ##_pins[] __maybe_unused = { _pin }
+
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_0, gpio_0);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_1, gpio_1);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_RST_N, emmc_rst_n);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DD_SB, emmc_dd_sb);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CLK, emmc_clk);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_CMD, emmc_cmd);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_6, gpio_6);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_7, gpio_7);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_8, gpio_8);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_9, gpio_9);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_10, gpio_10);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_11, gpio_11);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_12, gpio_12);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_13, gpio_13);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_14, gpio_14);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_15, gpio_15);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_16, gpio_16);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_17, gpio_17);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_18, gpio_18);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_19, gpio_19);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_20, gpio_20);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_0, emmc_data_0);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_1, emmc_data_1);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_2, emmc_data_2);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC2, usb_cc2);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_25, gpio_25);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_26, gpio_26);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_27, gpio_27);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_28, gpio_28);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_29, gpio_29);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_30, gpio_30);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_31, gpio_31);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_32, gpio_32);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_33, gpio_33);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_34, gpio_34);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_35, gpio_35);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_DATA, hif_data);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN, hif_en);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_RDY, hif_rdy);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_CLK, hif_clk);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_40, gpio_dummy_40);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_41, gpio_dummy_41);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_42, gpio_dummy_42);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_43, gpio_dummy_43);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_44, gpio_dummy_44);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_45, gpio_dummy_45);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_46, gpio_46);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_47, gpio_47);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_48, gpio_48);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_49, gpio_49);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_50, gpio_50);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_USB_CC1, usb_cc1);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_3, emmc_data_3);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_4, emmc_data_4);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_IR_RX, ir_rx);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_RX, ur0_rx);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR0_TX, ur0_tx);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_57, gpio_57);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_58, gpio_58);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_59, gpio_59);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_60, gpio_60);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_61, gpio_61);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_62, gpio_62);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_63, gpio_dummy_63);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_64, gpio_dummy_64);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_65, gpio_dummy_65);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_66, gpio_66);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_67, gpio_67);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_68, gpio_68);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_69, gpio_69);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_70, gpio_70);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_71, gpio_71);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_72, gpio_72);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_73, gpio_dummy_73);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_5, emmc_data_5);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_6, emmc_data_6);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EMMC_DATA_7, emmc_data_7);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_DUMMY_77, gpio_dummy_77);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_78, gpio_78);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_79, gpio_79);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_80, gpio_80);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GPIO_81, gpio_81);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_UR2_LOC, ur2_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_GSPI_LOC, gspi_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HI_WIDTH, hi_width);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_SF_EN, sf_en);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_DMIC_LOC, dmic_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_DMIC_LOC, vtc_dmic_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_TDM_LOC, vtc_tdm_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_VTC_I2SI_LOC, vtc_i2si_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_TDM_AI_LOC, tdm_ai_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_AI_LOC, ai_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_SPDIF_LOC, spdif_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_HIF_EN_LOC, hif_en_loc);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_SCAN_SWITCH, scan_switch);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_WD_RSET, wd_rset);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_BOOT_SEL, boot_sel);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_RESET_N, reset_n);
+DECLARE_RTD1315E_PIN(RTD1315E_ISO_TESTMODE, testmode);
+
+#define RTD1315E_GROUP(_name) \
+	{ \
+		.name = # _name, \
+		.pins = rtd1315e_ ## _name ## _pins, \
+		.num_pins = ARRAY_SIZE(rtd1315e_ ## _name ## _pins), \
+	}
+
+static const struct rtd_pin_group_desc rtd1315e_pin_groups[] = {
+	RTD1315E_GROUP(gpio_0),
+	RTD1315E_GROUP(gpio_1),
+	RTD1315E_GROUP(emmc_rst_n),
+	RTD1315E_GROUP(emmc_dd_sb),
+	RTD1315E_GROUP(emmc_clk),
+	RTD1315E_GROUP(emmc_cmd),
+	RTD1315E_GROUP(gpio_6),
+	RTD1315E_GROUP(gpio_7),
+	RTD1315E_GROUP(gpio_8),
+	RTD1315E_GROUP(gpio_9),
+	RTD1315E_GROUP(gpio_10),
+	RTD1315E_GROUP(gpio_11),
+	RTD1315E_GROUP(gpio_12),
+	RTD1315E_GROUP(gpio_13),
+	RTD1315E_GROUP(gpio_14),
+	RTD1315E_GROUP(gpio_15),
+	RTD1315E_GROUP(gpio_16),
+	RTD1315E_GROUP(gpio_17),
+	RTD1315E_GROUP(gpio_18),
+	RTD1315E_GROUP(gpio_19),
+	RTD1315E_GROUP(gpio_20),
+	RTD1315E_GROUP(emmc_data_0),
+	RTD1315E_GROUP(emmc_data_1),
+	RTD1315E_GROUP(emmc_data_2),
+	RTD1315E_GROUP(usb_cc2),
+	RTD1315E_GROUP(gpio_25),
+	RTD1315E_GROUP(gpio_26),
+	RTD1315E_GROUP(gpio_27),
+	RTD1315E_GROUP(gpio_28),
+	RTD1315E_GROUP(gpio_29),
+	RTD1315E_GROUP(gpio_30),
+	RTD1315E_GROUP(gpio_31),
+	RTD1315E_GROUP(gpio_32),
+	RTD1315E_GROUP(gpio_33),
+	RTD1315E_GROUP(gpio_34),
+	RTD1315E_GROUP(gpio_35),
+	RTD1315E_GROUP(hif_data),
+	RTD1315E_GROUP(hif_en),
+	RTD1315E_GROUP(hif_rdy),
+	RTD1315E_GROUP(hif_clk),
+	RTD1315E_GROUP(gpio_dummy_40),
+	RTD1315E_GROUP(gpio_dummy_41),
+	RTD1315E_GROUP(gpio_dummy_42),
+	RTD1315E_GROUP(gpio_dummy_43),
+	RTD1315E_GROUP(gpio_dummy_44),
+	RTD1315E_GROUP(gpio_dummy_45),
+	RTD1315E_GROUP(gpio_46),
+	RTD1315E_GROUP(gpio_47),
+	RTD1315E_GROUP(gpio_48),
+	RTD1315E_GROUP(gpio_49),
+	RTD1315E_GROUP(gpio_50),
+	RTD1315E_GROUP(usb_cc1),
+	RTD1315E_GROUP(emmc_data_3),
+	RTD1315E_GROUP(emmc_data_4),
+	RTD1315E_GROUP(ir_rx),
+	RTD1315E_GROUP(ur0_rx),
+	RTD1315E_GROUP(ur0_tx),
+	RTD1315E_GROUP(gpio_57),
+	RTD1315E_GROUP(gpio_58),
+	RTD1315E_GROUP(gpio_59),
+	RTD1315E_GROUP(gpio_60),
+	RTD1315E_GROUP(gpio_61),
+	RTD1315E_GROUP(gpio_62),
+	RTD1315E_GROUP(gpio_dummy_63),
+	RTD1315E_GROUP(gpio_dummy_64),
+	RTD1315E_GROUP(gpio_dummy_65),
+	RTD1315E_GROUP(gpio_66),
+	RTD1315E_GROUP(gpio_67),
+	RTD1315E_GROUP(gpio_68),
+	RTD1315E_GROUP(gpio_69),
+	RTD1315E_GROUP(gpio_70),
+	RTD1315E_GROUP(gpio_71),
+	RTD1315E_GROUP(gpio_72),
+	RTD1315E_GROUP(gpio_dummy_73),
+	RTD1315E_GROUP(emmc_data_5),
+	RTD1315E_GROUP(emmc_data_6),
+	RTD1315E_GROUP(emmc_data_7),
+	RTD1315E_GROUP(gpio_dummy_77),
+	RTD1315E_GROUP(gpio_78),
+	RTD1315E_GROUP(gpio_79),
+	RTD1315E_GROUP(gpio_80),
+	RTD1315E_GROUP(gpio_81),
+	RTD1315E_GROUP(ur2_loc),
+	RTD1315E_GROUP(gspi_loc),
+	RTD1315E_GROUP(hi_width),
+	RTD1315E_GROUP(sf_en),
+	RTD1315E_GROUP(arm_trace_dbg_en),
+	RTD1315E_GROUP(ejtag_aucpu_loc),
+	RTD1315E_GROUP(ejtag_acpu_loc),
+	RTD1315E_GROUP(ejtag_vcpu_loc),
+	RTD1315E_GROUP(ejtag_scpu_loc),
+	RTD1315E_GROUP(dmic_loc),
+	RTD1315E_GROUP(vtc_dmic_loc),
+	RTD1315E_GROUP(vtc_tdm_loc),
+	RTD1315E_GROUP(vtc_i2si_loc),
+	RTD1315E_GROUP(tdm_ai_loc),
+	RTD1315E_GROUP(ai_loc),
+	RTD1315E_GROUP(spdif_loc),
+	RTD1315E_GROUP(hif_en_loc),
+
+};
+
+static const char * const rtd1315e_gpio_groups[] = {
+	"gpio_0", "gpio_1", "emmc_rst_n", "emmc_dd_sb", "emmc_clk",
+	"emmc_cmd", "gpio_6", "gpio_7", "gpio_8", "gpio_9",
+	"gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14",
+	"gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19",
+	"gpio_20", "emmc_data_0", "emmc_data_1", "emmc_data_2", "usb_cc2",
+	"gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29",
+	"gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34",
+	"gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"gpio_46", "gpio_47", "gpio_48", "gpio_49",
+	"gpio_50", "usb_cc1", "emmc_data_3", "emmc_data_4", "ir_rx",
+	"ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59",
+	"gpio_60", "gpio_61", "gpio_62", "gpio_66", "gpio_67",
+	"gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+	"emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1315e_nf_groups[] = {
+	"emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0",
+	"emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4",
+	"emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1315e_emmc_groups[] = {
+	"emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+	"emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+	"emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" };
+
+static const char * const rtd1315e_ao_groups[] = {
+	"gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70",
+	"gpio_71", "gpio_72" };
+static const char * const rtd1315e_gspi_loc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" };
+static const char * const rtd1315e_gspi_loc1_groups[] = {
+	"gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" };
+static const char * const rtd1315e_uart0_groups[] = { "ur0_rx", "ur0_tx"};
+static const char * const rtd1315e_uart1_groups[] = {
+	"gpio_8", "gpio_9", "gpio_10", "gpio_11" };
+static const char * const rtd1315e_uart2_loc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" };
+static const char * const rtd1315e_uart2_loc1_groups[] = {
+	"gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" };
+static const char * const rtd1315e_i2c0_groups[] = { "gpio_12", "gpio_13" };
+static const char * const rtd1315e_i2c1_groups[] = { "gpio_16", "gpio_17" };
+static const char * const rtd1315e_i2c4_groups[] = { "gpio_34", "gpio_35" };
+static const char * const rtd1315e_i2c5_groups[] = { "gpio_29", "gpio_46" };
+static const char * const rtd1315e_pcie1_groups[] = { "gpio_25" };
+static const char * const rtd1315e_etn_led_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1315e_etn_phy_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1315e_spi_groups[] = {
+	"gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1315e_pwm0_loc0_groups[] = { "gpio_26" };
+static const char * const rtd1315e_pwm0_loc1_groups[] = { "gpio_20" };
+static const char * const rtd1315e_pwm1_loc0_groups[] = { "gpio_27" };
+static const char * const rtd1315e_pwm1_loc1_groups[] = { "gpio_29" };
+
+static const char * const rtd1315e_pwm2_loc0_groups[] = { "gpio_28" };
+static const char * const rtd1315e_pwm2_loc1_groups[] = { "gpio_30" };
+static const char * const rtd1315e_pwm3_loc0_groups[] = { "gpio_47" };
+static const char * const rtd1315e_pwm3_loc1_groups[] = { "gpio_31" };
+static const char * const rtd1315e_spdif_optical_loc0_groups[] = { "gpio_20", "spdif_loc" };
+static const char * const rtd1315e_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" };
+static const char * const rtd1315e_usb_cc1_groups[] = { "usb_cc1" };
+static const char * const rtd1315e_usb_cc2_groups[] = { "usb_cc2" };
+
+static const char * const rtd1315e_sd_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "gpio_35",
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1315e_dmic_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"gpio_62", "gpio_1", "gpio_6", "dmic_loc" };
+static const char * const rtd1315e_dmic_loc1_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "gpio_35",
+	"hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"dmic_loc" };
+static const char * const rtd1315e_ai_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"gpio_62", "gpio_1", "ai_loc" };
+static const char * const rtd1315e_ai_loc1_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "hif_data",
+	"hif_en", "hif_rdy", "hif_clk", "ai_loc" };
+static const char * const rtd1315e_tdm_ai_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59",
+	"gpio_60", "tdm_ai_loc" };
+static const char * const rtd1315e_tdm_ai_loc1_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" };
+static const char * const rtd1315e_hi_loc0_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1315e_hi_m_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1315e_vtc_i2so_groups[] = {
+	"gpio_67", "gpio_68", "gpio_69", "gpio_70"};
+static const char * const rtd1315e_vtc_i2si_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"vtc_i2si_loc" };
+static const char * const rtd1315e_vtc_i2si_loc1_groups[] = {
+	"gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"vtc_i2si_loc" };
+static const char * const rtd1315e_vtc_dmic_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60",
+	"vtc_dmic_loc" };
+static const char * const rtd1315e_vtc_dmic_loc1_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"vtc_dmic_loc" };
+static const char * const rtd1315e_vtc_tdm_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60",
+	"vtc_tdm_loc" };
+static const char * const rtd1315e_vtc_tdm_loc1_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"vtc_tdm_loc" };
+static const char * const rtd1315e_dc_fan_groups[] = { "gpio_47" };
+static const char * const rtd1315e_pll_test_loc0_groups[] = { "gpio_0", "gpio_1" };
+static const char * const rtd1315e_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" };
+static const char * const rtd1315e_spdif_groups[] = { "gpio_50" };
+static const char * const rtd1315e_ir_rx_groups[] = { "ir_rx" };
+static const char * const rtd1315e_uart2_disable_groups[] = { "ur2_loc" };
+static const char * const rtd1315e_gspi_disable_groups[] = { "gspi_loc" };
+static const char * const rtd1315e_hi_width_disable_groups[] = { "hi_width" };
+static const char * const rtd1315e_hi_width_1bit_groups[] = { "hi_width" };
+static const char * const rtd1315e_sf_disable_groups[] = { "sf_en" };
+static const char * const rtd1315e_sf_enable_groups[] = { "sf_en" };
+static const char * const rtd1315e_scpu_ejtag_loc0_groups[] = {
+	"gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+	"ejtag_scpu_loc" };
+static const char * const rtd1315e_scpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_scpu_loc" };
+static const char * const rtd1315e_scpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_scpu_loc" };
+static const char * const rtd1315e_scpu_ejtag_loc3_groups[] = {
+	"hif_data" };
+static const char * const rtd1315e_acpu_ejtag_loc0_groups[] = {
+	"gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+	"ejtag_acpu_loc" };
+static const char * const rtd1315e_acpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_acpu_loc" };
+static const char * const rtd1315e_acpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_acpu_loc" };
+static const char * const rtd1315e_vcpu_ejtag_loc0_groups[] = {
+	"gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+	"ejtag_vcpu_loc" };
+static const char * const rtd1315e_vcpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_vcpu_loc" };
+static const char * const rtd1315e_vcpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_vcpu_loc" };
+static const char * const rtd1315e_aucpu_ejtag_loc0_groups[] = {
+	"gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72",
+	"ejtag_aucpu_loc" };
+static const char * const rtd1315e_aucpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_aucpu_loc" };
+static const char * const rtd1315e_aucpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_aucpu_loc" };
+static const char * const rtd1315e_gpu_ejtag_groups[] = {
+	"gpio_68", "gpio_69", "gpio_70", "gpio_71", "gpio_72" };
+
+static const char * const rtd1315e_iso_tristate_groups[] = {
+	"emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+	"emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+	"emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"gpio_1", "gpio_7", "gpio_8", "gpio_9", "gpio_10",
+	"gpio_11", "usb_cc2", "gpio_32", "gpio_33", "hif_data",
+	"hif_en", "hif_rdy", "hif_clk", "ir_rx", "ur0_rx",
+	"ur0_tx", "gpio_66", "gpio_67", "gpio_68", "gpio_69", "gpio_70",
+	"gpio_71", "gpio_72", "gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1315e_dbg_out0_groups[] = {
+	"gpio_0", "gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26",
+	"gpio_27", "gpio_28", "gpio_29", "gpio_30", "gpio_34", "gpio_35",
+	"gpio_46", "gpio_48", "gpio_49", "usb_cc1", "gpio_57", "gpio_58", "gpio_59", "gpio_60" };
+static const char * const rtd1315e_dbg_out1_groups[] = {
+	"gpio_6", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20",
+	"gpio_25", "gpio_31", "gpio_47", "gpio_50", "gpio_59", "gpio_61",
+	"gpio_62" };
+static const char * const rtd1315e_standby_dbg_groups[] = {
+	"gpio_1", "gpio_6", "ir_rx" };
+static const char * const rtd1315e_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1315e_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1315e_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" };
+static const char * const rtd1315e_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" };
+static const char * const rtd1315e_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" };
+static const char * const rtd1315e_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" };
+static const char * const rtd1315e_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" };
+static const char * const rtd1315e_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" };
+static const char * const rtd1315e_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" };
+static const char * const rtd1315e_tdm_ai_disable_groups[] = { "tdm_ai_loc" };
+static const char * const rtd1315e_ai_disable_groups[] = { "ai_loc" };
+static const char * const rtd1315e_spdif_disable_groups[] = { "spdif_loc" };
+static const char * const rtd1315e_hif_disable_groups[] = { "hif_en_loc" };
+static const char * const rtd1315e_hif_enable_groups[] = { "hif_en_loc" };
+static const char * const rtd1315e_test_loop_groups[] = { "gpio_50" };
+static const char * const rtd1315e_pmic_pwrup_groups[] = { "gpio_78" };
+
+#define RTD1315E_FUNC(_name) \
+	{ \
+		.name = # _name, \
+		.groups = rtd1315e_ ## _name ## _groups, \
+		.num_groups = ARRAY_SIZE(rtd1315e_ ## _name ## _groups), \
+	}
+
+static const struct rtd_pin_func_desc rtd1315e_pin_functions[] = {
+	RTD1315E_FUNC(gpio),
+	RTD1315E_FUNC(nf),
+	RTD1315E_FUNC(emmc),
+	RTD1315E_FUNC(ao),
+	RTD1315E_FUNC(gspi_loc0),
+	RTD1315E_FUNC(gspi_loc1),
+	RTD1315E_FUNC(uart0),
+	RTD1315E_FUNC(uart1),
+	RTD1315E_FUNC(uart2_loc0),
+	RTD1315E_FUNC(uart2_loc1),
+	RTD1315E_FUNC(i2c0),
+	RTD1315E_FUNC(i2c1),
+	RTD1315E_FUNC(i2c4),
+	RTD1315E_FUNC(i2c5),
+	RTD1315E_FUNC(pcie1),
+	RTD1315E_FUNC(etn_led),
+	RTD1315E_FUNC(etn_phy),
+	RTD1315E_FUNC(spi),
+	RTD1315E_FUNC(pwm0_loc0),
+	RTD1315E_FUNC(pwm0_loc1),
+	RTD1315E_FUNC(pwm1_loc0),
+	RTD1315E_FUNC(pwm1_loc1),
+	RTD1315E_FUNC(pwm2_loc0),
+	RTD1315E_FUNC(pwm2_loc1),
+	RTD1315E_FUNC(pwm3_loc0),
+	RTD1315E_FUNC(pwm3_loc1),
+	RTD1315E_FUNC(spdif_optical_loc0),
+	RTD1315E_FUNC(spdif_optical_loc1),
+	RTD1315E_FUNC(usb_cc1),
+	RTD1315E_FUNC(usb_cc2),
+	RTD1315E_FUNC(sd),
+	RTD1315E_FUNC(dmic_loc0),
+	RTD1315E_FUNC(dmic_loc1),
+	RTD1315E_FUNC(ai_loc0),
+	RTD1315E_FUNC(ai_loc1),
+	RTD1315E_FUNC(tdm_ai_loc0),
+	RTD1315E_FUNC(tdm_ai_loc1),
+	RTD1315E_FUNC(hi_loc0),
+	RTD1315E_FUNC(hi_m),
+	RTD1315E_FUNC(vtc_i2so),
+	RTD1315E_FUNC(vtc_i2si_loc0),
+	RTD1315E_FUNC(vtc_i2si_loc1),
+	RTD1315E_FUNC(vtc_dmic_loc0),
+	RTD1315E_FUNC(vtc_dmic_loc1),
+	RTD1315E_FUNC(vtc_tdm_loc0),
+	RTD1315E_FUNC(vtc_tdm_loc1),
+	RTD1315E_FUNC(dc_fan),
+	RTD1315E_FUNC(pll_test_loc0),
+	RTD1315E_FUNC(pll_test_loc1),
+	RTD1315E_FUNC(ir_rx),
+	RTD1315E_FUNC(uart2_disable),
+	RTD1315E_FUNC(gspi_disable),
+	RTD1315E_FUNC(hi_width_disable),
+	RTD1315E_FUNC(hi_width_1bit),
+	RTD1315E_FUNC(sf_disable),
+	RTD1315E_FUNC(sf_enable),
+	RTD1315E_FUNC(scpu_ejtag_loc0),
+	RTD1315E_FUNC(scpu_ejtag_loc1),
+	RTD1315E_FUNC(scpu_ejtag_loc2),
+	RTD1315E_FUNC(scpu_ejtag_loc3),
+	RTD1315E_FUNC(acpu_ejtag_loc0),
+	RTD1315E_FUNC(acpu_ejtag_loc1),
+	RTD1315E_FUNC(acpu_ejtag_loc2),
+	RTD1315E_FUNC(vcpu_ejtag_loc0),
+	RTD1315E_FUNC(vcpu_ejtag_loc1),
+	RTD1315E_FUNC(vcpu_ejtag_loc2),
+	RTD1315E_FUNC(aucpu_ejtag_loc0),
+	RTD1315E_FUNC(aucpu_ejtag_loc1),
+	RTD1315E_FUNC(aucpu_ejtag_loc2),
+	RTD1315E_FUNC(gpu_ejtag),
+	RTD1315E_FUNC(iso_tristate),
+	RTD1315E_FUNC(dbg_out0),
+	RTD1315E_FUNC(dbg_out1),
+	RTD1315E_FUNC(standby_dbg),
+	RTD1315E_FUNC(spdif),
+	RTD1315E_FUNC(arm_trace_debug_disable),
+	RTD1315E_FUNC(arm_trace_debug_enable),
+	RTD1315E_FUNC(aucpu_ejtag_disable),
+	RTD1315E_FUNC(acpu_ejtag_disable),
+	RTD1315E_FUNC(vcpu_ejtag_disable),
+	RTD1315E_FUNC(scpu_ejtag_disable),
+	RTD1315E_FUNC(vtc_dmic_loc_disable),
+	RTD1315E_FUNC(vtc_tdm_disable),
+	RTD1315E_FUNC(vtc_i2si_disable),
+	RTD1315E_FUNC(tdm_ai_disable),
+	RTD1315E_FUNC(ai_disable),
+	RTD1315E_FUNC(spdif_disable),
+	RTD1315E_FUNC(hif_disable),
+	RTD1315E_FUNC(hif_enable),
+	RTD1315E_FUNC(test_loop),
+	RTD1315E_FUNC(pmic_pwrup),
+};
+
+#undef RTD1315E_FUNC
+
+static const struct rtd_pin_desc rtd1315e_iso_muxes[ARRAY_SIZE(rtd1315e_iso_pins)] = {
+	[RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pll_test_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "standby_dbg"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pll_test_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "standby_dbg"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1315E_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x8, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x8, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+	[RTD1315E_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0xc, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0xc, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0xc, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0xc, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0xc, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "spdif_optical_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+	[RTD1315E_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0xc, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "usb_cc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm0_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")),
+
+	[RTD1315E_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x10, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x10, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x10, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "pwm1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x10, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pwm2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x10, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm3_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x10, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x10, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x10, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "i2c4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")),
+
+	[RTD1315E_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x14, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "i2c4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+	[RTD1315E_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x14, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1315E_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x14, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1315E_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x14, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1315E_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x14, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x14, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "dc_fan"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pwm3_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "pll_test_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")),
+
+	[RTD1315E_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x18, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x18, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "test_loop"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out1")),
+	[RTD1315E_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x18, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "usb_cc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+	[RTD1315E_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x18, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ir_rx"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "standby_dbg"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1315E_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x18, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1315E_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x18, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x18, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x18, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out0")),
+
+	[RTD1315E_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x1c, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 0), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x1c, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+	[RTD1315E_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x1c, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x1c, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")),
+	[RTD1315E_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x1c, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x1c, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2so"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x1c, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "gpu_ejtag"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2so"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x1c, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "gpu_ejtag"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2so"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1315E_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x20, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "gpu_ejtag"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x20, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "gpu_ejtag"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x20, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "gpu_ejtag"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x20, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pmic_pwrup"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x20, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x20, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1315E_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x20, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+
+	[RTD1315E_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")),
+	[RTD1315E_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")),
+	[RTD1315E_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")),
+	[RTD1315E_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")),
+	[RTD1315E_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")),
+	[RTD1315E_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")),
+	[RTD1315E_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")),
+	[RTD1315E_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")),
+	[RTD1315E_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")),
+	[RTD1315E_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")),
+
+	[RTD1315E_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")),
+	[RTD1315E_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")),
+	[RTD1315E_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")),
+	[RTD1315E_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")),
+	[RTD1315E_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")),
+	[RTD1315E_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")),
+
+	[RTD1315E_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")),
+};
+
+static const struct rtd_pin_config_desc rtd1315e_iso_configs[ARRAY_SIZE(rtd1315e_iso_pins)] = {
+	[RTD1315E_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x24, 0, 0, 1, NA, 2, 3, NA),
+	[RTD1315E_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x24, 4, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x24, 17, 0, 1, NA, 2, 13, NA),
+	[RTD1315E_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x28, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x28, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x2c, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x2c, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x30, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x30, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x34, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x34, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x38, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x38, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x3c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x3c, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x3c, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x3c, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x3c, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x3c, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x40, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x40, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x40, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x40, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x40, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x40, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x44, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x44, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x44, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x44, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x44, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x44, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 6, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x48, 12, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x48, 17, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x4c, 5, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x4c, 18, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x50, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x54, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x54, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x54, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x58, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x58, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x58, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x58, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x5c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x5c, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x5c, 10, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x60, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x64, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x68, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x68, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x68, 26, 0, 1, NA, 2, 12, NA),
+	[RTD1315E_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x6c, 7, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x6c, 12, 0, 1, NA, 2, 3, PADDRI_4_8),
+	[RTD1315E_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x6c, 16, NA, NA, 0, 1, 2, PADDRI_4_8),
+	[RTD1315E_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x6c, 19, 0, 1, NA, 2, 3, PADDRI_4_8),
+	[RTD1315E_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x6c, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x6c, 28, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1315E_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x70, 1, NA, NA, 0, 1, 2, PADDRI_4_8),
+	[RTD1315E_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x70, 4, NA, NA, 0, 1, 2, PADDRI_4_8),
+	[RTD1315E_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x70, 7, 1, 2, 0, 3, 4, PADDRI_4_8),
+};
+
+static const struct rtd_pin_sconfig_desc rtd1315e_iso_sconfigs[] = {
+	RTK_PIN_SCONFIG(emmc_clk, 0x24, 7, 3, 10, 3, 13, 3),
+	RTK_PIN_SCONFIG(emmc_cmd, 0x24, 20, 3, 23, 3, 26, 3),
+	RTK_PIN_SCONFIG(emmc_data_0, 0x28, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_1, 0x28, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_2, 0x2c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_3, 0x2c, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_4, 0x30, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_5, 0x30, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_6, 0x34, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_7, 0x34, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_dd_sb, 0x38, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_rst_n, 0x38, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_32, 0x4c, 8, 3, 11, 3, 14, 3),
+	RTK_PIN_SCONFIG(gpio_33, 0x4c, 21, 3, 24, 3, 27, 3),
+	RTK_PIN_SCONFIG(gpio_78, 0x5c, 13, 3, 16, 3, 19, 3),
+	RTK_PIN_SCONFIG(gpio_79, 0x60, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_80, 0x60, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_81, 0x64, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(hif_clk, 0x64, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(hif_data, 0x68, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(hif_en, 0x68, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(hif_rdy, 0x68, 29, 3, 32, 3, 35, 3),
+
+};
+
+static const struct rtd_pinctrl_desc rtd1315e_iso_pinctrl_desc = {
+	.pins = rtd1315e_iso_pins,
+	.num_pins = ARRAY_SIZE(rtd1315e_iso_pins),
+	.groups = rtd1315e_pin_groups,
+	.num_groups = ARRAY_SIZE(rtd1315e_pin_groups),
+	.functions = rtd1315e_pin_functions,
+	.num_functions = ARRAY_SIZE(rtd1315e_pin_functions),
+	.muxes = rtd1315e_iso_muxes,
+	.num_muxes = ARRAY_SIZE(rtd1315e_iso_muxes),
+	.configs = rtd1315e_iso_configs,
+	.num_configs = ARRAY_SIZE(rtd1315e_iso_configs),
+	.sconfigs = rtd1315e_iso_sconfigs,
+	.num_sconfigs = ARRAY_SIZE(rtd1315e_iso_sconfigs),
+};
+
+static int rtd1315e_pinctrl_probe(struct platform_device *pdev)
+{
+	return rtd_pinctrl_probe(pdev, &rtd1315e_iso_pinctrl_desc);
+}
+
+static const struct of_device_id rtd1315e_pinctrl_of_match[] = {
+	{ .compatible = "realtek,rtd1315e-pinctrl", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, rtd1315e_pinctrl_of_match);
+
+static struct platform_driver rtd1315e_pinctrl_driver = {
+	.driver = {
+		.name = "rtd1315e-pinctrl",
+		.of_match_table = rtd1315e_pinctrl_of_match,
+	},
+	.probe = rtd1315e_pinctrl_probe,
+};
+
+static int __init rtd1315e_pinctrl_init(void)
+{
+	return platform_driver_register(&rtd1315e_pinctrl_driver);
+}
+arch_initcall(rtd1315e_pinctrl_init);
+
+static void __exit rtd1315e_pinctrl_exit(void)
+{
+	platform_driver_unregister(&rtd1315e_pinctrl_driver);
+}
+module_exit(rtd1315e_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Realtek Semiconductor Corporation");
+MODULE_DESCRIPTION("Realtek DHC SoC RTD1315E pinctrl driver");
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1319d.c b/drivers/pinctrl/realtek/pinctrl-rtd1319d.c
new file mode 100644
index 000000000..474c337d2
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1319d.c
@@ -0,0 +1,1611 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC 1319D pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-rtd.h"
+
+enum rtd13xxd_iso_pins {
+	RTD1319D_ISO_GPIO_0 = 0,
+	RTD1319D_ISO_GPIO_1,
+	RTD1319D_ISO_GPIO_2,
+	RTD1319D_ISO_GPIO_3,
+	RTD1319D_ISO_GPIO_4,
+	RTD1319D_ISO_GPIO_5,
+	RTD1319D_ISO_GPIO_6,
+	RTD1319D_ISO_GPIO_7,
+	RTD1319D_ISO_GPIO_8,
+	RTD1319D_ISO_GPIO_9,
+	RTD1319D_ISO_GPIO_10,
+	RTD1319D_ISO_GPIO_11,
+	RTD1319D_ISO_GPIO_12,
+	RTD1319D_ISO_GPIO_13,
+	RTD1319D_ISO_GPIO_14,
+	RTD1319D_ISO_GPIO_15,
+	RTD1319D_ISO_GPIO_16,
+	RTD1319D_ISO_GPIO_17,
+	RTD1319D_ISO_GPIO_18,
+	RTD1319D_ISO_GPIO_19,
+	RTD1319D_ISO_GPIO_20,
+	RTD1319D_ISO_GPIO_21,
+	RTD1319D_ISO_GPIO_22,
+	RTD1319D_ISO_GPIO_23,
+	RTD1319D_ISO_USB_CC2,
+	RTD1319D_ISO_GPIO_25,
+	RTD1319D_ISO_GPIO_26,
+	RTD1319D_ISO_GPIO_27,
+	RTD1319D_ISO_GPIO_28,
+	RTD1319D_ISO_GPIO_29,
+	RTD1319D_ISO_GPIO_30,
+	RTD1319D_ISO_GPIO_31,
+	RTD1319D_ISO_GPIO_32,
+	RTD1319D_ISO_GPIO_33,
+	RTD1319D_ISO_GPIO_34,
+	RTD1319D_ISO_GPIO_35,
+	RTD1319D_ISO_HIF_DATA,
+	RTD1319D_ISO_HIF_EN,
+	RTD1319D_ISO_HIF_RDY,
+	RTD1319D_ISO_HIF_CLK,
+	RTD1319D_ISO_GPIO_40,
+	RTD1319D_ISO_GPIO_41,
+	RTD1319D_ISO_GPIO_42,
+	RTD1319D_ISO_GPIO_43,
+	RTD1319D_ISO_GPIO_44,
+	RTD1319D_ISO_GPIO_45,
+	RTD1319D_ISO_GPIO_46,
+	RTD1319D_ISO_GPIO_47,
+	RTD1319D_ISO_GPIO_48,
+	RTD1319D_ISO_GPIO_49,
+	RTD1319D_ISO_GPIO_50,
+	RTD1319D_ISO_USB_CC1,
+	RTD1319D_ISO_GPIO_52,
+	RTD1319D_ISO_GPIO_53,
+	RTD1319D_ISO_IR_RX,
+	RTD1319D_ISO_UR0_RX,
+	RTD1319D_ISO_UR0_TX,
+	RTD1319D_ISO_GPIO_57,
+	RTD1319D_ISO_GPIO_58,
+	RTD1319D_ISO_GPIO_59,
+	RTD1319D_ISO_GPIO_60,
+	RTD1319D_ISO_GPIO_61,
+	RTD1319D_ISO_GPIO_62,
+	RTD1319D_ISO_GPIO_63,
+	RTD1319D_ISO_GPIO_64,
+	RTD1319D_ISO_EMMC_RST_N,
+	RTD1319D_ISO_EMMC_DD_SB,
+	RTD1319D_ISO_EMMC_CLK,
+	RTD1319D_ISO_EMMC_CMD,
+	RTD1319D_ISO_EMMC_DATA_0,
+	RTD1319D_ISO_EMMC_DATA_1,
+	RTD1319D_ISO_EMMC_DATA_2,
+	RTD1319D_ISO_EMMC_DATA_3,
+	RTD1319D_ISO_EMMC_DATA_4,
+	RTD1319D_ISO_EMMC_DATA_5,
+	RTD1319D_ISO_EMMC_DATA_6,
+	RTD1319D_ISO_EMMC_DATA_7,
+	RTD1319D_ISO_GPIO_DUMMY_77,
+	RTD1319D_ISO_GPIO_78,
+	RTD1319D_ISO_GPIO_79,
+	RTD1319D_ISO_GPIO_80,
+	RTD1319D_ISO_GPIO_81,
+	RTD1319D_ISO_UR2_LOC,
+	RTD1319D_ISO_GSPI_LOC,
+	RTD1319D_ISO_HI_WIDTH,
+	RTD1319D_ISO_SF_EN,
+	RTD1319D_ISO_ARM_TRACE_DBG_EN,
+	RTD1319D_ISO_EJTAG_AUCPU_LOC,
+	RTD1319D_ISO_EJTAG_ACPU_LOC,
+	RTD1319D_ISO_EJTAG_VCPU_LOC,
+	RTD1319D_ISO_EJTAG_SCPU_LOC,
+	RTD1319D_ISO_DMIC_LOC,
+	RTD1319D_ISO_EJTAG_SECPU_LOC,
+	RTD1319D_ISO_VTC_DMIC_LOC,
+	RTD1319D_ISO_VTC_TDM_LOC,
+	RTD1319D_ISO_VTC_I2SI_LOC,
+	RTD1319D_ISO_TDM_AI_LOC,
+	RTD1319D_ISO_AI_LOC,
+	RTD1319D_ISO_SPDIF_LOC,
+	RTD1319D_ISO_HIF_EN_LOC,
+	RTD1319D_ISO_SC0_LOC,
+	RTD1319D_ISO_SC1_LOC,
+	RTD1319D_ISO_SCAN_SWITCH,
+	RTD1319D_ISO_WD_RSET,
+	RTD1319D_ISO_BOOT_SEL,
+	RTD1319D_ISO_RESET_N,
+	RTD1319D_ISO_TESTMODE,
+};
+
+static const struct pinctrl_pin_desc rtd1319d_iso_pins[] = {
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_0, "gpio_0"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_1, "gpio_1"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_2, "gpio_2"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_3, "gpio_3"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_4, "gpio_4"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_5, "gpio_5"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_6, "gpio_6"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_7, "gpio_7"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_8, "gpio_8"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_9, "gpio_9"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_10, "gpio_10"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_11, "gpio_11"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_12, "gpio_12"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_13, "gpio_13"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_14, "gpio_14"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_15, "gpio_15"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_16, "gpio_16"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_17, "gpio_17"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_18, "gpio_18"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_19, "gpio_19"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_20, "gpio_20"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_21, "gpio_21"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_22, "gpio_22"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_23, "gpio_23"),
+	PINCTRL_PIN(RTD1319D_ISO_USB_CC2, "usb_cc2"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_25, "gpio_25"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_26, "gpio_26"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_27, "gpio_27"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_28, "gpio_28"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_29, "gpio_29"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_30, "gpio_30"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_31, "gpio_31"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_32, "gpio_32"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_33, "gpio_33"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_34, "gpio_34"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_35, "gpio_35"),
+	PINCTRL_PIN(RTD1319D_ISO_HIF_DATA, "hif_data"),
+	PINCTRL_PIN(RTD1319D_ISO_HIF_EN, "hif_en"),
+	PINCTRL_PIN(RTD1319D_ISO_HIF_RDY, "hif_rdy"),
+	PINCTRL_PIN(RTD1319D_ISO_HIF_CLK, "hif_clk"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_40, "gpio_40"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_41, "gpio_41"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_42, "gpio_42"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_43, "gpio_43"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_44, "gpio_44"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_45, "gpio_45"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_46, "gpio_46"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_47, "gpio_47"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_48, "gpio_48"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_49, "gpio_49"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_50, "gpio_50"),
+	PINCTRL_PIN(RTD1319D_ISO_USB_CC1, "usb_cc1"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_52, "gpio_52"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_53, "gpio_53"),
+	PINCTRL_PIN(RTD1319D_ISO_IR_RX, "ir_rx"),
+	PINCTRL_PIN(RTD1319D_ISO_UR0_RX, "ur0_rx"),
+	PINCTRL_PIN(RTD1319D_ISO_UR0_TX, "ur0_tx"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_57, "gpio_57"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_58, "gpio_58"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_59, "gpio_59"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_60, "gpio_60"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_61, "gpio_61"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_62, "gpio_62"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_63, "gpio_63"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_64, "gpio_64"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_RST_N, "emmc_rst_n"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DD_SB, "emmc_dd_sb"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_CLK, "emmc_clk"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_CMD, "emmc_cmd"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_0, "emmc_data_0"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_1, "emmc_data_1"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_2, "emmc_data_2"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_3, "emmc_data_3"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_4, "emmc_data_4"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_5, "emmc_data_5"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_6, "emmc_data_6"),
+	PINCTRL_PIN(RTD1319D_ISO_EMMC_DATA_7, "emmc_data_7"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_DUMMY_77, "dummy"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_78, "gpio_78"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_79, "gpio_79"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_80, "gpio_80"),
+	PINCTRL_PIN(RTD1319D_ISO_GPIO_81, "gpio_81"),
+	PINCTRL_PIN(RTD1319D_ISO_UR2_LOC, "ur2_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_GSPI_LOC, "gspi_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_HI_WIDTH, "hi_width"),
+	PINCTRL_PIN(RTD1319D_ISO_SF_EN, "sf_en"),
+	PINCTRL_PIN(RTD1319D_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"),
+	PINCTRL_PIN(RTD1319D_ISO_EJTAG_AUCPU_LOC, "ejtag_aucpu_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_DMIC_LOC, "dmic_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_EJTAG_SECPU_LOC, "ejtag_secpu_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_VTC_DMIC_LOC, "vtc_dmic_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_VTC_TDM_LOC, "vtc_tdm_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_VTC_I2SI_LOC, "vtc_i2si_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_TDM_AI_LOC, "tdm_ai_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_AI_LOC, "ai_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_SPDIF_LOC, "spdif_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_HIF_EN_LOC, "hif_en_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_SC0_LOC, "sc0_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_SC1_LOC, "sc1_loc"),
+	PINCTRL_PIN(RTD1319D_ISO_SCAN_SWITCH, "scan_switch"),
+	PINCTRL_PIN(RTD1319D_ISO_WD_RSET, "wd_rset"),
+	PINCTRL_PIN(RTD1319D_ISO_BOOT_SEL, "boot_sel"),
+	PINCTRL_PIN(RTD1319D_ISO_RESET_N, "reset_n"),
+	PINCTRL_PIN(RTD1319D_ISO_TESTMODE, "testmode"),
+};
+
+/* Tagged as __maybe_unused since there are pins we may use in the future */
+#define DECLARE_RTD1319D_PIN(_pin, _name) \
+	static const unsigned int rtd1319d_## _name ##_pins[] __maybe_unused = { _pin }
+
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_0, gpio_0);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_1, gpio_1);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_2, gpio_2);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_3, gpio_3);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_4, gpio_4);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_5, gpio_5);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_6, gpio_6);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_7, gpio_7);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_8, gpio_8);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_9, gpio_9);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_10, gpio_10);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_11, gpio_11);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_12, gpio_12);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_13, gpio_13);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_14, gpio_14);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_15, gpio_15);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_16, gpio_16);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_17, gpio_17);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_18, gpio_18);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_19, gpio_19);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_20, gpio_20);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_21, gpio_21);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_22, gpio_22);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_23, gpio_23);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_USB_CC2, usb_cc2);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_25, gpio_25);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_26, gpio_26);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_27, gpio_27);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_28, gpio_28);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_29, gpio_29);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_30, gpio_30);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_31, gpio_31);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_32, gpio_32);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_33, gpio_33);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_34, gpio_34);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_35, gpio_35);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_DATA, hif_data);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_EN, hif_en);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_RDY, hif_rdy);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_CLK, hif_clk);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_40, gpio_40);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_41, gpio_41);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_42, gpio_42);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_43, gpio_43);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_44, gpio_44);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_45, gpio_45);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_46, gpio_46);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_47, gpio_47);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_48, gpio_48);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_49, gpio_49);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_50, gpio_50);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_USB_CC1, usb_cc1);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_52, gpio_52);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_53, gpio_53);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_IR_RX, ir_rx);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR0_RX, ur0_rx);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR0_TX, ur0_tx);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_57, gpio_57);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_58, gpio_58);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_59, gpio_59);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_60, gpio_60);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_61, gpio_61);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_62, gpio_62);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_63, gpio_63);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_64, gpio_64);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_RST_N, emmc_rst_n);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DD_SB, emmc_dd_sb);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_CLK, emmc_clk);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_CMD, emmc_cmd);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_0, emmc_data_0);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_1, emmc_data_1);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_2, emmc_data_2);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_3, emmc_data_3);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_4, emmc_data_4);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_5, emmc_data_5);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_6, emmc_data_6);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EMMC_DATA_7, emmc_data_7);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_78, gpio_78);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_79, gpio_79);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_80, gpio_80);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GPIO_81, gpio_81);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_UR2_LOC, ur2_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_GSPI_LOC, gspi_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HI_WIDTH, hi_width);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SF_EN, sf_en);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_AUCPU_LOC, ejtag_aucpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_DMIC_LOC, dmic_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_EJTAG_SECPU_LOC, ejtag_secpu_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_DMIC_LOC, vtc_dmic_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_TDM_LOC, vtc_tdm_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_VTC_I2SI_LOC, vtc_i2si_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_TDM_AI_LOC, tdm_ai_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_AI_LOC, ai_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SPDIF_LOC, spdif_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_HIF_EN_LOC, hif_en_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SC0_LOC, sc0_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SC1_LOC, sc1_loc);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_SCAN_SWITCH, scan_switch);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_WD_RSET, wd_rset);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_BOOT_SEL, boot_sel);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_RESET_N, reset_n);
+DECLARE_RTD1319D_PIN(RTD1319D_ISO_TESTMODE, testmode);
+
+#define RTD1319D_GROUP(_name) \
+	{ \
+		.name = # _name, \
+		.pins = rtd1319d_ ## _name ## _pins, \
+		.num_pins = ARRAY_SIZE(rtd1319d_ ## _name ## _pins), \
+	}
+
+static const struct rtd_pin_group_desc rtd1319d_pin_groups[] = {
+	RTD1319D_GROUP(gpio_0),
+	RTD1319D_GROUP(gpio_1),
+	RTD1319D_GROUP(gpio_2),
+	RTD1319D_GROUP(gpio_3),
+	RTD1319D_GROUP(gpio_4),
+	RTD1319D_GROUP(gpio_5),
+	RTD1319D_GROUP(gpio_6),
+	RTD1319D_GROUP(gpio_7),
+	RTD1319D_GROUP(gpio_8),
+	RTD1319D_GROUP(gpio_9),
+	RTD1319D_GROUP(gpio_10),
+	RTD1319D_GROUP(gpio_11),
+	RTD1319D_GROUP(gpio_12),
+	RTD1319D_GROUP(gpio_13),
+	RTD1319D_GROUP(gpio_14),
+	RTD1319D_GROUP(gpio_15),
+	RTD1319D_GROUP(gpio_16),
+	RTD1319D_GROUP(gpio_17),
+	RTD1319D_GROUP(gpio_18),
+	RTD1319D_GROUP(gpio_19),
+	RTD1319D_GROUP(gpio_20),
+	RTD1319D_GROUP(gpio_21),
+	RTD1319D_GROUP(gpio_22),
+	RTD1319D_GROUP(gpio_23),
+	RTD1319D_GROUP(usb_cc2),
+	RTD1319D_GROUP(gpio_25),
+	RTD1319D_GROUP(gpio_26),
+	RTD1319D_GROUP(gpio_27),
+	RTD1319D_GROUP(gpio_28),
+	RTD1319D_GROUP(gpio_29),
+	RTD1319D_GROUP(gpio_30),
+	RTD1319D_GROUP(gpio_31),
+	RTD1319D_GROUP(gpio_32),
+	RTD1319D_GROUP(gpio_33),
+	RTD1319D_GROUP(gpio_34),
+	RTD1319D_GROUP(gpio_35),
+	RTD1319D_GROUP(hif_data),
+	RTD1319D_GROUP(hif_en),
+	RTD1319D_GROUP(hif_rdy),
+	RTD1319D_GROUP(hif_clk),
+	RTD1319D_GROUP(gpio_40),
+	RTD1319D_GROUP(gpio_41),
+	RTD1319D_GROUP(gpio_42),
+	RTD1319D_GROUP(gpio_43),
+	RTD1319D_GROUP(gpio_44),
+	RTD1319D_GROUP(gpio_45),
+	RTD1319D_GROUP(gpio_46),
+	RTD1319D_GROUP(gpio_47),
+	RTD1319D_GROUP(gpio_48),
+	RTD1319D_GROUP(gpio_49),
+	RTD1319D_GROUP(gpio_50),
+	RTD1319D_GROUP(usb_cc1),
+	RTD1319D_GROUP(gpio_52),
+	RTD1319D_GROUP(gpio_53),
+	RTD1319D_GROUP(ir_rx),
+	RTD1319D_GROUP(ur0_rx),
+	RTD1319D_GROUP(ur0_tx),
+	RTD1319D_GROUP(gpio_57),
+	RTD1319D_GROUP(gpio_58),
+	RTD1319D_GROUP(gpio_59),
+	RTD1319D_GROUP(gpio_60),
+	RTD1319D_GROUP(gpio_61),
+	RTD1319D_GROUP(gpio_62),
+	RTD1319D_GROUP(gpio_63),
+	RTD1319D_GROUP(gpio_64),
+	RTD1319D_GROUP(emmc_rst_n),
+	RTD1319D_GROUP(emmc_dd_sb),
+	RTD1319D_GROUP(emmc_clk),
+	RTD1319D_GROUP(emmc_cmd),
+	RTD1319D_GROUP(emmc_data_0),
+	RTD1319D_GROUP(emmc_data_1),
+	RTD1319D_GROUP(emmc_data_2),
+	RTD1319D_GROUP(emmc_data_3),
+	RTD1319D_GROUP(emmc_data_4),
+	RTD1319D_GROUP(emmc_data_5),
+	RTD1319D_GROUP(emmc_data_6),
+	RTD1319D_GROUP(emmc_data_7),
+	RTD1319D_GROUP(gpio_78),
+	RTD1319D_GROUP(gpio_79),
+	RTD1319D_GROUP(gpio_80),
+	RTD1319D_GROUP(gpio_81),
+	RTD1319D_GROUP(ur2_loc),
+	RTD1319D_GROUP(gspi_loc),
+	RTD1319D_GROUP(hi_width),
+	RTD1319D_GROUP(sf_en),
+	RTD1319D_GROUP(arm_trace_dbg_en),
+	RTD1319D_GROUP(ejtag_aucpu_loc),
+	RTD1319D_GROUP(ejtag_acpu_loc),
+	RTD1319D_GROUP(ejtag_vcpu_loc),
+	RTD1319D_GROUP(ejtag_scpu_loc),
+	RTD1319D_GROUP(dmic_loc),
+	RTD1319D_GROUP(ejtag_secpu_loc),
+	RTD1319D_GROUP(vtc_dmic_loc),
+	RTD1319D_GROUP(vtc_tdm_loc),
+	RTD1319D_GROUP(vtc_i2si_loc),
+	RTD1319D_GROUP(tdm_ai_loc),
+	RTD1319D_GROUP(ai_loc),
+	RTD1319D_GROUP(spdif_loc),
+	RTD1319D_GROUP(hif_en_loc),
+	RTD1319D_GROUP(sc0_loc),
+	RTD1319D_GROUP(sc1_loc),
+};
+
+static const char * const rtd1319d_gpio_groups[] = {
+	"gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4",
+	"gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9",
+	"gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14",
+	"gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19",
+	"gpio_20", "gpio_21", "gpio_22", "gpio_23", "usb_cc2",
+	"gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29",
+	"gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34",
+	"gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44",
+	"gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49",
+	"gpio_50", "usb_cc1", "gpio_52", "gpio_53", "ir_rx",
+	"ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59",
+	"gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_64",
+	"emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+	"emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+	"emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1319d_nf_groups[] = {
+	"emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0",
+	"emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4",
+	"emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"gpio_78", "gpio_79", "gpio_80", "gpio_81" };
+static const char * const rtd1319d_emmc_groups[] = {
+	"emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+	"emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+	"emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7" };
+static const char * const rtd1319d_tp0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_57", "gpio_58",
+	"gpio_59", "gpio_60", "gpio_61", "gpio_62", "gpio_63",
+	"gpio_64" };
+static const char * const rtd1319d_tp1_groups[] = {
+	"gpio_61", "gpio_62", "gpio_63", "gpio_64" };
+static const char * const rtd1319d_sc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_31" };
+static const char * const rtd1319d_sc0_data0_groups[] = { "gpio_20", "sc0_loc" };
+static const char * const rtd1319d_sc0_data1_groups[] = { "gpio_30", "sc0_loc" };
+static const char * const rtd1319d_sc0_data2_groups[] = { "gpio_47", "sc0_loc" };
+static const char * const rtd1319d_sc1_groups[] = {
+	"gpio_2", "gpio_3", "gpio_5" };
+static const char * const rtd1319d_sc1_data0_groups[] = { "gpio_52", "sc1_loc" };
+static const char * const rtd1319d_sc1_data1_groups[] = { "gpio_34", "sc1_loc" };
+static const char * const rtd1319d_sc1_data2_groups[] = { "gpio_35", "sc1_loc" };
+static const char * const rtd1319d_ao_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_61", "gpio_62",
+	"gpio_63", "gpio_64" };
+static const char * const rtd1319d_gspi_loc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" };
+static const char * const rtd1319d_gspi_loc1_groups[] = {
+	"gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" };
+static const char * const rtd1319d_uart0_groups[] = { "ur0_rx", "ur0_tx"};
+static const char * const rtd1319d_uart1_groups[] = {
+	"gpio_8", "gpio_9", "gpio_10", "gpio_11" };
+static const char * const rtd1319d_uart2_loc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" };
+static const char * const rtd1319d_uart2_loc1_groups[] = {
+	"gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" };
+static const char * const rtd1319d_i2c0_groups[] = { "gpio_12", "gpio_13" };
+static const char * const rtd1319d_i2c1_groups[] = { "gpio_16", "gpio_17" };
+static const char * const rtd1319d_i2c3_groups[] = { "gpio_26", "gpio_27" };
+static const char * const rtd1319d_i2c4_groups[] = { "gpio_34", "gpio_35" };
+static const char * const rtd1319d_i2c5_groups[] = { "gpio_29", "gpio_46" };
+static const char * const rtd1319d_pcie1_groups[] = { "gpio_22" };
+static const char * const rtd1319d_sdio_groups[] = {
+	"gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44",
+	"gpio_45" };
+static const char * const rtd1319d_etn_led_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1319d_etn_phy_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1319d_spi_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31" };
+static const char * const rtd1319d_pwm0_loc0_groups[] = { "gpio_26" };
+static const char * const rtd1319d_pwm0_loc1_groups[] = { "gpio_20" };
+static const char * const rtd1319d_pwm1_loc0_groups[] = { "gpio_27" };
+static const char * const rtd1319d_pwm1_loc1_groups[] = { "gpio_21" };
+
+static const char * const rtd1319d_pwm2_loc0_groups[] = { "gpio_28" };
+static const char * const rtd1319d_pwm2_loc1_groups[] = { "gpio_22" };
+static const char * const rtd1319d_pwm3_loc0_groups[] = { "gpio_47" };
+static const char * const rtd1319d_pwm3_loc1_groups[] = { "gpio_23" };
+static const char * const rtd1319d_qam_agc_if0_groups[] = { "gpio_21" };
+static const char * const rtd1319d_qam_agc_if1_groups[] = { "gpio_23" };
+static const char * const rtd1319d_spdif_optical_loc0_groups[] = { "gpio_21", "spdif_loc" };
+static const char * const rtd1319d_spdif_optical_loc1_groups[] = { "gpio_6", "spdif_loc" };
+static const char * const rtd1319d_usb_cc1_groups[] = { "usb_cc1" };
+static const char * const rtd1319d_usb_cc2_groups[] = { "usb_cc2" };
+static const char * const rtd1319d_vfd_groups[] = {
+	"gpio_26", "gpio_27", "gpio_28" };
+static const char * const rtd1319d_sd_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "gpio_35",
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1319d_dmic_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"gpio_62", "gpio_63", "gpio_64", "dmic_loc" };
+static const char * const rtd1319d_dmic_loc1_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "gpio_35",
+	"hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"dmic_loc" };
+static const char * const rtd1319d_ai_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"gpio_62", "gpio_63", "ai_loc" };
+static const char * const rtd1319d_ai_loc1_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "hif_data",
+	"hif_en", "hif_rdy", "hif_clk", "ai_loc" };
+static const char * const rtd1319d_tdm_ai_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59",
+	"gpio_60", "tdm_ai_loc" };
+static const char * const rtd1319d_tdm_ai_loc1_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk", "tdm_ai_loc" };
+static const char * const rtd1319d_hi_loc0_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1319d_hi_m_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1319d_vtc_i2so_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_64"};
+static const char * const rtd1319d_vtc_i2si_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"vtc_i2si_loc" };
+static const char * const rtd1319d_vtc_i2si_loc1_groups[] = {
+	"gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"vtc_i2si_loc" };
+static const char * const rtd1319d_vtc_dmic_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60",
+	"vtc_dmic_loc" };
+static const char * const rtd1319d_vtc_dmic_loc1_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"vtc_dmic_loc" };
+static const char * const rtd1319d_vtc_tdm_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60",
+	"vtc_tdm_loc" };
+static const char * const rtd1319d_vtc_tdm_loc1_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"vtc_tdm_loc" };
+static const char * const rtd1319d_dc_fan_groups[] = { "gpio_47" };
+static const char * const rtd1319d_pll_test_loc0_groups[] = { "gpio_52", "gpio_53" };
+static const char * const rtd1319d_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" };
+static const char * const rtd1319d_spdif_groups[] = { "gpio_50" };
+static const char * const rtd1319d_ir_rx_groups[] = { "ir_rx" };
+static const char * const rtd1319d_uart2_disable_groups[] = { "ur2_loc" };
+static const char * const rtd1319d_gspi_disable_groups[] = { "gspi_loc" };
+static const char * const rtd1319d_hi_width_disable_groups[] = { "hi_width" };
+static const char * const rtd1319d_hi_width_1bit_groups[] = { "hi_width" };
+static const char * const rtd1319d_sf_disable_groups[] = { "sf_en" };
+static const char * const rtd1319d_sf_enable_groups[] = { "sf_en" };
+static const char * const rtd1319d_scpu_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+	"ejtag_scpu_loc" };
+static const char * const rtd1319d_scpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_scpu_loc" };
+static const char * const rtd1319d_scpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_scpu_loc" };
+static const char * const rtd1319d_acpu_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+	"ejtag_acpu_loc" };
+static const char * const rtd1319d_acpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_acpu_loc" };
+static const char * const rtd1319d_acpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_acpu_loc" };
+static const char * const rtd1319d_vcpu_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+	"ejtag_vcpu_loc" };
+static const char * const rtd1319d_vcpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_vcpu_loc" };
+static const char * const rtd1319d_vcpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_vcpu_loc" };
+static const char * const rtd1319d_secpu_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+	"ejtag_secpu_loc" };
+static const char * const rtd1319d_secpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_secpu_loc" };
+static const char * const rtd1319d_secpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_secpu_loc" };
+static const char * const rtd1319d_aucpu_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+	"ejtag_aucpu_loc" };
+static const char * const rtd1319d_aucpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en", "hif_clk",
+	"ejtag_aucpu_loc" };
+static const char * const rtd1319d_aucpu_ejtag_loc2_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"ejtag_aucpu_loc" };
+static const char * const rtd1319d_iso_tristate_groups[] = {
+	"emmc_rst_n", "emmc_dd_sb", "emmc_clk", "emmc_cmd",
+	"emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3",
+	"emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"gpio_78", "gpio_79", "gpio_80", "gpio_81", "gpio_1",
+	"gpio_8", "gpio_9", "gpio_10", "gpio_11", "gpio_22",
+	"gpio_23", "usb_cc2", "gpio_25", "gpio_28", "gpio_29",
+	"gpio_30", "gpio_32", "gpio_33", "hif_data", "hif_en",
+	"hif_rdy", "hif_clk", "gpio_40", "gpio_41", "gpio_42",
+	"gpio_43", "gpio_44", "gpio_45", "gpio_46", "usb_cc1",
+	"ir_rx", "ur0_rx", "ur0_tx", "gpio_62", "gpio_63", "gpio_64" };
+static const char * const rtd1319d_dbg_out0_groups[] = {
+	"gpio_12", "gpio_13", "gpio_16", "gpio_17", "gpio_26", "gpio_27",
+	"gpio_34", "gpio_35", "gpio_48", "gpio_49", "gpio_57", "gpio_58",
+	"gpio_59", "gpio_60", "gpio_61" };
+static const char * const rtd1319d_dbg_out1_groups[] = {
+	"gpio_0", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6",
+	"gpio_7", "gpio_14", "gpio_15", "gpio_18", "gpio_19", "gpio_20",
+	"gpio_21", "gpio_31", "gpio_47", "gpio_50", "gpio_52", "gpio_53" };
+static const char * const rtd1319d_standby_dbg_groups[] = {
+	"gpio_2", "gpio_3", "ir_rx" };
+static const char * const rtd1319d_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1319d_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1319d_aucpu_ejtag_disable_groups[] = { "ejtag_aucpu_loc" };
+static const char * const rtd1319d_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" };
+static const char * const rtd1319d_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" };
+static const char * const rtd1319d_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" };
+static const char * const rtd1319d_secpu_ejtag_disable_groups[] = { "ejtag_secpu_loc" };
+static const char * const rtd1319d_vtc_dmic_loc_disable_groups[] = { "vtc_dmic_loc" };
+static const char * const rtd1319d_vtc_tdm_disable_groups[] = { "vtc_tdm_loc" };
+static const char * const rtd1319d_vtc_i2si_disable_groups[] = { "vtc_i2si_loc" };
+static const char * const rtd1319d_tdm_ai_disable_groups[] = { "tdm_ai_loc" };
+static const char * const rtd1319d_ai_disable_groups[] = { "ai_loc" };
+static const char * const rtd1319d_spdif_disable_groups[] = { "spdif_loc" };
+static const char * const rtd1319d_hif_disable_groups[] = { "hif_en_loc" };
+static const char * const rtd1319d_hif_enable_groups[] = { "hif_en_loc" };
+static const char * const rtd1319d_test_loop_groups[] = { "gpio_27" };
+static const char * const rtd1319d_pmic_pwrup_groups[] = { "gpio_78" };
+
+#define RTD1319D_FUNC(_name) \
+	{ \
+		.name = # _name, \
+		.groups = rtd1319d_ ## _name ## _groups, \
+		.num_groups = ARRAY_SIZE(rtd1319d_ ## _name ## _groups), \
+	}
+
+static const struct rtd_pin_func_desc rtd1319d_pin_functions[] = {
+	RTD1319D_FUNC(gpio),
+	RTD1319D_FUNC(nf),
+	RTD1319D_FUNC(emmc),
+	RTD1319D_FUNC(tp0),
+	RTD1319D_FUNC(tp1),
+	RTD1319D_FUNC(sc0),
+	RTD1319D_FUNC(sc0_data0),
+	RTD1319D_FUNC(sc0_data1),
+	RTD1319D_FUNC(sc0_data2),
+	RTD1319D_FUNC(sc1),
+	RTD1319D_FUNC(sc1_data0),
+	RTD1319D_FUNC(sc1_data1),
+	RTD1319D_FUNC(sc1_data2),
+	RTD1319D_FUNC(ao),
+	RTD1319D_FUNC(gspi_loc0),
+	RTD1319D_FUNC(gspi_loc1),
+	RTD1319D_FUNC(uart0),
+	RTD1319D_FUNC(uart1),
+	RTD1319D_FUNC(uart2_loc0),
+	RTD1319D_FUNC(uart2_loc1),
+	RTD1319D_FUNC(i2c0),
+	RTD1319D_FUNC(i2c1),
+	RTD1319D_FUNC(i2c3),
+	RTD1319D_FUNC(i2c4),
+	RTD1319D_FUNC(i2c5),
+	RTD1319D_FUNC(pcie1),
+	RTD1319D_FUNC(sdio),
+	RTD1319D_FUNC(etn_led),
+	RTD1319D_FUNC(etn_phy),
+	RTD1319D_FUNC(spi),
+	RTD1319D_FUNC(pwm0_loc0),
+	RTD1319D_FUNC(pwm0_loc1),
+	RTD1319D_FUNC(pwm1_loc0),
+	RTD1319D_FUNC(pwm1_loc1),
+	RTD1319D_FUNC(pwm2_loc0),
+	RTD1319D_FUNC(pwm2_loc1),
+	RTD1319D_FUNC(pwm3_loc0),
+	RTD1319D_FUNC(pwm3_loc1),
+	RTD1319D_FUNC(qam_agc_if0),
+	RTD1319D_FUNC(qam_agc_if1),
+	RTD1319D_FUNC(spdif_optical_loc0),
+	RTD1319D_FUNC(spdif_optical_loc1),
+	RTD1319D_FUNC(usb_cc1),
+	RTD1319D_FUNC(usb_cc2),
+	RTD1319D_FUNC(vfd),
+	RTD1319D_FUNC(sd),
+	RTD1319D_FUNC(dmic_loc0),
+	RTD1319D_FUNC(dmic_loc1),
+	RTD1319D_FUNC(ai_loc0),
+	RTD1319D_FUNC(ai_loc1),
+	RTD1319D_FUNC(tdm_ai_loc0),
+	RTD1319D_FUNC(tdm_ai_loc1),
+	RTD1319D_FUNC(hi_loc0),
+	RTD1319D_FUNC(hi_m),
+	RTD1319D_FUNC(vtc_i2so),
+	RTD1319D_FUNC(vtc_i2si_loc0),
+	RTD1319D_FUNC(vtc_i2si_loc1),
+	RTD1319D_FUNC(vtc_dmic_loc0),
+	RTD1319D_FUNC(vtc_dmic_loc1),
+	RTD1319D_FUNC(vtc_tdm_loc0),
+	RTD1319D_FUNC(vtc_tdm_loc1),
+	RTD1319D_FUNC(dc_fan),
+	RTD1319D_FUNC(pll_test_loc0),
+	RTD1319D_FUNC(pll_test_loc1),
+	RTD1319D_FUNC(ir_rx),
+	RTD1319D_FUNC(uart2_disable),
+	RTD1319D_FUNC(gspi_disable),
+	RTD1319D_FUNC(hi_width_disable),
+	RTD1319D_FUNC(hi_width_1bit),
+	RTD1319D_FUNC(sf_disable),
+	RTD1319D_FUNC(sf_enable),
+	RTD1319D_FUNC(scpu_ejtag_loc0),
+	RTD1319D_FUNC(scpu_ejtag_loc1),
+	RTD1319D_FUNC(scpu_ejtag_loc2),
+	RTD1319D_FUNC(acpu_ejtag_loc0),
+	RTD1319D_FUNC(acpu_ejtag_loc1),
+	RTD1319D_FUNC(acpu_ejtag_loc2),
+	RTD1319D_FUNC(vcpu_ejtag_loc0),
+	RTD1319D_FUNC(vcpu_ejtag_loc1),
+	RTD1319D_FUNC(vcpu_ejtag_loc2),
+	RTD1319D_FUNC(secpu_ejtag_loc0),
+	RTD1319D_FUNC(secpu_ejtag_loc1),
+	RTD1319D_FUNC(secpu_ejtag_loc2),
+	RTD1319D_FUNC(aucpu_ejtag_loc0),
+	RTD1319D_FUNC(aucpu_ejtag_loc1),
+	RTD1319D_FUNC(aucpu_ejtag_loc2),
+	RTD1319D_FUNC(iso_tristate),
+	RTD1319D_FUNC(dbg_out0),
+	RTD1319D_FUNC(dbg_out1),
+	RTD1319D_FUNC(standby_dbg),
+	RTD1319D_FUNC(spdif),
+	RTD1319D_FUNC(arm_trace_debug_disable),
+	RTD1319D_FUNC(arm_trace_debug_enable),
+	RTD1319D_FUNC(aucpu_ejtag_disable),
+	RTD1319D_FUNC(acpu_ejtag_disable),
+	RTD1319D_FUNC(vcpu_ejtag_disable),
+	RTD1319D_FUNC(scpu_ejtag_disable),
+	RTD1319D_FUNC(secpu_ejtag_disable),
+	RTD1319D_FUNC(vtc_dmic_loc_disable),
+	RTD1319D_FUNC(vtc_tdm_disable),
+	RTD1319D_FUNC(vtc_i2si_disable),
+	RTD1319D_FUNC(tdm_ai_disable),
+	RTD1319D_FUNC(ai_disable),
+	RTD1319D_FUNC(spdif_disable),
+	RTD1319D_FUNC(hif_disable),
+	RTD1319D_FUNC(hif_enable),
+	RTD1319D_FUNC(test_loop),
+	RTD1319D_FUNC(pmic_pwrup),
+};
+
+#undef RTD1319D_FUNC
+
+static const struct rtd_pin_desc rtd1319d_iso_muxes[] = {
+	[RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_78] = RTK_PIN_MUX(gpio_78, 0x4, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "pmic_pwrup"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_79] = RTK_PIN_MUX(gpio_79, 0x4, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_80] = RTK_PIN_MUX(gpio_80, 0x4, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_81] = RTK_PIN_MUX(gpio_81, 0x4, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1319D_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x8, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x8, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x8, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "standby_dbg"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "sc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "secpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2so"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x8, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "standby_dbg"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "sc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "secpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2so"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x8, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "secpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2so"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x8, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "sc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "secpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x8, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "spdif_optical_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "secpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x8, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+	[RTD1319D_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0xc, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0xc, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0xc, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0xc, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0xc, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "i2c0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0xc, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0xc, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "etn_led"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "etn_phy"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0xc, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "etn_led"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "etn_phy"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+	[RTD1319D_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x10, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x10, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "i2c1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x10, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x10, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "sc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x10, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pwm0_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc0_data0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x10, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "pwm1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "qam_agc_if0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "spdif_optical_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x10, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "pwm2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcie1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x10, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "pwm3_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "qam_agc_if1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1319D_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x14, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "usb_cc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0x14, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0x14, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "vfd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "pwm0_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "i2c3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0x14, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "vfd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "pwm1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "i2c3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "test_loop"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x14, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "vfd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "pwm2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x14, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "i2c5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x14, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "sc0_data1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x14, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "sc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+	[RTD1319D_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x18, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "secpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x18, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "secpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x18, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "i2c4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "sc1_data1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x18, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "i2c4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "sc1_data2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")),
+	[RTD1319D_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x18, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "secpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1319D_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x18, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 20), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 20), "vtc_dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "secpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1319D_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x18, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 24), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 24), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "vtc_dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1319D_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x18, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 28), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 28), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 28), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 28), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "vtc_dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "secpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1319D_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x1c, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x1c, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x1c, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x1c, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x1c, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x1c, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x1c, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "i2c5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x1c, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "dc_fan"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "pwm3_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "sc0_data2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "dbg_out1")),
+
+	[RTD1319D_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x20, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x20, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "pll_test_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x20, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "spdif"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out1")),
+	[RTD1319D_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x20, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "usb_cc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x20, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "pll_test_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc1_data0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out1")),
+	[RTD1319D_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x20, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "pll_test_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out1")),
+	[RTD1319D_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x20, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ir_rx"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "standby_dbg"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1319D_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x20, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1319D_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x24, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x24, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "secpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 4), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 4), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x24, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "secpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 8), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x24, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "secpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 12), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x24, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "secpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 16), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x24, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "tp1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "secpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "aucpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 20), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "dbg_out0")),
+	[RTD1319D_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x24, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "tp1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")),
+	[RTD1319D_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x24, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "tp1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")),
+
+	[RTD1319D_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x28, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "tp1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 0), "vtc_i2so"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")),
+
+	[RTD1319D_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")),
+	[RTD1319D_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")),
+	[RTD1319D_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")),
+	[RTD1319D_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")),
+	[RTD1319D_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")),
+	[RTD1319D_ISO_EJTAG_AUCPU_LOC] = RTK_PIN_MUX(ejtag_aucpu_loc, 0x120, GENMASK(16, 14),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "aucpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu_ejtag_loc2")),
+	[RTD1319D_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")),
+	[RTD1319D_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")),
+	[RTD1319D_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")),
+	[RTD1319D_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")),
+
+	[RTD1319D_ISO_EJTAG_SECPU_LOC] = RTK_PIN_MUX(ejtag_secpu_loc, 0x124, GENMASK(20, 18),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "secpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "secpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "secpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "secpu_ejtag_loc2")),
+
+	[RTD1319D_ISO_VTC_DMIC_LOC] = RTK_PIN_MUX(vtc_dmic_loc, 0x128, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "vtc_dmic_loc_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vtc_dmic_loc1")),
+	[RTD1319D_ISO_VTC_TDM_LOC] = RTK_PIN_MUX(vtc_tdm_loc, 0x128, GENMASK(3, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "vtc_tdm_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vtc_tdm_loc1")),
+	[RTD1319D_ISO_VTC_I2SI_LOC] = RTK_PIN_MUX(vtc_i2si_loc, 0x128, GENMASK(5, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "vtc_i2si_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vtc_i2si_loc1")),
+	[RTD1319D_ISO_TDM_AI_LOC] = RTK_PIN_MUX(tdm_ai_loc, 0x128, GENMASK(7, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "tdm_ai_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "tdm_ai_loc1")),
+	[RTD1319D_ISO_AI_LOC] = RTK_PIN_MUX(ai_loc, 0x128, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "ai_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ai_loc1")),
+	[RTD1319D_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(11, 10),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "spdif_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "spdif_optical_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "spdif_optical_loc1")),
+
+	[RTD1319D_ISO_HIF_EN_LOC] = RTK_PIN_MUX(hif_en_loc, 0x12c, GENMASK(2, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "hif_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "hif_enable")),
+	[RTD1319D_ISO_SC0_LOC] = RTK_PIN_MUX(sc0_loc, 0x188, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "sc0_data0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sc0_data1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "sc0_data2")),
+	[RTD1319D_ISO_SC1_LOC] = RTK_PIN_MUX(sc1_loc, 0x188, GENMASK(11, 10),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "sc1_data0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "sc1_data1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sc1_data2")),
+
+	[RTD1319D_ISO_TESTMODE] = {0},
+};
+
+static const struct rtd_pin_config_desc rtd1319d_iso_configs[] = {
+	[RTD1319D_ISO_SCAN_SWITCH] = RTK_PIN_CONFIG(scan_switch, 0x2c, 0, NA, NA, 0, 1, 2, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x2c, 3, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x2c, 8, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x2c, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x2c, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x2c, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x30, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x30, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x30, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_0] = RTK_PIN_CONFIG(gpio_0, 0x30, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x30, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_5] = RTK_PIN_CONFIG(gpio_5, 0x30, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x34, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x34, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x34, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_22] = RTK_PIN_CONFIG(gpio_22, 0x34, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x34, 20, NA, NA, 0, 1, 2, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x34, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x38, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x38, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x38, 10, NA, NA, 0, 1, 2, PADDRI_4_8),
+	[RTD1319D_ISO_WD_RSET] = RTK_PIN_CONFIG(wd_rset, 0x38, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x38, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_BOOT_SEL] = RTK_PIN_CONFIG(boot_sel, 0x38, 23, 0, 1, NA, 2, 3, PADDRI_4_8),
+	[RTD1319D_ISO_RESET_N] = RTK_PIN_CONFIG(reset_n, 0x38, 27, 0, 1, NA, 2, 3, PADDRI_4_8),
+	[RTD1319D_ISO_TESTMODE] = RTK_PIN_CONFIG(testmode, 0x3c, 0, 0, 1, NA, 2, 3, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x3c, 4, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x3c, 17, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_42] = RTK_PIN_CONFIG(gpio_42, 0x40, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_43] = RTK_PIN_CONFIG(gpio_43, 0x40, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_44] = RTK_PIN_CONFIG(gpio_44, 0x44, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x44, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x48, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x48, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x4c, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x4c, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x50, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x50, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x54, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x54, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x58, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x58, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x5c, 0, 0, 1, NA, 2, 13, NA),
+	[RTD1319D_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x5c, 14, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x60, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_78] = RTK_PIN_CONFIG(gpio_78, 0x60, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_79] = RTK_PIN_CONFIG(gpio_79, 0x64, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x64, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_2] = RTK_PIN_CONFIG(gpio_2, 0x64, 26, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_3] = RTK_PIN_CONFIG(gpio_3, 0x68, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_4] = RTK_PIN_CONFIG(gpio_4, 0x68, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x68, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x68, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x68, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x68, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x6c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x6c, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_63] = RTK_PIN_CONFIG(gpio_63, 0x6c, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x6c, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x6c, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x6c, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x70, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_21] = RTK_PIN_CONFIG(gpio_21, 0x70, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_23] = RTK_PIN_CONFIG(gpio_23, 0x70, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x70, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x74, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x74, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x78, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x78, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x7c, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x7c, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1319D_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x7c, 26, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x80, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x80, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x80, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x80, 16, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x80, 22, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x84, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x84, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x84, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x84, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x84, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x84, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x88, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_52] = RTK_PIN_CONFIG(gpio_52, 0x88, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1319D_ISO_GPIO_53] = RTK_PIN_CONFIG(gpio_53, 0x88, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+};
+
+static const struct rtd_pin_sconfig_desc rtd1319d_iso_sconfigs[] = {
+	RTK_PIN_SCONFIG(gpio_40, 0x3c, 7, 3, 10, 3, 13, 3),
+	RTK_PIN_SCONFIG(gpio_41, 0x3c, 20, 3, 23, 3, 26, 3),
+	RTK_PIN_SCONFIG(gpio_42, 0x40, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_43, 0x40, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_44, 0x44, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_45, 0x44, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_0, 0x48, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_1, 0x48, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_2, 0x4c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_3, 0x4c, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_4, 0x50, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_5, 0x50, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_6, 0x54, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_7, 0x54, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_dd_sb, 0x58, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_rst_n, 0x58, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_cmd, 0x5c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_clk, 0x5c, 17, 3, 20, 3, 23, 3),
+	RTK_PIN_SCONFIG(gpio_80, 0x60, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_78, 0x60, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_79, 0x64, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_81, 0x64, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(hif_en, 0x74, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(hif_data, 0x74, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_33, 0x78, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_32, 0x78, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(hif_clk, 0x7c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(hif_rdy, 0x7c, 16, 3, 19, 3, 22, 3),
+};
+
+static const struct rtd_pinctrl_desc rtd1319d_iso_pinctrl_desc = {
+	.pins = rtd1319d_iso_pins,
+	.num_pins = ARRAY_SIZE(rtd1319d_iso_pins),
+	.groups = rtd1319d_pin_groups,
+	.num_groups = ARRAY_SIZE(rtd1319d_pin_groups),
+	.functions = rtd1319d_pin_functions,
+	.num_functions = ARRAY_SIZE(rtd1319d_pin_functions),
+	.muxes = rtd1319d_iso_muxes,
+	.num_muxes = ARRAY_SIZE(rtd1319d_iso_muxes),
+	.configs = rtd1319d_iso_configs,
+	.num_configs = ARRAY_SIZE(rtd1319d_iso_configs),
+	.sconfigs = rtd1319d_iso_sconfigs,
+	.num_sconfigs = ARRAY_SIZE(rtd1319d_iso_sconfigs),
+};
+
+static int rtd1319d_pinctrl_probe(struct platform_device *pdev)
+{
+	return rtd_pinctrl_probe(pdev, &rtd1319d_iso_pinctrl_desc);
+}
+
+static const struct of_device_id rtd1319d_pinctrl_of_match[] = {
+	{ .compatible = "realtek,rtd1319d-pinctrl", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, rtd1319d_pinctrl_of_match);
+
+static struct platform_driver rtd1319d_pinctrl_driver = {
+	.driver = {
+		.name = "rtd1319d-pinctrl",
+		.of_match_table = rtd1319d_pinctrl_of_match,
+	},
+	.probe = rtd1319d_pinctrl_probe,
+};
+
+static int __init rtd1319d_pinctrl_init(void)
+{
+	return platform_driver_register(&rtd1319d_pinctrl_driver);
+}
+arch_initcall(rtd1319d_pinctrl_init);
+
+static void __exit rtd1319d_pinctrl_exit(void)
+{
+	platform_driver_unregister(&rtd1319d_pinctrl_driver);
+}
+module_exit(rtd1319d_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Realtek Semiconductor Corporation");
+MODULE_DESCRIPTION("Realtek DHC SoC RTD1319D pinctrl driver");
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1619b.c b/drivers/pinctrl/realtek/pinctrl-rtd1619b.c
new file mode 100644
index 000000000..b07e50d63
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1619b.c
@@ -0,0 +1,1601 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC 1619B pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-rtd.h"
+
+enum rtd16xxb_iso_pins {
+	RTD1619B_ISO_GPIO_0 = 0,
+	RTD1619B_ISO_GPIO_1,
+	RTD1619B_ISO_GPIO_2,
+	RTD1619B_ISO_GPIO_3,
+	RTD1619B_ISO_GPIO_4,
+	RTD1619B_ISO_GPIO_5,
+	RTD1619B_ISO_GPIO_6,
+	RTD1619B_ISO_GPIO_7,
+	RTD1619B_ISO_GPIO_8,
+	RTD1619B_ISO_GPIO_9,
+	RTD1619B_ISO_GPIO_10,
+	RTD1619B_ISO_GPIO_11,
+	RTD1619B_ISO_GPIO_12,
+	RTD1619B_ISO_GPIO_13,
+	RTD1619B_ISO_GPIO_14,
+	RTD1619B_ISO_GPIO_15,
+	RTD1619B_ISO_GPIO_16,
+	RTD1619B_ISO_GPIO_17,
+	RTD1619B_ISO_GPIO_18,
+	RTD1619B_ISO_GPIO_19,
+	RTD1619B_ISO_GPIO_20,
+	RTD1619B_ISO_GPIO_21,
+	RTD1619B_ISO_GPIO_22,
+	RTD1619B_ISO_GPIO_23,
+	RTD1619B_ISO_USB_CC2,
+	RTD1619B_ISO_GPIO_25,
+	RTD1619B_ISO_GPIO_26,
+	RTD1619B_ISO_GPIO_27,
+	RTD1619B_ISO_GPIO_28,
+	RTD1619B_ISO_GPIO_29,
+	RTD1619B_ISO_GPIO_30,
+	RTD1619B_ISO_GPIO_31,
+	RTD1619B_ISO_GPIO_32,
+	RTD1619B_ISO_GPIO_33,
+	RTD1619B_ISO_GPIO_34,
+	RTD1619B_ISO_GPIO_35,
+	RTD1619B_ISO_HIF_DATA,
+	RTD1619B_ISO_HIF_EN,
+	RTD1619B_ISO_HIF_RDY,
+	RTD1619B_ISO_HIF_CLK,
+	RTD1619B_ISO_GPIO_40,
+	RTD1619B_ISO_GPIO_41,
+	RTD1619B_ISO_GPIO_42,
+	RTD1619B_ISO_GPIO_43,
+	RTD1619B_ISO_GPIO_44,
+	RTD1619B_ISO_GPIO_45,
+	RTD1619B_ISO_GPIO_46,
+	RTD1619B_ISO_GPIO_47,
+	RTD1619B_ISO_GPIO_48,
+	RTD1619B_ISO_GPIO_49,
+	RTD1619B_ISO_GPIO_50,
+	RTD1619B_ISO_USB_CC1,
+	RTD1619B_ISO_GPIO_52,
+	RTD1619B_ISO_GPIO_53,
+	RTD1619B_ISO_IR_RX,
+	RTD1619B_ISO_UR0_RX,
+	RTD1619B_ISO_UR0_TX,
+	RTD1619B_ISO_GPIO_57,
+	RTD1619B_ISO_GPIO_58,
+	RTD1619B_ISO_GPIO_59,
+	RTD1619B_ISO_GPIO_60,
+	RTD1619B_ISO_GPIO_61,
+	RTD1619B_ISO_GPIO_62,
+	RTD1619B_ISO_GPIO_63,
+	RTD1619B_ISO_GPIO_64,
+	RTD1619B_ISO_GPIO_65,
+	RTD1619B_ISO_GPIO_66,
+	RTD1619B_ISO_GPIO_67,
+	RTD1619B_ISO_GPIO_68,
+	RTD1619B_ISO_GPIO_69,
+	RTD1619B_ISO_GPIO_70,
+	RTD1619B_ISO_GPIO_71,
+	RTD1619B_ISO_GPIO_72,
+	RTD1619B_ISO_GPIO_73,
+	RTD1619B_ISO_GPIO_74,
+	RTD1619B_ISO_GPIO_75,
+	RTD1619B_ISO_GPIO_76,
+	RTD1619B_ISO_EMMC_CMD,
+	RTD1619B_ISO_SPI_CE_N,
+	RTD1619B_ISO_SPI_SCK,
+	RTD1619B_ISO_SPI_SO,
+	RTD1619B_ISO_SPI_SI,
+	RTD1619B_ISO_EMMC_RST_N,
+	RTD1619B_ISO_EMMC_DD_SB,
+	RTD1619B_ISO_EMMC_CLK,
+	RTD1619B_ISO_EMMC_DATA_0,
+	RTD1619B_ISO_EMMC_DATA_1,
+	RTD1619B_ISO_EMMC_DATA_2,
+	RTD1619B_ISO_EMMC_DATA_3,
+	RTD1619B_ISO_EMMC_DATA_4,
+	RTD1619B_ISO_EMMC_DATA_5,
+	RTD1619B_ISO_EMMC_DATA_6,
+	RTD1619B_ISO_EMMC_DATA_7,
+	RTD1619B_ISO_UR2_LOC,
+	RTD1619B_ISO_GSPI_LOC,
+	RTD1619B_ISO_SDIO_LOC,
+	RTD1619B_ISO_HI_LOC,
+	RTD1619B_ISO_HI_WIDTH,
+	RTD1619B_ISO_SF_EN,
+	RTD1619B_ISO_ARM_TRACE_DBG_EN,
+	RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0,
+	RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0,
+	RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1,
+	RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1,
+	RTD1619B_ISO_EJTAG_ACPU_LOC,
+	RTD1619B_ISO_EJTAG_VCPU_LOC,
+	RTD1619B_ISO_EJTAG_SCPU_LOC,
+	RTD1619B_ISO_DMIC_LOC,
+	RTD1619B_ISO_ISO_GSPI_LOC,
+	RTD1619B_ISO_EJTAG_VE3_LOC,
+	RTD1619B_ISO_EJTAG_AUCPU0_LOC,
+	RTD1619B_ISO_EJTAG_AUCPU1_LOC,
+};
+
+static const struct pinctrl_pin_desc rtd1619b_iso_pins[] = {
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_0, "gpio_0"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_1, "gpio_1"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_2, "gpio_2"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_3, "gpio_3"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_4, "gpio_4"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_5, "gpio_5"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_6, "gpio_6"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_7, "gpio_7"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_8, "gpio_8"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_9, "gpio_9"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_10, "gpio_10"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_11, "gpio_11"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_12, "gpio_12"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_13, "gpio_13"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_14, "gpio_14"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_15, "gpio_15"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_16, "gpio_16"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_17, "gpio_17"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_18, "gpio_18"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_19, "gpio_19"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_20, "gpio_20"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_21, "gpio_21"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_22, "gpio_22"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_23, "gpio_23"),
+	PINCTRL_PIN(RTD1619B_ISO_USB_CC2, "usb_cc2"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_25, "gpio_25"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_26, "gpio_26"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_27, "gpio_27"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_28, "gpio_28"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_29, "gpio_29"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_30, "gpio_30"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_31, "gpio_31"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_32, "gpio_32"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_33, "gpio_33"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_34, "gpio_34"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_35, "gpio_35"),
+	PINCTRL_PIN(RTD1619B_ISO_HIF_DATA, "hif_data"),
+	PINCTRL_PIN(RTD1619B_ISO_HIF_EN, "hif_en"),
+	PINCTRL_PIN(RTD1619B_ISO_HIF_RDY, "hif_rdy"),
+	PINCTRL_PIN(RTD1619B_ISO_HIF_CLK, "hif_clk"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_40, "gpio_40"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_41, "gpio_41"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_42, "gpio_42"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_43, "gpio_43"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_44, "gpio_44"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_45, "gpio_45"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_46, "gpio_46"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_47, "gpio_47"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_48, "gpio_48"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_49, "gpio_49"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_50, "gpio_50"),
+	PINCTRL_PIN(RTD1619B_ISO_USB_CC1, "usb_cc1"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_52, "gpio_52"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_53, "gpio_53"),
+	PINCTRL_PIN(RTD1619B_ISO_IR_RX, "ir_rx"),
+	PINCTRL_PIN(RTD1619B_ISO_UR0_RX, "ur0_rx"),
+	PINCTRL_PIN(RTD1619B_ISO_UR0_TX, "ur0_tx"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_57, "gpio_57"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_58, "gpio_58"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_59, "gpio_59"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_60, "gpio_60"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_61, "gpio_61"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_62, "gpio_62"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_63, "gpio_63"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_64, "gpio_64"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_65, "gpio_65"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_66, "gpio_66"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_67, "gpio_67"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_68, "gpio_68"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_69, "gpio_69"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_70, "gpio_70"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_71, "gpio_71"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_72, "gpio_72"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_73, "gpio_73"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_74, "gpio_74"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_75, "gpio_75"),
+	PINCTRL_PIN(RTD1619B_ISO_GPIO_76, "gpio_76"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_CMD, "emmc_cmd"),
+	PINCTRL_PIN(RTD1619B_ISO_SPI_CE_N, "spi_ce_n"),
+	PINCTRL_PIN(RTD1619B_ISO_SPI_SCK, "spi_sck"),
+	PINCTRL_PIN(RTD1619B_ISO_SPI_SO, "spi_so"),
+	PINCTRL_PIN(RTD1619B_ISO_SPI_SI, "spi_si"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_RST_N, "emmc_rst_n"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DD_SB, "emmc_dd_sb"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_CLK, "emmc_clk"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_0, "emmc_data_0"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_1, "emmc_data_1"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_2, "emmc_data_2"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_3, "emmc_data_3"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_4, "emmc_data_4"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_5, "emmc_data_5"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_6, "emmc_data_6"),
+	PINCTRL_PIN(RTD1619B_ISO_EMMC_DATA_7, "emmc_data_7"),
+	PINCTRL_PIN(RTD1619B_ISO_UR2_LOC, "ur2_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_GSPI_LOC, "gspi_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_SDIO_LOC, "sdio_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_HI_LOC, "hi_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_HI_WIDTH, "hi_width"),
+	PINCTRL_PIN(RTD1619B_ISO_SF_EN, "sf_en"),
+	PINCTRL_PIN(RTD1619B_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"),
+	PINCTRL_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, "pwm_01_open_drain_en_loc0"),
+	PINCTRL_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, "pwm_23_open_drain_en_loc0"),
+	PINCTRL_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, "pwm_01_open_drain_en_loc1"),
+	PINCTRL_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, "pwm_23_open_drain_en_loc1"),
+	PINCTRL_PIN(RTD1619B_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_EJTAG_VCPU_LOC, "ejtag_vcpu_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_DMIC_LOC, "dmic_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_ISO_GSPI_LOC, "iso_gspi_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_EJTAG_VE3_LOC, "ejtag_ve3_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_EJTAG_AUCPU0_LOC, "ejtag_aucpu0_loc"),
+	PINCTRL_PIN(RTD1619B_ISO_EJTAG_AUCPU1_LOC, "ejtag_aucpu1_loc"),
+};
+
+#define DECLARE_RTD1619B_PIN(_pin, _name) \
+	static const unsigned int rtd1619b_## _name ##_pins[] = { _pin }
+
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_0, gpio_0);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_1, gpio_1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_2, gpio_2);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_3, gpio_3);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_4, gpio_4);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_5, gpio_5);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_6, gpio_6);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_7, gpio_7);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_8, gpio_8);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_9, gpio_9);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_10, gpio_10);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_11, gpio_11);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_12, gpio_12);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_13, gpio_13);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_14, gpio_14);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_15, gpio_15);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_16, gpio_16);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_17, gpio_17);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_18, gpio_18);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_19, gpio_19);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_20, gpio_20);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_21, gpio_21);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_22, gpio_22);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_23, gpio_23);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_USB_CC2, usb_cc2);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_25, gpio_25);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_26, gpio_26);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_27, gpio_27);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_28, gpio_28);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_29, gpio_29);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_30, gpio_30);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_31, gpio_31);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_32, gpio_32);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_33, gpio_33);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_34, gpio_34);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_35, gpio_35);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_DATA, hif_data);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_EN, hif_en);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_RDY, hif_rdy);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HIF_CLK, hif_clk);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_40, gpio_40);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_41, gpio_41);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_42, gpio_42);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_43, gpio_43);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_44, gpio_44);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_45, gpio_45);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_46, gpio_46);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_47, gpio_47);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_48, gpio_48);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_49, gpio_49);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_50, gpio_50);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_USB_CC1, usb_cc1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_52, gpio_52);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_53, gpio_53);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_IR_RX, ir_rx);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR0_RX, ur0_rx);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR0_TX, ur0_tx);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_57, gpio_57);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_58, gpio_58);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_59, gpio_59);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_60, gpio_60);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_61, gpio_61);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_62, gpio_62);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_63, gpio_63);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_64, gpio_64);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_65, gpio_65);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_66, gpio_66);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_67, gpio_67);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_68, gpio_68);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_69, gpio_69);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_70, gpio_70);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_71, gpio_71);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_72, gpio_72);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_73, gpio_73);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_74, gpio_74);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_75, gpio_75);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GPIO_76, gpio_76);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_CMD, emmc_cmd);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_CE_N, spi_ce_n);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SCK, spi_sck);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SO, spi_so);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SPI_SI, spi_si);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_RST_N, emmc_rst_n);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DD_SB, emmc_dd_sb);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_CLK, emmc_clk);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_0, emmc_data_0);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_1, emmc_data_1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_2, emmc_data_2);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_3, emmc_data_3);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_4, emmc_data_4);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_5, emmc_data_5);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_6, emmc_data_6);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EMMC_DATA_7, emmc_data_7);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_UR2_LOC, ur2_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_GSPI_LOC, gspi_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SDIO_LOC, sdio_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HI_LOC, hi_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_HI_WIDTH, hi_width);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_SF_EN, sf_en);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0, pwm_01_open_drain_en_loc0);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0, pwm_23_open_drain_en_loc0);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1, pwm_01_open_drain_en_loc1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1, pwm_23_open_drain_en_loc1);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_VCPU_LOC, ejtag_vcpu_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_DMIC_LOC, dmic_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_ISO_GSPI_LOC, iso_gspi_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_VE3_LOC, ejtag_ve3_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_AUCPU0_LOC, ejtag_aucpu0_loc);
+DECLARE_RTD1619B_PIN(RTD1619B_ISO_EJTAG_AUCPU1_LOC, ejtag_aucpu1_loc);
+
+#define RTD1619B_GROUP(_name) \
+	{ \
+		.name = # _name, \
+		.pins = rtd1619b_ ## _name ## _pins, \
+		.num_pins = ARRAY_SIZE(rtd1619b_ ## _name ## _pins), \
+	}
+
+static const struct rtd_pin_group_desc rtd1619b_pin_groups[] = {
+	RTD1619B_GROUP(gpio_0),
+	RTD1619B_GROUP(gpio_1),
+	RTD1619B_GROUP(gpio_2),
+	RTD1619B_GROUP(gpio_3),
+	RTD1619B_GROUP(gpio_4),
+	RTD1619B_GROUP(gpio_5),
+	RTD1619B_GROUP(gpio_6),
+	RTD1619B_GROUP(gpio_7),
+	RTD1619B_GROUP(gpio_8),
+	RTD1619B_GROUP(gpio_9),
+	RTD1619B_GROUP(gpio_10),
+	RTD1619B_GROUP(gpio_11),
+	RTD1619B_GROUP(gpio_12),
+	RTD1619B_GROUP(gpio_13),
+	RTD1619B_GROUP(gpio_14),
+	RTD1619B_GROUP(gpio_15),
+	RTD1619B_GROUP(gpio_16),
+	RTD1619B_GROUP(gpio_17),
+	RTD1619B_GROUP(gpio_18),
+	RTD1619B_GROUP(gpio_19),
+	RTD1619B_GROUP(gpio_20),
+	RTD1619B_GROUP(gpio_21),
+	RTD1619B_GROUP(gpio_22),
+	RTD1619B_GROUP(gpio_23),
+	RTD1619B_GROUP(usb_cc2),
+	RTD1619B_GROUP(gpio_25),
+	RTD1619B_GROUP(gpio_26),
+	RTD1619B_GROUP(gpio_27),
+	RTD1619B_GROUP(gpio_28),
+	RTD1619B_GROUP(gpio_29),
+	RTD1619B_GROUP(gpio_30),
+	RTD1619B_GROUP(gpio_31),
+	RTD1619B_GROUP(gpio_32),
+	RTD1619B_GROUP(gpio_33),
+	RTD1619B_GROUP(gpio_34),
+	RTD1619B_GROUP(gpio_35),
+	RTD1619B_GROUP(hif_data),
+	RTD1619B_GROUP(hif_en),
+	RTD1619B_GROUP(hif_rdy),
+	RTD1619B_GROUP(hif_clk),
+	RTD1619B_GROUP(gpio_40),
+	RTD1619B_GROUP(gpio_41),
+	RTD1619B_GROUP(gpio_42),
+	RTD1619B_GROUP(gpio_43),
+	RTD1619B_GROUP(gpio_44),
+	RTD1619B_GROUP(gpio_45),
+	RTD1619B_GROUP(gpio_46),
+	RTD1619B_GROUP(gpio_47),
+	RTD1619B_GROUP(gpio_48),
+	RTD1619B_GROUP(gpio_49),
+	RTD1619B_GROUP(gpio_50),
+	RTD1619B_GROUP(usb_cc1),
+	RTD1619B_GROUP(gpio_52),
+	RTD1619B_GROUP(gpio_53),
+	RTD1619B_GROUP(ir_rx),
+	RTD1619B_GROUP(ur0_rx),
+	RTD1619B_GROUP(ur0_tx),
+	RTD1619B_GROUP(gpio_57),
+	RTD1619B_GROUP(gpio_58),
+	RTD1619B_GROUP(gpio_59),
+	RTD1619B_GROUP(gpio_60),
+	RTD1619B_GROUP(gpio_61),
+	RTD1619B_GROUP(gpio_62),
+	RTD1619B_GROUP(gpio_63),
+	RTD1619B_GROUP(gpio_64),
+	RTD1619B_GROUP(gpio_65),
+	RTD1619B_GROUP(gpio_66),
+	RTD1619B_GROUP(gpio_67),
+	RTD1619B_GROUP(gpio_68),
+	RTD1619B_GROUP(gpio_69),
+	RTD1619B_GROUP(gpio_70),
+	RTD1619B_GROUP(gpio_71),
+	RTD1619B_GROUP(gpio_72),
+	RTD1619B_GROUP(gpio_73),
+	RTD1619B_GROUP(gpio_74),
+	RTD1619B_GROUP(gpio_75),
+	RTD1619B_GROUP(gpio_76),
+	RTD1619B_GROUP(emmc_cmd),
+	RTD1619B_GROUP(spi_ce_n),
+	RTD1619B_GROUP(spi_sck),
+	RTD1619B_GROUP(spi_so),
+	RTD1619B_GROUP(spi_si),
+	RTD1619B_GROUP(emmc_rst_n),
+	RTD1619B_GROUP(emmc_dd_sb),
+	RTD1619B_GROUP(emmc_clk),
+	RTD1619B_GROUP(emmc_data_0),
+	RTD1619B_GROUP(emmc_data_1),
+	RTD1619B_GROUP(emmc_data_2),
+	RTD1619B_GROUP(emmc_data_3),
+	RTD1619B_GROUP(emmc_data_4),
+	RTD1619B_GROUP(emmc_data_5),
+	RTD1619B_GROUP(emmc_data_6),
+	RTD1619B_GROUP(emmc_data_7),
+	RTD1619B_GROUP(ur2_loc),
+	RTD1619B_GROUP(gspi_loc),
+	RTD1619B_GROUP(sdio_loc),
+	RTD1619B_GROUP(hi_loc),
+	RTD1619B_GROUP(hi_width),
+	RTD1619B_GROUP(sf_en),
+	RTD1619B_GROUP(arm_trace_dbg_en),
+	RTD1619B_GROUP(pwm_01_open_drain_en_loc0),
+	RTD1619B_GROUP(pwm_23_open_drain_en_loc0),
+	RTD1619B_GROUP(pwm_01_open_drain_en_loc1),
+	RTD1619B_GROUP(pwm_23_open_drain_en_loc1),
+	RTD1619B_GROUP(ejtag_acpu_loc),
+	RTD1619B_GROUP(ejtag_vcpu_loc),
+	RTD1619B_GROUP(ejtag_scpu_loc),
+	RTD1619B_GROUP(dmic_loc),
+	RTD1619B_GROUP(iso_gspi_loc),
+	RTD1619B_GROUP(ejtag_ve3_loc),
+	RTD1619B_GROUP(ejtag_aucpu0_loc),
+	RTD1619B_GROUP(ejtag_aucpu1_loc),
+};
+
+static const char * const rtd1619b_gpio_groups[] = {
+	"gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4",
+	"gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9",
+	"gpio_10", "gpio_11", "gpio_12", "gpio_13", "gpio_14",
+	"gpio_15", "gpio_16", "gpio_17", "gpio_18", "gpio_19",
+	"gpio_20", "gpio_21", "gpio_22", "gpio_23", "usb_cc2",
+	"gpio_25", "gpio_26", "gpio_27", "gpio_28", "gpio_29",
+	"gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34",
+	"gpio_35", "hif_data", "hif_en", "hif_rdy", "hif_clk",
+	"gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44",
+	"gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49",
+	"gpio_50", "usb_cc1", "gpio_52", "gpio_53", "ir_rx",
+	"ur0_rx", "ur0_tx", "gpio_57", "gpio_58", "gpio_59",
+	"gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_64",
+	"gpio_65", "gpio_66", "gpio_67", "gpio_68", "gpio_69",
+	"gpio_70", "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+	"gpio_75", "gpio_76", "emmc_cmd", "spi_ce_n", "spi_sck",
+	"spi_so", "spi_si"};
+static const char * const rtd1619b_nf_groups[] = {
+	"emmc_rst_n", "emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1",
+	"emmc_data_2", "emmc_data_3", "emmc_data_4",
+	"emmc_data_5", "emmc_data_6", "emmc_data_7", "spi_ce_n",
+	"spi_sck", "spi_so", "spi_si" };
+static const char * const rtd1619b_nf_spi_groups[] = {
+	"emmc_data_0", "emmc_data_1",
+	"emmc_data_2", "emmc_data_3", "emmc_data_4",
+	"emmc_data_5" };
+static const char * const rtd1619b_spi_groups[] = {
+	"spi_ce_n", "spi_sck", "spi_so", "spi_si" };
+static const char * const rtd1619b_emmc_groups[] = {
+	"emmc_rst_n", "emmc_clk", "emmc_data_0", "emmc_data_1",
+	"emmc_data_2", "emmc_data_3", "emmc_data_4",
+	"emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"emmc_dd_sb", "emmc_cmd"};
+
+static const char * const rtd1619b_pmic_groups[] = { "spi_ce_n" };
+static const char * const rtd1619b_spdif_groups[] = { "gpio_50" };
+static const char * const rtd1619b_spdif_coaxial_groups[] = { "gpio_1" };
+static const char * const rtd1619b_spdif_optical_loc0_groups[] = { "gpio_6" };
+static const char * const rtd1619b_spdif_optical_loc1_groups[] = { "gpio_21" };
+
+static const char * const rtd1619b_emmc_spi_groups[] = {
+	"gpio_1", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6" };
+static const char * const rtd1619b_sc1_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4", "gpio_5" };
+static const char * const rtd1619b_uart0_groups[] = { "ur0_rx", "ur0_tx" };
+static const char * const rtd1619b_uart1_groups[] = {
+	"gpio_8", "gpio_9", "gpio_10", "gpio_11" };
+static const char * const rtd1619b_uart2_loc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31", "ur2_loc" };
+static const char * const rtd1619b_uart2_loc1_groups[] = {
+	"gpio_25", "gpio_26", "gpio_27", "gpio_28", "ur2_loc" };
+static const char * const rtd1619b_gspi_loc1_groups[] = {
+	"gpio_8", "gpio_9", "gpio_10", "gpio_11", "gspi_loc" };
+static const char * const rtd1619b_iso_gspi_loc1_groups[] = {
+	"gpio_8", "gpio_9", "gpio_10", "gpio_11", "iso_gspi_loc" };
+static const char * const rtd1619b_i2c0_groups[] = { "gpio_12", "gpio_13" };
+static const char * const rtd1619b_i2c1_groups[] = { "gpio_16", "gpio_17" };
+static const char * const rtd1619b_i2c3_groups[] = { "gpio_63", "gpio_64" };
+static const char * const rtd1619b_i2c4_groups[] = { "gpio_34", "gpio_35" };
+static const char * const rtd1619b_i2c5_groups[] = { "gpio_29", "gpio_46" };
+static const char * const rtd1619b_pwm0_groups[] = { "gpio_20", "gpio_26" };
+static const char * const rtd1619b_pwm1_groups[] = { "gpio_21", "gpio_27" };
+static const char * const rtd1619b_pwm2_groups[] = { "gpio_22", "gpio_28" };
+static const char * const rtd1619b_pwm3_groups[] = { "gpio_23", "gpio_47" };
+static const char * const rtd1619b_etn_led_groups[] = { "gpio_14", "gpio_15", "gpio_23" };
+static const char * const rtd1619b_etn_phy_groups[] = { "gpio_14", "gpio_15" };
+static const char * const rtd1619b_etn_clk_groups[] = { "gpio_14" };
+static const char * const rtd1619b_sc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31" };
+static const char * const rtd1619b_vfd_groups[] = {
+	"gpio_26", "gpio_27", "gpio_28" };
+
+static const char * const rtd1619b_gspi_loc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31", "gspi_loc" };
+static const char * const rtd1619b_iso_gspi_loc0_groups[] = {
+	"gpio_18", "gpio_19", "gpio_20", "gpio_31", "iso_gspi_loc" };
+static const char * const rtd1619b_pcie1_groups[] = { "gpio_25" };
+static const char * const rtd1619b_pcie2_groups[] = { "gpio_52" };
+static const char * const rtd1619b_sd_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "gpio_35", "hif_data",
+	"hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_sdio_loc0_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en",
+	"hif_rdy", "hif_clk", "sdio_loc" };
+static const char * const rtd1619b_sdio_loc1_groups[] = {
+	"gpio_40", "gpio_41", "gpio_42", "gpio_43", "gpio_44",
+	"gpio_45", "sdio_loc" };
+static const char * const rtd1619b_hi_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_hi_m_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_dc_fan_groups[] = { "gpio_47" };
+static const char * const rtd1619b_pll_test_loc0_groups[] = { "gpio_52", "gpio_53" };
+static const char * const rtd1619b_pll_test_loc1_groups[] = { "gpio_48", "gpio_49" };
+static const char * const rtd1619b_tdm_ai_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60" };
+static const char * const rtd1619b_tdm_ai_loc1_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_dmic_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"gpio_62", "gpio_63", "gpio_64", "dmic_loc"};
+static const char * const rtd1619b_dmic_loc1_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "gpio_35", "hif_data",
+	"hif_en", "hif_rdy", "hif_clk", "dmic_loc" };
+static const char * const rtd1619b_ai_loc0_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61",
+	"gpio_62", "gpio_63" };
+static const char * const rtd1619b_ai_loc1_groups[] = {
+	"gpio_32", "gpio_33", "gpio_34", "hif_data",
+	"hif_en", "hif_rdy", "hif_clk"};
+static const char * const rtd1619b_tp0_groups[] = {
+	"gpio_66", "gpio_67", "gpio_68", "gpio_69",
+	"gpio_70", "gpio_71", "gpio_72", "gpio_73", "gpio_74",
+	"gpio_75", "gpio_76" };
+static const char * const rtd1619b_tp1_groups[] = {
+	"gpio_69", "gpio_70", "gpio_71", "gpio_72" };
+static const char * const rtd1619b_ao_groups[] = {
+	"gpio_66", "gpio_67", "gpio_68", "gpio_69",
+	"gpio_70", "gpio_71", "gpio_72" };
+static const char * const rtd1619b_uart2_disable_groups[] = { "ur2_loc" };
+static const char * const rtd1619b_gspi_disable_groups[] = { "gspi_loc" };
+static const char * const rtd1619b_sdio_disable_groups[] = { "sdio_loc" };
+static const char * const rtd1619b_hi_loc_disable_groups[] = { "hi_loc" };
+static const char * const rtd1619b_hi_loc0_groups[] = { "hi_loc" };
+static const char * const rtd1619b_hi_width_disable_groups[] = { "hi_width" };
+static const char * const rtd1619b_hi_width_1bit_groups[] = { "hi_width" };
+
+static const char * const rtd1619b_vtc_i2si_loc0_groups[] = {
+	"gpio_32", "hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_vtc_tdm_loc0_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_vtc_dmic_loc0_groups[] = {
+	"hif_data", "hif_en", "hif_rdy", "hif_clk" };
+static const char * const rtd1619b_vtc_i2si_loc1_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60", "gpio_61" };
+static const char * const rtd1619b_vtc_tdm_loc1_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60" };
+static const char * const rtd1619b_vtc_dmic_loc1_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60" };
+static const char * const rtd1619b_vtc_i2so_groups[] = {
+	"gpio_66", "gpio_67", "gpio_68", "gpio_69" };
+static const char * const rtd1619b_ve3_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4",
+	"gpio_5", "gpio_6", "ejtag_ve3_loc" };
+static const char * const rtd1619b_aucpu0_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4",
+	"gpio_5", "gpio_6", "ejtag_aucpu0_loc" };
+static const char * const rtd1619b_aucpu1_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4",
+	"gpio_5", "gpio_6", "ejtag_aucpu1_loc" };
+static const char * const rtd1619b_ve3_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en",
+	"hif_clk", "ejtag_ve3_loc" };
+static const char * const rtd1619b_aucpu0_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en",
+	"hif_clk", "ejtag_aucpu0_loc" };
+static const char * const rtd1619b_aucpu1_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en",
+	"hif_clk", "ejtag_aucpu1_loc" };
+
+static const char * const rtd1619b_ve3_ejtag_loc2_groups[] = {
+	"gpio_71", "gpio_72", "gpio_73", "gpio_74",
+	"gpio_75", "gpio_76", "ejtag_ve3_loc" };
+static const char * const rtd1619b_aucpu0_ejtag_loc2_groups[] = {
+	"gpio_71", "gpio_72", "gpio_73", "gpio_74",
+	"gpio_75", "gpio_76", "ejtag_aucpu0_loc" };
+static const char * const rtd1619b_aucpu1_ejtag_loc2_groups[] = {
+	"gpio_71", "gpio_72", "gpio_73", "gpio_74",
+	"gpio_75", "gpio_76", "ejtag_aucpu1_loc" };
+
+static const char * const rtd1619b_scpu_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4",
+	"gpio_5", "gpio_6", "ejtag_scpu_loc" };
+static const char * const rtd1619b_acpu_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4",
+	"gpio_5", "gpio_6", "ejtag_acpu_loc" };
+static const char * const rtd1619b_vcpu_ejtag_loc0_groups[] = {
+	"gpio_2", "gpio_3", "gpio_4",
+	"gpio_5", "gpio_6", "ejtag_vcpu_loc" };
+static const char * const rtd1619b_scpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en",
+	"hif_clk", "ejtag_scpu_loc" };
+static const char * const rtd1619b_acpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data",  "hif_en",
+	"hif_clk", "ejtag_acpu_loc" };
+static const char * const rtd1619b_vcpu_ejtag_loc1_groups[] = {
+	"gpio_32", "gpio_33", "hif_data", "hif_en",
+	"hif_clk", "ejtag_vcpu_loc" };
+
+static const char * const rtd1619b_scpu_ejtag_loc2_groups[] = {
+	"gpio_71", "gpio_72", "gpio_73", "gpio_74",
+	"gpio_75", "gpio_76", "ejtag_scpu_loc" };
+static const char * const rtd1619b_acpu_ejtag_loc2_groups[] = {
+	"gpio_71", "gpio_72", "gpio_73", "gpio_74",
+	"gpio_75", "gpio_76", "ejtag_acpu_loc" };
+static const char * const rtd1619b_vcpu_ejtag_loc2_groups[] = {
+	"gpio_71", "gpio_72", "gpio_73", "gpio_74",
+	"gpio_75", "gpio_76", "ejtag_vcpu_loc"};
+static const char * const rtd1619b_ve3_ejtag_disable_groups[] = { "ejtag_ve3_loc" };
+static const char * const rtd1619b_aucpu0_ejtag_disable_groups[] = { "ejtag_aucpu0_loc" };
+static const char * const rtd1619b_aucpu1_ejtag_disable_groups[] = { "ejtag_aucpu1_loc" };
+
+static const char * const rtd1619b_acpu_ejtag_disable_groups[] = { "ejtag_acpu_loc" };
+static const char * const rtd1619b_vcpu_ejtag_disable_groups[] = { "ejtag_vcpu_loc" };
+static const char * const rtd1619b_scpu_ejtag_disable_groups[] = { "ejtag_scpu_loc" };
+static const char * const rtd1619b_sf_disable_groups[] = { "sf_en" };
+static const char * const rtd1619b_sf_enable_groups[] = { "sf_en" };
+static const char * const rtd1619b_iso_gspi_disable_groups[] = { "iso_gspi_loc" };
+static const char * const rtd1619b_arm_trace_debug_disable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1619b_arm_trace_debug_enable_groups[] = { "arm_trace_dbg_en" };
+static const char * const rtd1619b_pwm_normal_groups[] = {
+	"pwm_01_open_drain_en_loc0", "pwm_23_open_drain_en_loc0",
+	"pwm_01_open_drain_en_loc1", "pwm_23_open_drain_en_loc1" };
+static const char * const rtd1619b_pwm_open_drain_groups[] = {
+	"pwm_01_open_drain_en_loc0", "pwm_23_open_drain_en_loc0",
+	"pwm_01_open_drain_en_loc1", "pwm_23_open_drain_en_loc1" };
+static const char * const rtd1619b_standby_dbg_groups[] = {
+	"gpio_2", "gpio_3", "ir_rx" };
+
+static const char * const rtd1619b_usb_cc1_groups[] = { "usb_cc1" };
+static const char * const rtd1619b_usb_cc2_groups[] = { "usb_cc2" };
+static const char * const rtd1619b_ir_rx_groups[] = { "ir_rx" };
+static const char * const rtd1619b_test_loop_dis_groups[] = { "gpio_50" };
+
+#define RTD1619B_FUNC(_name) \
+	{ \
+		.name = # _name, \
+		.groups = rtd1619b_ ## _name ## _groups, \
+		.num_groups = ARRAY_SIZE(rtd1619b_ ## _name ## _groups), \
+	}
+
+static const struct rtd_pin_func_desc rtd1619b_pin_functions[] = {
+	RTD1619B_FUNC(gpio),
+	RTD1619B_FUNC(nf),
+	RTD1619B_FUNC(nf_spi),
+	RTD1619B_FUNC(spi),
+	RTD1619B_FUNC(pmic),
+	RTD1619B_FUNC(spdif),
+	RTD1619B_FUNC(spdif_coaxial),
+	RTD1619B_FUNC(spdif_optical_loc0),
+	RTD1619B_FUNC(spdif_optical_loc1),
+	RTD1619B_FUNC(emmc_spi),
+	RTD1619B_FUNC(emmc),
+	RTD1619B_FUNC(sc1),
+	RTD1619B_FUNC(uart0),
+	RTD1619B_FUNC(uart1),
+	RTD1619B_FUNC(uart2_loc0),
+	RTD1619B_FUNC(uart2_loc1),
+	RTD1619B_FUNC(gspi_loc1),
+	RTD1619B_FUNC(iso_gspi_loc1),
+	RTD1619B_FUNC(i2c0),
+	RTD1619B_FUNC(i2c1),
+	RTD1619B_FUNC(i2c3),
+	RTD1619B_FUNC(i2c4),
+	RTD1619B_FUNC(i2c5),
+	RTD1619B_FUNC(pwm0),
+	RTD1619B_FUNC(pwm1),
+	RTD1619B_FUNC(pwm2),
+	RTD1619B_FUNC(pwm3),
+	RTD1619B_FUNC(etn_led),
+	RTD1619B_FUNC(etn_phy),
+	RTD1619B_FUNC(etn_clk),
+	RTD1619B_FUNC(sc0),
+	RTD1619B_FUNC(vfd),
+	RTD1619B_FUNC(gspi_loc0),
+	RTD1619B_FUNC(iso_gspi_loc0),
+	RTD1619B_FUNC(pcie1),
+	RTD1619B_FUNC(pcie2),
+	RTD1619B_FUNC(sd),
+	RTD1619B_FUNC(sdio_loc0),
+	RTD1619B_FUNC(sdio_loc1),
+	RTD1619B_FUNC(hi),
+	RTD1619B_FUNC(hi_m),
+	RTD1619B_FUNC(dc_fan),
+	RTD1619B_FUNC(pll_test_loc0),
+	RTD1619B_FUNC(pll_test_loc1),
+	RTD1619B_FUNC(usb_cc1),
+	RTD1619B_FUNC(usb_cc2),
+	RTD1619B_FUNC(ir_rx),
+	RTD1619B_FUNC(tdm_ai_loc0),
+	RTD1619B_FUNC(tdm_ai_loc1),
+	RTD1619B_FUNC(dmic_loc0),
+	RTD1619B_FUNC(dmic_loc1),
+	RTD1619B_FUNC(ai_loc0),
+	RTD1619B_FUNC(ai_loc1),
+	RTD1619B_FUNC(tp0),
+	RTD1619B_FUNC(tp1),
+	RTD1619B_FUNC(ao),
+	RTD1619B_FUNC(uart2_disable),
+	RTD1619B_FUNC(gspi_disable),
+	RTD1619B_FUNC(sdio_disable),
+	RTD1619B_FUNC(hi_loc_disable),
+	RTD1619B_FUNC(hi_loc0),
+	RTD1619B_FUNC(hi_width_disable),
+	RTD1619B_FUNC(hi_width_1bit),
+	RTD1619B_FUNC(vtc_i2si_loc0),
+	RTD1619B_FUNC(vtc_tdm_loc0),
+	RTD1619B_FUNC(vtc_dmic_loc0),
+	RTD1619B_FUNC(vtc_i2si_loc1),
+	RTD1619B_FUNC(vtc_tdm_loc1),
+	RTD1619B_FUNC(vtc_dmic_loc1),
+	RTD1619B_FUNC(vtc_i2so),
+	RTD1619B_FUNC(ve3_ejtag_loc0),
+	RTD1619B_FUNC(aucpu0_ejtag_loc0),
+	RTD1619B_FUNC(aucpu1_ejtag_loc0),
+	RTD1619B_FUNC(ve3_ejtag_loc1),
+	RTD1619B_FUNC(aucpu0_ejtag_loc1),
+	RTD1619B_FUNC(aucpu1_ejtag_loc1),
+	RTD1619B_FUNC(ve3_ejtag_loc2),
+	RTD1619B_FUNC(aucpu0_ejtag_loc2),
+	RTD1619B_FUNC(aucpu1_ejtag_loc2),
+	RTD1619B_FUNC(scpu_ejtag_loc0),
+	RTD1619B_FUNC(acpu_ejtag_loc0),
+	RTD1619B_FUNC(vcpu_ejtag_loc0),
+	RTD1619B_FUNC(scpu_ejtag_loc1),
+	RTD1619B_FUNC(acpu_ejtag_loc1),
+	RTD1619B_FUNC(vcpu_ejtag_loc1),
+	RTD1619B_FUNC(scpu_ejtag_loc2),
+	RTD1619B_FUNC(acpu_ejtag_loc2),
+	RTD1619B_FUNC(vcpu_ejtag_loc2),
+	RTD1619B_FUNC(ve3_ejtag_disable),
+	RTD1619B_FUNC(aucpu0_ejtag_disable),
+	RTD1619B_FUNC(aucpu1_ejtag_disable),
+	RTD1619B_FUNC(acpu_ejtag_disable),
+	RTD1619B_FUNC(vcpu_ejtag_disable),
+	RTD1619B_FUNC(scpu_ejtag_disable),
+	RTD1619B_FUNC(iso_gspi_disable),
+	RTD1619B_FUNC(sf_disable),
+	RTD1619B_FUNC(sf_enable),
+	RTD1619B_FUNC(arm_trace_debug_disable),
+	RTD1619B_FUNC(arm_trace_debug_enable),
+	RTD1619B_FUNC(pwm_normal),
+	RTD1619B_FUNC(pwm_open_drain),
+	RTD1619B_FUNC(standby_dbg),
+	RTD1619B_FUNC(test_loop_dis),
+};
+
+#undef RTD1619B_FUNC
+
+static const struct rtd_pin_desc rtd1619b_iso_muxes[] = {
+	[RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc")),
+	[RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(3, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "emmc")),
+	[RTD1619B_ISO_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(5, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc")),
+	[RTD1619B_ISO_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(7, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "emmc")),
+	[RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "nf_spi")),
+	[RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(11, 10),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "nf_spi")),
+	[RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(13, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "nf_spi")),
+	[RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(15, 14),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "nf_spi")),
+	[RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x0, GENMASK(17, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "nf_spi")),
+	[RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x0, GENMASK(19, 18),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "nf_spi")),
+	[RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x0, GENMASK(21, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc")),
+	[RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x0, GENMASK(23, 22),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 22), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 22), "emmc")),
+	[RTD1619B_ISO_SPI_CE_N] = RTK_PIN_MUX(spi_ce_n, 0x0, GENMASK(25, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "pmic")),
+	[RTD1619B_ISO_SPI_SCK] = RTK_PIN_MUX(spi_sck, 0x0, GENMASK(27, 26),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "spi")),
+	[RTD1619B_ISO_SPI_SO] = RTK_PIN_MUX(spi_so, 0x0, GENMASK(29, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "spi")),
+	[RTD1619B_ISO_SPI_SI] = RTK_PIN_MUX(spi_si, 0x0, GENMASK(31, 30),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 30), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 30), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 30), "spi")),
+
+	[RTD1619B_ISO_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x4, GENMASK(0, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio")),
+	[RTD1619B_ISO_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x4, GENMASK(3, 1),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 1), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 1), "emmc_spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 1), "spdif_coaxial")),
+	[RTD1619B_ISO_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x4, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "standby_dbg"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "emmc_spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "sc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ve3_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 4), "aucpu1_ejtag_loc0")),
+	[RTD1619B_ISO_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x4, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "standby_dbg"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "emmc_spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "sc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 8), "ve3_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 8), "aucpu1_ejtag_loc0")),
+	[RTD1619B_ISO_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x4, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "emmc_spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "sc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ve3_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 12), "aucpu1_ejtag_loc0")),
+	[RTD1619B_ISO_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x4, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "emmc_spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "sc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ve3_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 16), "aucpu1_ejtag_loc0")),
+	[RTD1619B_ISO_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x4, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "emmc_spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "spdif_optical_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ve3_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 20), "aucpu1_ejtag_loc0")),
+	[RTD1619B_ISO_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x4, GENMASK(24, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio")),
+	[RTD1619B_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x4, GENMASK(27, 25),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 25), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 25), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 25), "iso_gspi_loc1")),
+	[RTD1619B_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x4, GENMASK(30, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "iso_gspi_loc1")),
+	[RTD1619B_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x8, GENMASK(2, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "iso_gspi_loc1")),
+	[RTD1619B_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x8, GENMASK(5, 3),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 3), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 3), "gspi_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 3), "iso_gspi_loc1")),
+
+	[RTD1619B_ISO_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x8, GENMASK(6, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "i2c0")),
+	[RTD1619B_ISO_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x8, GENMASK(7, 7),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 7), "i2c0")),
+	[RTD1619B_ISO_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x8, GENMASK(10, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "etn_led"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "etn_phy"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "etn_clk")),
+	[RTD1619B_ISO_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x8, GENMASK(12, 11),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "etn_led"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 11), "etn_phy")),
+	[RTD1619B_ISO_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x8, GENMASK(13, 13),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "i2c1")),
+	[RTD1619B_ISO_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x8, GENMASK(14, 14),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "i2c1")),
+	[RTD1619B_ISO_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x8, GENMASK(17, 15),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 15), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "sc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 15), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 15), "iso_gspi_loc0")),
+	[RTD1619B_ISO_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x8, GENMASK(20, 18),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "sc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 18), "iso_gspi_loc0")),
+	[RTD1619B_ISO_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x8, GENMASK(23, 21),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "pwm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 21), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "sc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 21), "iso_gspi_loc0")),
+	[RTD1619B_ISO_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x8, GENMASK(26, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "pwm1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "spdif_optical_loc1")),
+	[RTD1619B_ISO_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x8, GENMASK(28, 27),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "pwm2")),
+	[RTD1619B_ISO_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x8, GENMASK(30, 29),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 29), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 29), "etn_led"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "pwm3")),
+	[RTD1619B_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x8, GENMASK(31, 31),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 31), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 31), "usb_cc2")),
+	[RTD1619B_ISO_GPIO_25] = RTK_PIN_MUX(gpio_25, 0xc, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "pcie1")),
+	[RTD1619B_ISO_GPIO_26] = RTK_PIN_MUX(gpio_26, 0xc, GENMASK(3, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "vfd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 2), "pwm0")),
+	[RTD1619B_ISO_GPIO_27] = RTK_PIN_MUX(gpio_27, 0xc, GENMASK(5, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vfd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "pwm1")),
+
+	[RTD1619B_ISO_GPIO_28] = RTK_PIN_MUX(gpio_28, 0xc, GENMASK(7, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "uart2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "vfd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 6), "pwm2")),
+	[RTD1619B_ISO_GPIO_29] = RTK_PIN_MUX(gpio_29, 0xc, GENMASK(8, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "i2c5")),
+	[RTD1619B_ISO_GPIO_30] = RTK_PIN_MUX(gpio_30, 0xc, GENMASK(9, 9),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio")),
+	[RTD1619B_ISO_GPIO_31] = RTK_PIN_MUX(gpio_31, 0xc, GENMASK(12, 10),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 10), "iso_gspi_loc0")),
+	[RTD1619B_ISO_GPIO_32] = RTK_PIN_MUX(gpio_32, 0xc, GENMASK(17, 13),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 13), "sdio_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 13), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 13), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 13), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 13), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 13), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 13), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x14, 13), "ve3_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x15, 13), "aucpu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x16, 13), "aucpu1_ejtag_loc1")),
+	[RTD1619B_ISO_GPIO_33] = RTK_PIN_MUX(gpio_33, 0xc, GENMASK(22, 18),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "sdio_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 18), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 18), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 18), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x14, 18), "ve3_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x15, 18), "aucpu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x16, 18), "aucpu1_ejtag_loc1")),
+	[RTD1619B_ISO_GPIO_34] = RTK_PIN_MUX(gpio_34, 0xc, GENMASK(25, 23),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 23), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 23), "i2c4")),
+	[RTD1619B_ISO_GPIO_35] = RTK_PIN_MUX(gpio_35, 0xc, GENMASK(28, 26),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 26), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 26), "i2c4")),
+	[RTD1619B_ISO_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x10, GENMASK(4, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "sdio_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 0), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "hi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x12, 0), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 0), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x14, 0), "ve3_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x15, 0), "aucpu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x16, 0), "aucpu1_ejtag_loc1")),
+	[RTD1619B_ISO_HIF_EN] = RTK_PIN_MUX(hif_en, 0x10, GENMASK(9, 5),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 5), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 5), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 5), "sdio_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 5), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 5), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 5), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 5), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 5), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 5), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 5), "hi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 5), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 5), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x12, 5), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 5), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x14, 5), "ve3_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x15, 5), "aucpu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x16, 5), "aucpu1_ejtag_loc1")),
+	[RTD1619B_ISO_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x10, GENMASK(13, 10),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "sdio_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 10), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 10), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 10), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 10), "hi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 10), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 10), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x12, 10), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 10), "vtc_dmic_loc0")),
+
+	[RTD1619B_ISO_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x10, GENMASK(18, 14),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "sdio_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "dmic_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "tdm_ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 14), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 14), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 14), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 14), "ai_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 14), "hi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 14), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 14), "vtc_i2si_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x12, 14), "vtc_tdm_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 14), "vtc_dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x14, 14), "ve3_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x15, 14), "aucpu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x16, 14), "aucpu1_ejtag_loc1")),
+	[RTD1619B_ISO_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x10, GENMASK(20, 19),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "sdio_loc1")),
+	[RTD1619B_ISO_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x10, GENMASK(22, 21),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "sdio_loc1")),
+	[RTD1619B_ISO_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x10, GENMASK(24, 23),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "sdio_loc1")),
+	[RTD1619B_ISO_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x10, GENMASK(26, 25),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 25), "sdio_loc1")),
+	[RTD1619B_ISO_GPIO_44] = RTK_PIN_MUX(gpio_44, 0x10, GENMASK(28, 27),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "sdio_loc1")),
+	[RTD1619B_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x10, GENMASK(30, 29),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 29), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "sdio_loc1")),
+	[RTD1619B_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x10, GENMASK(31, 31),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 31), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 31), "i2c5")),
+	[RTD1619B_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x14, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "dc_fan"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "pwm3")),
+	[RTD1619B_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x14, GENMASK(2, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "pll_test_loc1")),
+	[RTD1619B_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x14, GENMASK(3, 3),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 3), "pll_test_loc1")),
+	[RTD1619B_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x14, GENMASK(5, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "spdif"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "test_loop_dis")),
+	[RTD1619B_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x14, GENMASK(6, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "usb_cc1")),
+	[RTD1619B_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x14, GENMASK(8, 7),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 7), "pll_test_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 7), "pcie2")),
+	[RTD1619B_ISO_GPIO_53] = RTK_PIN_MUX(gpio_53, 0x14, GENMASK(9, 9),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 9), "pll_test_loc0")),
+	[RTD1619B_ISO_IR_RX] = RTK_PIN_MUX(ir_rx, 0x14, GENMASK(11, 10),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 10), "ir_rx"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 10), "standby_dbg")),
+	[RTD1619B_ISO_UR0_RX] = RTK_PIN_MUX(ur0_rx, 0x14, GENMASK(12, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart0")),
+
+	[RTD1619B_ISO_UR0_TX] = RTK_PIN_MUX(ur0_tx, 0x14, GENMASK(13, 13),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "uart0")),
+	[RTD1619B_ISO_GPIO_57] = RTK_PIN_MUX(gpio_57, 0x14, GENMASK(17, 14),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 14), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 14), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x12, 14), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 14), "vtc_dmic_loc1")),
+	[RTD1619B_ISO_GPIO_58] = RTK_PIN_MUX(gpio_58, 0x14, GENMASK(21, 18),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 18), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x12, 18), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 18), "vtc_dmic_loc1")),
+	[RTD1619B_ISO_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x14, GENMASK(25, 22),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 22), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 22), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 22), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 22), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 22), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x12, 22), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 22), "vtc_dmic_loc1")),
+	[RTD1619B_ISO_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x14, GENMASK(29, 26),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 26), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "tdm_ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 26), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 26), "vtc_i2si_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x12, 26), "vtc_tdm_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 26), "vtc_dmic_loc1")),
+	[RTD1619B_ISO_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x18, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "vtc_i2si_loc1")),
+	[RTD1619B_ISO_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x18, GENMASK(5, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic_loc0")),
+	[RTD1619B_ISO_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x18, GENMASK(7, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "ai_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "i2c3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 6), "dmic_loc0")),
+	[RTD1619B_ISO_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x18, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "i2c3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic_loc0")),
+	[RTD1619B_ISO_GPIO_65] = RTK_PIN_MUX(gpio_65, 0x18, GENMASK(10, 10),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 10), "gpio")),
+	[RTD1619B_ISO_GPIO_66] = RTK_PIN_MUX(gpio_66, 0x18, GENMASK(14, 11),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 11), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 11), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 11), "vtc_i2so")),
+	[RTD1619B_ISO_GPIO_67] = RTK_PIN_MUX(gpio_67, 0x18, GENMASK(18, 15),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 15), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 15), "vtc_i2so")),
+	[RTD1619B_ISO_GPIO_68] = RTK_PIN_MUX(gpio_68, 0x18, GENMASK(22, 19),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 19), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 19), "vtc_i2so")),
+	[RTD1619B_ISO_GPIO_69] = RTK_PIN_MUX(gpio_69, 0x18, GENMASK(26, 23),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 23), "tp1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 23), "vtc_i2so")),
+
+	[RTD1619B_ISO_GPIO_70] = RTK_PIN_MUX(gpio_70, 0x18, GENMASK(29, 27),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 27), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 27), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 27), "tp1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 27), "ao")),
+	[RTD1619B_ISO_GPIO_71] = RTK_PIN_MUX(gpio_71, 0x1c, GENMASK(2, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "tp1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 0), "ve3_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "aucpu1_ejtag_loc2")),
+	[RTD1619B_ISO_GPIO_72] = RTK_PIN_MUX(gpio_72, 0x1c, GENMASK(6, 3),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 3), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 3), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 3), "tp1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 3), "ao"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 3), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 3), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 3), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 3), "ve3_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 3), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 3), "aucpu1_ejtag_loc2")),
+	[RTD1619B_ISO_GPIO_73] = RTK_PIN_MUX(gpio_73, 0x1c, GENMASK(10, 7),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 7), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 7), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 7), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 7), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 7), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 7), "ve3_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 7), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 7), "aucpu1_ejtag_loc2")),
+	[RTD1619B_ISO_GPIO_74] = RTK_PIN_MUX(gpio_74, 0x1c, GENMASK(14, 11),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 11), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 11), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 11), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 11), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 11), "ve3_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 11), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 11), "aucpu1_ejtag_loc2")),
+	[RTD1619B_ISO_GPIO_75] = RTK_PIN_MUX(gpio_75, 0x1c, GENMASK(18, 15),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 15), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 15), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 15), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 15), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 15), "ve3_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 15), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 15), "aucpu1_ejtag_loc2")),
+	[RTD1619B_ISO_GPIO_76] = RTK_PIN_MUX(gpio_76, 0x1c, GENMASK(22, 19),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 19), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 19), "tp0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 19), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 19), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 19), "vcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 19), "ve3_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 19), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 19), "aucpu1_ejtag_loc2")),
+
+	[RTD1619B_ISO_UR2_LOC] = RTK_PIN_MUX(ur2_loc, 0x120, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "uart2_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart2_loc1")),
+	[RTD1619B_ISO_GSPI_LOC] = RTK_PIN_MUX(gspi_loc, 0x120, GENMASK(3, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 2), "gspi_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "gspi_loc1")),
+	[RTD1619B_ISO_SDIO_LOC] = RTK_PIN_MUX(sdio_loc, 0x120, GENMASK(5, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "sdio_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sdio_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "sdio_loc1")),
+	[RTD1619B_ISO_HI_LOC] = RTK_PIN_MUX(hi_loc, 0x120, GENMASK(7, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 6), "hi_loc_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "hi_loc0")),
+	[RTD1619B_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")),
+	[RTD1619B_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")),
+	[RTD1619B_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(12, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")),
+	[RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC0] = RTK_PIN_MUX(pwm_01_open_drain_en_loc0, 0x120,
+		GENMASK(13, 13),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "pwm_normal"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "pwm_open_drain")),
+	[RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC0] = RTK_PIN_MUX(pwm_23_open_drain_en_loc0, 0x120,
+		GENMASK(14, 14),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 14), "pwm_normal"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "pwm_open_drain")),
+	[RTD1619B_ISO_PWM_01_OPEN_DRAIN_EN_LOC1] = RTK_PIN_MUX(pwm_01_open_drain_en_loc1, 0x120,
+		GENMASK(15, 15),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 15), "pwm_normal"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 15), "pwm_open_drain")),
+	[RTD1619B_ISO_PWM_23_OPEN_DRAIN_EN_LOC1] = RTK_PIN_MUX(pwm_23_open_drain_en_loc1, 0x120,
+		GENMASK(16, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "pwm_normal"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "pwm_open_drain")),
+	[RTD1619B_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(19, 17),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "acpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "acpu_ejtag_loc2")),
+	[RTD1619B_ISO_EJTAG_VCPU_LOC] = RTK_PIN_MUX(ejtag_vcpu_loc, 0x120, GENMASK(22, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "vcpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "vcpu_ejtag_loc2")),
+	[RTD1619B_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 23), "scpu_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")),
+	[RTD1619B_ISO_DMIC_LOC] = RTK_PIN_MUX(dmic_loc, 0x120, GENMASK(27, 26),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "dmic_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "dmic_loc1")),
+	[RTD1619B_ISO_ISO_GSPI_LOC] = RTK_PIN_MUX(iso_gspi_loc, 0x120, GENMASK(29, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "iso_gspi_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "iso_gspi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "iso_gspi_loc1")),
+	[RTD1619B_ISO_EJTAG_VE3_LOC] = RTK_PIN_MUX(ejtag_ve3_loc, 0x124, GENMASK(20, 18),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "ve3_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "ve3_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "ve3_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 18), "ve3_ejtag_loc2")),
+	[RTD1619B_ISO_EJTAG_AUCPU1_LOC] = RTK_PIN_MUX(ejtag_aucpu1_loc, 0x124, GENMASK(23, 21),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "aucpu1_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "aucpu1_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "aucpu1_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "aucpu1_ejtag_loc2")),
+	[RTD1619B_ISO_EJTAG_AUCPU0_LOC] = RTK_PIN_MUX(ejtag_aucpu0_loc, 0x124, GENMASK(26, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "aucpu0_ejtag_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "aucpu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "aucpu0_ejtag_loc2")),
+};
+
+static const struct rtd_pin_config_desc rtd1619b_iso_configs[] = {
+	[RTD1619B_ISO_GPIO_17] = RTK_PIN_CONFIG(gpio_17, 0x20, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_19] = RTK_PIN_CONFIG(gpio_19, 0x20, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x20, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_21] = RTK_PIN_CONFIG(gpio_21, 0x20, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x20, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x20, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_68] = RTK_PIN_CONFIG(gpio_68, 0x24, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_69] = RTK_PIN_CONFIG(gpio_69, 0x24, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_70] = RTK_PIN_CONFIG(gpio_70, 0x24, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_71] = RTK_PIN_CONFIG(gpio_71, 0x24, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_72] = RTK_PIN_CONFIG(gpio_72, 0x24, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_73] = RTK_PIN_CONFIG(gpio_73, 0x24, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_74] = RTK_PIN_CONFIG(gpio_74, 0x28, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_75] = RTK_PIN_CONFIG(gpio_75, 0x28, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_76] = RTK_PIN_CONFIG(gpio_76, 0x28, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_SPI_SI] = RTK_PIN_CONFIG(spi_si, 0x28, 15, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_SPI_SCK] = RTK_PIN_CONFIG(spi_sck, 0x2c, 0, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_SPI_CE_N] = RTK_PIN_CONFIG(spi_ce_n, 0x2c, 13, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_SPI_SO] = RTK_PIN_CONFIG(spi_so, 0x2c, 26, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x30, 7, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x34, 0, 0, 1, 3, 2, 13, NA),
+	[RTD1619B_ISO_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x34, 14, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x34, 27, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x38, 8, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x3c, 0, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x3c, 13, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x3c, 26, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x40, 7, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x44, 0, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x44, 13, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x44, 26, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_USB_CC1] = RTK_PIN_CONFIG(usb_cc1, 0x48, 7, NA, NA, 0, 1, 9, PADDRI_4_8),
+	[RTD1619B_ISO_USB_CC2] = RTK_PIN_CONFIG(usb_cc2, 0x48, 10, NA, NA, 0, 1, 9, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_26] = RTK_PIN_CONFIG(gpio_26, 0x48, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_27] = RTK_PIN_CONFIG(gpio_27, 0x48, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_28] = RTK_PIN_CONFIG(gpio_28, 0x48, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_29] = RTK_PIN_CONFIG(gpio_29, 0x4c, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x4c, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x4c, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x4c, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_53] = RTK_PIN_CONFIG(gpio_53, 0x4c, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_65] = RTK_PIN_CONFIG(gpio_65, 0x4c, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x50, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x50, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_23] = RTK_PIN_CONFIG(gpio_23, 0x50, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_IR_RX] = RTK_PIN_CONFIG(ir_rx, 0x50, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_57] = RTK_PIN_CONFIG(gpio_57, 0x50, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_58] = RTK_PIN_CONFIG(gpio_58, 0x50, 30, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_59] = RTK_PIN_CONFIG(gpio_59, 0x54, 3, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_60] = RTK_PIN_CONFIG(gpio_60, 0x54, 8, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_61] = RTK_PIN_CONFIG(gpio_61, 0x54, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_62] = RTK_PIN_CONFIG(gpio_62, 0x54, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_63] = RTK_PIN_CONFIG(gpio_63, 0x54, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x58, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_UR0_TX] = RTK_PIN_CONFIG(ur0_tx, 0x58, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_UR0_RX] = RTK_PIN_CONFIG(ur0_rx, 0x58, 13, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_12] = RTK_PIN_CONFIG(gpio_12, 0x58, 18, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_13] = RTK_PIN_CONFIG(gpio_13, 0x58, 23, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_30] = RTK_PIN_CONFIG(gpio_30, 0x58, 28, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_7] = RTK_PIN_CONFIG(gpio_7, 0x5c, 1, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_16] = RTK_PIN_CONFIG(gpio_16, 0x5c, 6, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_18] = RTK_PIN_CONFIG(gpio_18, 0x5c, 11, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_20] = RTK_PIN_CONFIG(gpio_20, 0x5c, 16, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_22] = RTK_PIN_CONFIG(gpio_22, 0x5c, 21, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_31] = RTK_PIN_CONFIG(gpio_31, 0x5c, 26, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x60, 12, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_25] = RTK_PIN_CONFIG(gpio_25, 0x60, 17, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_6] = RTK_PIN_CONFIG(gpio_6, 0x60, 22, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_5] = RTK_PIN_CONFIG(gpio_5, 0x60, 27, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_4] = RTK_PIN_CONFIG(gpio_4, 0x64, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_3] = RTK_PIN_CONFIG(gpio_3, 0x64, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_2] = RTK_PIN_CONFIG(gpio_2, 0x64, 10, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_1] = RTK_PIN_CONFIG(gpio_1, 0x64, 15, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_0] = RTK_PIN_CONFIG(gpio_0, 0x64, 20, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_52] = RTK_PIN_CONFIG(gpio_52, 0x64, 25, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_35] = RTK_PIN_CONFIG(gpio_35, 0x68, 0, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_34] = RTK_PIN_CONFIG(gpio_34, 0x68, 5, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x68, 10, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x6c, 0, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_GPIO_42] = RTK_PIN_CONFIG(gpio_42, 0x6c, 13, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_GPIO_43] = RTK_PIN_CONFIG(gpio_43, 0x70, 0, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_GPIO_44] = RTK_PIN_CONFIG(gpio_44, 0x70, 13, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x70, 26, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_GPIO_8] = RTK_PIN_CONFIG(gpio_8, 0x74, 7, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_9] = RTK_PIN_CONFIG(gpio_9, 0x74, 12, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_10] = RTK_PIN_CONFIG(gpio_10, 0x74, 17, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_GPIO_11] = RTK_PIN_CONFIG(gpio_11, 0x74, 22, 1, 2, 0, 3, 4, PADDRI_4_8),
+	[RTD1619B_ISO_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x78, 0, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x78, 13, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_GPIO_32] = RTK_PIN_CONFIG(gpio_32, 0x78, 26, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_GPIO_33] = RTK_PIN_CONFIG(gpio_33, 0x7c, 7, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x80, 0, 0, 1, 3, 2, 12, NA),
+	[RTD1619B_ISO_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x80, 13, 0, 1, 3, 2, 12, NA),
+};
+
+static const struct rtd_pin_sconfig_desc rtd1619b_iso_sconfigs[] = {
+	RTK_PIN_SCONFIG(spi_si, 0x28, 18, 3, 21, 3, 24, 3),
+	RTK_PIN_SCONFIG(spi_sck, 0x2c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(spi_ce_n, 0x2c, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(spi_so, 0x2c, 29, 3, 32, 3, 35, 3),
+	RTK_PIN_SCONFIG(emmc_clk, 0x30, 10, 3, 13, 3, 16, 3),
+	RTK_PIN_SCONFIG(emmc_cmd, 0x34, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_rst_n, 0x34, 17, 3, 20, 3, 23, 3),
+	RTK_PIN_SCONFIG(emmc_dd_sb, 0x34, 30, 3, 33, 3, 36, 3),
+	RTK_PIN_SCONFIG(emmc_data_5, 0x38, 11, 3, 14, 3, 17, 3),
+	RTK_PIN_SCONFIG(emmc_data_3, 0x3c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_4, 0x3c, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_0, 0x3c, 29, 3, 32, 3, 35, 3),
+	RTK_PIN_SCONFIG(emmc_data_1, 0x40, 10, 3, 13, 3, 16, 3),
+	RTK_PIN_SCONFIG(emmc_data_2, 0x44, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_7, 0x44, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_6, 0x44, 29, 3, 32, 3, 35, 3),
+	RTK_PIN_SCONFIG(gpio_40, 0x68, 13, 3, 16, 3, 19, 3),
+	RTK_PIN_SCONFIG(gpio_41, 0x6c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_42, 0x6c, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_43, 0x70, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_44, 0x70, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_45, 0x70, 29, 3, 32, 3, 35, 3),
+	RTK_PIN_SCONFIG(hif_rdy, 0x78, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(hif_clk, 0x78, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_32, 0x78, 29, 3, 32, 3, 35, 3),
+	RTK_PIN_SCONFIG(gpio_33, 0x7c, 10, 3, 13, 3, 16, 3),
+	RTK_PIN_SCONFIG(hif_data, 0x80, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(hif_en, 0x80, 16, 3, 19, 3, 22, 3),
+};
+
+static const struct rtd_pinctrl_desc rtd1619b_iso_pinctrl_desc = {
+	.pins = rtd1619b_iso_pins,
+	.num_pins = ARRAY_SIZE(rtd1619b_iso_pins),
+	.groups = rtd1619b_pin_groups,
+	.num_groups = ARRAY_SIZE(rtd1619b_pin_groups),
+	.functions = rtd1619b_pin_functions,
+	.num_functions = ARRAY_SIZE(rtd1619b_pin_functions),
+	.muxes = rtd1619b_iso_muxes,
+	.num_muxes = ARRAY_SIZE(rtd1619b_iso_muxes),
+	.configs = rtd1619b_iso_configs,
+	.num_configs = ARRAY_SIZE(rtd1619b_iso_configs),
+	.sconfigs = rtd1619b_iso_sconfigs,
+	.num_sconfigs = ARRAY_SIZE(rtd1619b_iso_sconfigs),
+};
+
+static int rtd1619b_pinctrl_probe(struct platform_device *pdev)
+{
+	return rtd_pinctrl_probe(pdev, &rtd1619b_iso_pinctrl_desc);
+}
+
+static const struct of_device_id rtd1619b_pinctrl_of_match[] = {
+	{ .compatible = "realtek,rtd1619b-pinctrl", },
+	{},
+};
+
+static struct platform_driver rtd1619b_pinctrl_driver = {
+	.driver = {
+		.name = "rtd1619b-pinctrl",
+		.of_match_table = rtd1619b_pinctrl_of_match,
+	},
+	.probe = rtd1619b_pinctrl_probe,
+};
+
+static int __init rtd1619b_pinctrl_init(void)
+{
+	return platform_driver_register(&rtd1619b_pinctrl_driver);
+}
+arch_initcall(rtd1619b_pinctrl_init);
+
+static void __exit rtd1619b_pinctrl_exit(void)
+{
+	platform_driver_unregister(&rtd1619b_pinctrl_driver);
+}
+module_exit(rtd1619b_pinctrl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Realtek Semiconductor Corporation");
+MODULE_DESCRIPTION("Realtek DHC SoC RTD1619B pinctrl driver");
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1625.c b/drivers/pinctrl/realtek/pinctrl-rtd1625.c
new file mode 100644
index 000000000..88f2be37f
--- /dev/null
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1625.c
@@ -0,0 +1,3138 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Realtek DHC 1625 pin controller driver
+ *
+ * Copyright (c) 2023 Realtek Semiconductor Corp.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-rtd.h"
+
+enum rtd1625_iso_pins_enum {
+	RTD1625_ISO_GPIO_8 = 0,
+	RTD1625_ISO_GPIO_9,
+	RTD1625_ISO_GPIO_10,
+	RTD1625_ISO_GPIO_11,
+	RTD1625_ISO_USB_CC1,
+	RTD1625_ISO_USB_CC2,
+	RTD1625_ISO_GPIO_45,
+	RTD1625_ISO_GPIO_46,
+	RTD1625_ISO_GPIO_47,
+	RTD1625_ISO_GPIO_48,
+	RTD1625_ISO_GPIO_49,
+	RTD1625_ISO_GPIO_50,
+	RTD1625_ISO_GPIO_52,
+	RTD1625_ISO_GPIO_94,
+	RTD1625_ISO_GPIO_95,
+	RTD1625_ISO_GPIO_96,
+	RTD1625_ISO_GPIO_97,
+	RTD1625_ISO_GPIO_98,
+	RTD1625_ISO_GPIO_99,
+	RTD1625_ISO_GPIO_100,
+	RTD1625_ISO_GPIO_101,
+	RTD1625_ISO_GPIO_102,
+	RTD1625_ISO_GPIO_103,
+	RTD1625_ISO_GPIO_104,
+	RTD1625_ISO_GPIO_105,
+	RTD1625_ISO_GPIO_106,
+	RTD1625_ISO_GPIO_107,
+	RTD1625_ISO_GPIO_108,
+	RTD1625_ISO_GPIO_109,
+	RTD1625_ISO_GPIO_110,
+	RTD1625_ISO_GPIO_111,
+	RTD1625_ISO_GPIO_112,
+	RTD1625_ISO_GPIO_128,
+	RTD1625_ISO_GPIO_129,
+	RTD1625_ISO_GPIO_130,
+	RTD1625_ISO_GPIO_131,
+	RTD1625_ISO_GPIO_145,
+	RTD1625_ISO_GPIO_146,
+	RTD1625_ISO_GPIO_147,
+	RTD1625_ISO_GPIO_148,
+	RTD1625_ISO_GPIO_149,
+	RTD1625_ISO_GPIO_150,
+	RTD1625_ISO_GPIO_151,
+	RTD1625_ISO_GPIO_152,
+	RTD1625_ISO_GPIO_153,
+	RTD1625_ISO_GPIO_154,
+	RTD1625_ISO_GPIO_155,
+	RTD1625_ISO_GPIO_156,
+	RTD1625_ISO_GPIO_157,
+	RTD1625_ISO_GPIO_158,
+	RTD1625_ISO_GPIO_159,
+	RTD1625_ISO_GPIO_160,
+	RTD1625_ISO_GPIO_161,
+	RTD1625_ISO_GPIO_162,
+	RTD1625_ISO_GPIO_163,
+	RTD1625_ISO_HI_WIDTH,
+	RTD1625_ISO_SF_EN,
+	RTD1625_ISO_ARM_TRACE_DBG_EN,
+	RTD1625_ISO_EJTAG_AUCPU0_LOC,
+	RTD1625_ISO_EJTAG_AUCPU1_LOC,
+	RTD1625_ISO_EJTAG_VE2_LOC,
+	RTD1625_ISO_EJTAG_SCPU_LOC,
+	RTD1625_ISO_EJTAG_PCPU_LOC,
+	RTD1625_ISO_EJTAG_ACPU_LOC,
+	RTD1625_ISO_I2C6_LOC,
+	RTD1625_ISO_UART0_LOC,
+	RTD1625_ISO_AI_I2S1_LOC,
+	RTD1625_ISO_AO_I2S1_LOC,
+	RTD1625_ISO_ETN_PHY_LOC,
+	RTD1625_ISO_SPDIF_LOC,
+	RTD1625_ISO_RGMII_VDSEL,
+	RTD1625_ISO_CSI_VDSEL,
+	RTD1625_ISO_SPDIF_IN_MODE,
+};
+
+static const struct pinctrl_pin_desc rtd1625_iso_pins[] = {
+	PINCTRL_PIN(RTD1625_ISO_GPIO_8, "gpio_8"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_9, "gpio_9"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_10, "gpio_10"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_11, "gpio_11"),
+	PINCTRL_PIN(RTD1625_ISO_USB_CC1, "usb_cc1"),
+	PINCTRL_PIN(RTD1625_ISO_USB_CC2, "usb_cc2"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_45, "gpio_45"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_46, "gpio_46"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_47, "gpio_47"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_48, "gpio_48"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_49, "gpio_49"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_50, "gpio_50"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_52, "gpio_52"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_94, "gpio_94"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_95, "gpio_95"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_96, "gpio_96"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_97, "gpio_97"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_98, "gpio_98"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_99, "gpio_99"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_100, "gpio_100"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_101, "gpio_101"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_102, "gpio_102"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_103, "gpio_103"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_104, "gpio_104"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_105, "gpio_105"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_106, "gpio_106"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_107, "gpio_107"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_108, "gpio_108"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_109, "gpio_109"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_110, "gpio_110"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_111, "gpio_111"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_112, "gpio_112"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_128, "gpio_128"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_129, "gpio_129"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_130, "gpio_130"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_131, "gpio_131"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_145, "gpio_145"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_146, "gpio_146"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_147, "gpio_147"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_148, "gpio_148"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_149, "gpio_149"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_150, "gpio_150"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_151, "gpio_151"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_152, "gpio_152"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_153, "gpio_153"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_154, "gpio_154"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_155, "gpio_155"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_156, "gpio_156"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_157, "gpio_157"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_158, "gpio_158"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_159, "gpio_159"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_160, "gpio_160"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_161, "gpio_161"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_162, "gpio_162"),
+	PINCTRL_PIN(RTD1625_ISO_GPIO_163, "gpio_163"),
+	PINCTRL_PIN(RTD1625_ISO_HI_WIDTH, "hi_width"),
+	PINCTRL_PIN(RTD1625_ISO_SF_EN, "sf_en"),
+	PINCTRL_PIN(RTD1625_ISO_ARM_TRACE_DBG_EN, "arm_trace_dbg_en"),
+	PINCTRL_PIN(RTD1625_ISO_EJTAG_AUCPU0_LOC, "ejtag_aucpu0_loc"),
+	PINCTRL_PIN(RTD1625_ISO_EJTAG_AUCPU1_LOC, "ejtag_aucpu1_loc"),
+	PINCTRL_PIN(RTD1625_ISO_EJTAG_VE2_LOC, "ejtag_ve2_loc"),
+	PINCTRL_PIN(RTD1625_ISO_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+	PINCTRL_PIN(RTD1625_ISO_EJTAG_PCPU_LOC, "ejtag_pcpu_loc"),
+	PINCTRL_PIN(RTD1625_ISO_EJTAG_ACPU_LOC, "ejtag_acpu_loc"),
+	PINCTRL_PIN(RTD1625_ISO_I2C6_LOC, "i2c6_loc"),
+	PINCTRL_PIN(RTD1625_ISO_UART0_LOC, "uart0_loc"),
+	PINCTRL_PIN(RTD1625_ISO_AI_I2S1_LOC, "ai_i2s1_loc"),
+	PINCTRL_PIN(RTD1625_ISO_AO_I2S1_LOC, "ao_i2s1_loc"),
+	PINCTRL_PIN(RTD1625_ISO_ETN_PHY_LOC, "etn_phy_loc"),
+	PINCTRL_PIN(RTD1625_ISO_SPDIF_LOC, "spdif_loc"),
+	PINCTRL_PIN(RTD1625_ISO_RGMII_VDSEL, "rgmii_vdsel"),
+	PINCTRL_PIN(RTD1625_ISO_CSI_VDSEL, "csi_vdsel"),
+	PINCTRL_PIN(RTD1625_ISO_SPDIF_IN_MODE, "spdif_in_mode"),
+};
+
+enum rtd1625_isom_pins_enum {
+	RTD1625_ISOM_GPIO_0 = 0,
+	RTD1625_ISOM_GPIO_1,
+	RTD1625_ISOM_GPIO_28,
+	RTD1625_ISOM_GPIO_29,
+	RTD1625_ISOM_IR_RX_LOC,
+};
+
+static const struct pinctrl_pin_desc rtd1625_isom_pins[] = {
+	PINCTRL_PIN(RTD1625_ISOM_GPIO_0, "gpio_0"),
+	PINCTRL_PIN(RTD1625_ISOM_GPIO_1, "gpio_1"),
+	PINCTRL_PIN(RTD1625_ISOM_GPIO_28, "gpio_28"),
+	PINCTRL_PIN(RTD1625_ISOM_GPIO_29, "gpio_29"),
+	PINCTRL_PIN(RTD1625_ISOM_IR_RX_LOC, "ir_rx_loc"),
+};
+
+enum rtd1625_ve4_pins_enum {
+	RTD1625_VE4_GPIO_2 = 0,
+	RTD1625_VE4_GPIO_3,
+	RTD1625_VE4_GPIO_4,
+	RTD1625_VE4_GPIO_5,
+	RTD1625_VE4_GPIO_6,
+	RTD1625_VE4_GPIO_7,
+	RTD1625_VE4_GPIO_12,
+	RTD1625_VE4_GPIO_13,
+	RTD1625_VE4_GPIO_16,
+	RTD1625_VE4_GPIO_17,
+	RTD1625_VE4_GPIO_18,
+	RTD1625_VE4_GPIO_19,
+	RTD1625_VE4_GPIO_23,
+	RTD1625_VE4_GPIO_24,
+	RTD1625_VE4_GPIO_25,
+	RTD1625_VE4_GPIO_30,
+	RTD1625_VE4_GPIO_31,
+	RTD1625_VE4_GPIO_32,
+	RTD1625_VE4_GPIO_33,
+	RTD1625_VE4_GPIO_34,
+	RTD1625_VE4_GPIO_35,
+	RTD1625_VE4_GPIO_42,
+	RTD1625_VE4_GPIO_43,
+	RTD1625_VE4_GPIO_44,
+	RTD1625_VE4_GPIO_51,
+	RTD1625_VE4_GPIO_53,
+	RTD1625_VE4_GPIO_54,
+	RTD1625_VE4_GPIO_55,
+	RTD1625_VE4_GPIO_56,
+	RTD1625_VE4_GPIO_57,
+	RTD1625_VE4_GPIO_58,
+	RTD1625_VE4_GPIO_59,
+	RTD1625_VE4_GPIO_60,
+	RTD1625_VE4_GPIO_61,
+	RTD1625_VE4_GPIO_62,
+	RTD1625_VE4_GPIO_63,
+	RTD1625_VE4_GPIO_92,
+	RTD1625_VE4_GPIO_93,
+	RTD1625_VE4_GPIO_132,
+	RTD1625_VE4_GPIO_133,
+	RTD1625_VE4_GPIO_134,
+	RTD1625_VE4_GPIO_135,
+	RTD1625_VE4_GPIO_136,
+	RTD1625_VE4_GPIO_137,
+	RTD1625_VE4_GPIO_138,
+	RTD1625_VE4_GPIO_139,
+	RTD1625_VE4_GPIO_140,
+	RTD1625_VE4_GPIO_141,
+	RTD1625_VE4_GPIO_142,
+	RTD1625_VE4_GPIO_143,
+	RTD1625_VE4_GPIO_144,
+	RTD1625_VE4_GPIO_164,
+	RTD1625_VE4_GPIO_165,
+	RTD1625_VE4_UART_LOC,
+};
+
+static const struct pinctrl_pin_desc rtd1625_ve4_pins[] = {
+	PINCTRL_PIN(RTD1625_VE4_GPIO_2, "gpio_2"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_3, "gpio_3"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_4, "gpio_4"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_5, "gpio_5"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_6, "gpio_6"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_7, "gpio_7"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_12, "gpio_12"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_13, "gpio_13"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_16, "gpio_16"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_17, "gpio_17"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_18, "gpio_18"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_19, "gpio_19"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_23, "gpio_23"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_24, "gpio_24"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_25, "gpio_25"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_30, "gpio_30"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_31, "gpio_31"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_32, "gpio_32"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_33, "gpio_33"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_34, "gpio_34"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_35, "gpio_35"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_42, "gpio_42"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_43, "gpio_43"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_44, "gpio_44"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_51, "gpio_51"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_53, "gpio_53"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_54, "gpio_54"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_55, "gpio_55"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_56, "gpio_56"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_57, "gpio_57"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_58, "gpio_58"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_59, "gpio_59"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_60, "gpio_60"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_61, "gpio_61"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_62, "gpio_62"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_63, "gpio_63"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_92, "gpio_92"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_93, "gpio_93"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_132, "gpio_132"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_133, "gpio_133"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_134, "gpio_134"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_135, "gpio_135"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_136, "gpio_136"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_137, "gpio_137"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_138, "gpio_138"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_139, "gpio_139"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_140, "gpio_140"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_141, "gpio_141"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_142, "gpio_142"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_143, "gpio_143"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_144, "gpio_144"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_164, "gpio_164"),
+	PINCTRL_PIN(RTD1625_VE4_GPIO_165, "gpio_165"),
+	PINCTRL_PIN(RTD1625_VE4_UART_LOC, "ve4_uart_loc"),
+};
+
+enum rtd1625_main2_pins_enum {
+	RTD1625_MAIN2_GPIO_14 = 0,
+	RTD1625_MAIN2_GPIO_15,
+	RTD1625_MAIN2_GPIO_20,
+	RTD1625_MAIN2_GPIO_21,
+	RTD1625_MAIN2_GPIO_22,
+	RTD1625_MAIN2_HIF_DATA,
+	RTD1625_MAIN2_HIF_EN,
+	RTD1625_MAIN2_HIF_RDY,
+	RTD1625_MAIN2_HIF_CLK,
+	RTD1625_MAIN2_GPIO_40,
+	RTD1625_MAIN2_GPIO_41,
+	RTD1625_MAIN2_GPIO_64,
+	RTD1625_MAIN2_GPIO_65,
+	RTD1625_MAIN2_GPIO_66,
+	RTD1625_MAIN2_GPIO_67,
+	RTD1625_MAIN2_EMMC_DATA_0,
+	RTD1625_MAIN2_EMMC_DATA_1,
+	RTD1625_MAIN2_EMMC_DATA_2,
+	RTD1625_MAIN2_EMMC_DATA_3,
+	RTD1625_MAIN2_EMMC_DATA_4,
+	RTD1625_MAIN2_EMMC_DATA_5,
+	RTD1625_MAIN2_EMMC_DATA_6,
+	RTD1625_MAIN2_EMMC_DATA_7,
+	RTD1625_MAIN2_EMMC_RST_N,
+	RTD1625_MAIN2_EMMC_CMD,
+	RTD1625_MAIN2_EMMC_CLK,
+	RTD1625_MAIN2_EMMC_DD_SB,
+	RTD1625_MAIN2_GPIO_80,
+	RTD1625_MAIN2_GPIO_81,
+	RTD1625_MAIN2_GPIO_82,
+	RTD1625_MAIN2_GPIO_83,
+	RTD1625_MAIN2_GPIO_84,
+	RTD1625_MAIN2_GPIO_85,
+	RTD1625_MAIN2_GPIO_86,
+	RTD1625_MAIN2_GPIO_87,
+	RTD1625_MAIN2_GPIO_88,
+	RTD1625_MAIN2_GPIO_89,
+	RTD1625_MAIN2_GPIO_90,
+	RTD1625_MAIN2_GPIO_91,
+};
+
+static const struct pinctrl_pin_desc rtd1625_main2_pins[] = {
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_14, "gpio_14"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_15, "gpio_15"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_20, "gpio_20"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_21, "gpio_21"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_22, "gpio_22"),
+	PINCTRL_PIN(RTD1625_MAIN2_HIF_DATA, "hif_data"),
+	PINCTRL_PIN(RTD1625_MAIN2_HIF_EN, "hif_en"),
+	PINCTRL_PIN(RTD1625_MAIN2_HIF_RDY, "hif_rdy"),
+	PINCTRL_PIN(RTD1625_MAIN2_HIF_CLK, "hif_clk"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_40, "gpio_40"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_41, "gpio_41"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_64, "gpio_64"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_65, "gpio_65"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_66, "gpio_66"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_67, "gpio_67"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_0, "emmc_data_0"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_1, "emmc_data_1"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_2, "emmc_data_2"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_3, "emmc_data_3"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_4, "emmc_data_4"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_5, "emmc_data_5"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_6, "emmc_data_6"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DATA_7, "emmc_data_7"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_RST_N, "emmc_rst_n"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_CMD, "emmc_cmd"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_CLK, "emmc_clk"),
+	PINCTRL_PIN(RTD1625_MAIN2_EMMC_DD_SB, "emmc_dd_sb"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_80, "gpio_80"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_81, "gpio_81"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_82, "gpio_82"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_83, "gpio_83"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_84, "gpio_84"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_85, "gpio_85"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_86, "gpio_86"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_87, "gpio_87"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_88, "gpio_88"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_89, "gpio_89"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_90, "gpio_90"),
+	PINCTRL_PIN(RTD1625_MAIN2_GPIO_91, "gpio_91"),
+};
+
+#define DECLARE_RTD1625_PIN(_pin, _name) \
+	static const unsigned int rtd1625_##_name##_pins[] = { _pin }
+
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_8, gpio_8);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_9, gpio_9);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_10, gpio_10);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_11, gpio_11);
+DECLARE_RTD1625_PIN(RTD1625_ISO_USB_CC1, usb_cc1);
+DECLARE_RTD1625_PIN(RTD1625_ISO_USB_CC2, usb_cc2);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_45, gpio_45);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_46, gpio_46);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_47, gpio_47);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_48, gpio_48);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_49, gpio_49);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_50, gpio_50);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_52, gpio_52);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_94, gpio_94);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_95, gpio_95);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_96, gpio_96);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_97, gpio_97);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_98, gpio_98);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_99, gpio_99);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_100, gpio_100);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_101, gpio_101);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_102, gpio_102);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_103, gpio_103);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_104, gpio_104);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_105, gpio_105);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_106, gpio_106);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_107, gpio_107);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_108, gpio_108);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_109, gpio_109);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_110, gpio_110);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_111, gpio_111);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_112, gpio_112);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_128, gpio_128);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_129, gpio_129);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_130, gpio_130);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_131, gpio_131);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_145, gpio_145);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_146, gpio_146);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_147, gpio_147);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_148, gpio_148);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_149, gpio_149);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_150, gpio_150);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_151, gpio_151);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_152, gpio_152);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_153, gpio_153);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_154, gpio_154);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_155, gpio_155);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_156, gpio_156);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_157, gpio_157);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_158, gpio_158);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_159, gpio_159);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_160, gpio_160);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_161, gpio_161);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_162, gpio_162);
+DECLARE_RTD1625_PIN(RTD1625_ISO_GPIO_163, gpio_163);
+
+DECLARE_RTD1625_PIN(RTD1625_ISO_HI_WIDTH, hi_width);
+DECLARE_RTD1625_PIN(RTD1625_ISO_SF_EN, sf_en);
+DECLARE_RTD1625_PIN(RTD1625_ISO_ARM_TRACE_DBG_EN, arm_trace_dbg_en);
+DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_AUCPU0_LOC, ejtag_aucpu0_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_AUCPU1_LOC, ejtag_aucpu1_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_VE2_LOC, ejtag_ve2_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_SCPU_LOC, ejtag_scpu_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_PCPU_LOC, ejtag_pcpu_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_EJTAG_ACPU_LOC, ejtag_acpu_loc);
+
+DECLARE_RTD1625_PIN(RTD1625_ISO_I2C6_LOC, i2c6_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_UART0_LOC, uart0_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_AI_I2S1_LOC, ai_i2s1_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_AO_I2S1_LOC, ao_i2s1_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_ETN_PHY_LOC, etn_phy_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_SPDIF_LOC, spdif_loc);
+DECLARE_RTD1625_PIN(RTD1625_ISO_RGMII_VDSEL, rgmii_vdsel);
+DECLARE_RTD1625_PIN(RTD1625_ISO_CSI_VDSEL, csi_vdsel);
+DECLARE_RTD1625_PIN(RTD1625_ISO_SPDIF_IN_MODE, spdif_in_mode);
+
+DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_0, gpio_0);
+DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_1, gpio_1);
+DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_28, gpio_28);
+DECLARE_RTD1625_PIN(RTD1625_ISOM_GPIO_29, gpio_29);
+DECLARE_RTD1625_PIN(RTD1625_ISOM_IR_RX_LOC, ir_rx_loc);
+
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_2, gpio_2);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_3, gpio_3);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_4, gpio_4);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_5, gpio_5);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_6, gpio_6);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_7, gpio_7);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_12, gpio_12);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_13, gpio_13);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_16, gpio_16);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_17, gpio_17);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_18, gpio_18);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_19, gpio_19);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_23, gpio_23);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_24, gpio_24);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_25, gpio_25);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_30, gpio_30);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_31, gpio_31);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_32, gpio_32);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_33, gpio_33);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_34, gpio_34);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_35, gpio_35);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_42, gpio_42);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_43, gpio_43);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_44, gpio_44);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_51, gpio_51);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_53, gpio_53);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_54, gpio_54);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_55, gpio_55);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_56, gpio_56);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_57, gpio_57);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_58, gpio_58);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_59, gpio_59);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_60, gpio_60);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_61, gpio_61);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_62, gpio_62);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_63, gpio_63);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_92, gpio_92);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_93, gpio_93);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_132, gpio_132);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_133, gpio_133);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_134, gpio_134);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_135, gpio_135);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_136, gpio_136);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_137, gpio_137);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_138, gpio_138);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_139, gpio_139);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_140, gpio_140);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_141, gpio_141);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_142, gpio_142);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_143, gpio_143);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_144, gpio_144);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_164, gpio_164);
+DECLARE_RTD1625_PIN(RTD1625_VE4_GPIO_165, gpio_165);
+DECLARE_RTD1625_PIN(RTD1625_VE4_UART_LOC, ve4_uart_loc);
+
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_RST_N, emmc_rst_n);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DD_SB, emmc_dd_sb);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_CLK, emmc_clk);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_CMD, emmc_cmd);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_0, emmc_data_0);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_1, emmc_data_1);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_2, emmc_data_2);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_3, emmc_data_3);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_4, emmc_data_4);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_5, emmc_data_5);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_6, emmc_data_6);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_EMMC_DATA_7, emmc_data_7);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_14, gpio_14);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_15, gpio_15);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_20, gpio_20);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_21, gpio_21);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_22, gpio_22);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_DATA, hif_data);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_EN, hif_en);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_RDY, hif_rdy);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_HIF_CLK, hif_clk);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_40, gpio_40);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_41, gpio_41);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_64, gpio_64);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_65, gpio_65);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_66, gpio_66);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_67, gpio_67);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_80, gpio_80);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_81, gpio_81);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_82, gpio_82);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_83, gpio_83);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_84, gpio_84);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_85, gpio_85);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_86, gpio_86);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_87, gpio_87);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_88, gpio_88);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_89, gpio_89);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_90, gpio_90);
+DECLARE_RTD1625_PIN(RTD1625_MAIN2_GPIO_91, gpio_91);
+
+#define RTD1625_GROUP(_name) \
+	{ \
+		.name = # _name, \
+		.pins = rtd1625_ ## _name ## _pins, \
+		.num_pins = ARRAY_SIZE(rtd1625_ ## _name ## _pins), \
+	}
+
+static const struct rtd_pin_group_desc rtd1625_iso_pin_groups[] = {
+	RTD1625_GROUP(gpio_8),
+	RTD1625_GROUP(gpio_9),
+	RTD1625_GROUP(gpio_10),
+	RTD1625_GROUP(gpio_11),
+	RTD1625_GROUP(usb_cc1),
+	RTD1625_GROUP(usb_cc2),
+	RTD1625_GROUP(gpio_45),
+	RTD1625_GROUP(gpio_46),
+	RTD1625_GROUP(gpio_47),
+	RTD1625_GROUP(gpio_48),
+	RTD1625_GROUP(gpio_49),
+	RTD1625_GROUP(gpio_50),
+	RTD1625_GROUP(gpio_52),
+	RTD1625_GROUP(gpio_94),
+	RTD1625_GROUP(gpio_95),
+	RTD1625_GROUP(gpio_96),
+	RTD1625_GROUP(gpio_97),
+	RTD1625_GROUP(gpio_98),
+	RTD1625_GROUP(gpio_99),
+	RTD1625_GROUP(gpio_100),
+	RTD1625_GROUP(gpio_101),
+	RTD1625_GROUP(gpio_102),
+	RTD1625_GROUP(gpio_103),
+	RTD1625_GROUP(gpio_104),
+	RTD1625_GROUP(gpio_105),
+	RTD1625_GROUP(gpio_106),
+	RTD1625_GROUP(gpio_107),
+	RTD1625_GROUP(gpio_108),
+	RTD1625_GROUP(gpio_109),
+	RTD1625_GROUP(gpio_110),
+	RTD1625_GROUP(gpio_111),
+	RTD1625_GROUP(gpio_112),
+	RTD1625_GROUP(gpio_128),
+	RTD1625_GROUP(gpio_129),
+	RTD1625_GROUP(gpio_130),
+	RTD1625_GROUP(gpio_131),
+	RTD1625_GROUP(gpio_145),
+	RTD1625_GROUP(gpio_146),
+	RTD1625_GROUP(gpio_147),
+	RTD1625_GROUP(gpio_148),
+	RTD1625_GROUP(gpio_149),
+	RTD1625_GROUP(gpio_150),
+	RTD1625_GROUP(gpio_151),
+	RTD1625_GROUP(gpio_152),
+	RTD1625_GROUP(gpio_153),
+	RTD1625_GROUP(gpio_154),
+	RTD1625_GROUP(gpio_155),
+	RTD1625_GROUP(gpio_156),
+	RTD1625_GROUP(gpio_157),
+	RTD1625_GROUP(gpio_158),
+	RTD1625_GROUP(gpio_159),
+	RTD1625_GROUP(gpio_160),
+	RTD1625_GROUP(gpio_161),
+	RTD1625_GROUP(gpio_162),
+	RTD1625_GROUP(gpio_163),
+	RTD1625_GROUP(hi_width),
+	RTD1625_GROUP(sf_en),
+	RTD1625_GROUP(arm_trace_dbg_en),
+	RTD1625_GROUP(ejtag_aucpu0_loc),
+	RTD1625_GROUP(ejtag_aucpu1_loc),
+	RTD1625_GROUP(ejtag_ve2_loc),
+	RTD1625_GROUP(ejtag_scpu_loc),
+	RTD1625_GROUP(ejtag_pcpu_loc),
+	RTD1625_GROUP(ejtag_acpu_loc),
+	RTD1625_GROUP(i2c6_loc),
+	RTD1625_GROUP(uart0_loc),
+	RTD1625_GROUP(ai_i2s1_loc),
+	RTD1625_GROUP(ao_i2s1_loc),
+	RTD1625_GROUP(etn_phy_loc),
+	RTD1625_GROUP(spdif_loc),
+	RTD1625_GROUP(rgmii_vdsel),
+	RTD1625_GROUP(csi_vdsel),
+	RTD1625_GROUP(spdif_in_mode),
+};
+
+static const struct rtd_pin_group_desc rtd1625_isom_pin_groups[] = {
+	RTD1625_GROUP(gpio_0),
+	RTD1625_GROUP(gpio_1),
+	RTD1625_GROUP(gpio_28),
+	RTD1625_GROUP(gpio_29),
+	RTD1625_GROUP(ir_rx_loc),
+};
+
+static const struct rtd_pin_group_desc rtd1625_ve4_pin_groups[] = {
+	RTD1625_GROUP(gpio_2),
+	RTD1625_GROUP(gpio_3),
+	RTD1625_GROUP(gpio_4),
+	RTD1625_GROUP(gpio_5),
+	RTD1625_GROUP(gpio_6),
+	RTD1625_GROUP(gpio_7),
+	RTD1625_GROUP(gpio_12),
+	RTD1625_GROUP(gpio_13),
+	RTD1625_GROUP(gpio_16),
+	RTD1625_GROUP(gpio_17),
+	RTD1625_GROUP(gpio_18),
+	RTD1625_GROUP(gpio_19),
+	RTD1625_GROUP(gpio_23),
+	RTD1625_GROUP(gpio_24),
+	RTD1625_GROUP(gpio_25),
+	RTD1625_GROUP(gpio_30),
+	RTD1625_GROUP(gpio_31),
+	RTD1625_GROUP(gpio_32),
+	RTD1625_GROUP(gpio_33),
+	RTD1625_GROUP(gpio_34),
+	RTD1625_GROUP(gpio_35),
+	RTD1625_GROUP(gpio_42),
+	RTD1625_GROUP(gpio_43),
+	RTD1625_GROUP(gpio_44),
+	RTD1625_GROUP(gpio_51),
+	RTD1625_GROUP(gpio_53),
+	RTD1625_GROUP(gpio_54),
+	RTD1625_GROUP(gpio_55),
+	RTD1625_GROUP(gpio_56),
+	RTD1625_GROUP(gpio_57),
+	RTD1625_GROUP(gpio_58),
+	RTD1625_GROUP(gpio_59),
+	RTD1625_GROUP(gpio_60),
+	RTD1625_GROUP(gpio_61),
+	RTD1625_GROUP(gpio_62),
+	RTD1625_GROUP(gpio_63),
+	RTD1625_GROUP(gpio_92),
+	RTD1625_GROUP(gpio_93),
+	RTD1625_GROUP(gpio_132),
+	RTD1625_GROUP(gpio_133),
+	RTD1625_GROUP(gpio_134),
+	RTD1625_GROUP(gpio_135),
+	RTD1625_GROUP(gpio_136),
+	RTD1625_GROUP(gpio_137),
+	RTD1625_GROUP(gpio_138),
+	RTD1625_GROUP(gpio_139),
+	RTD1625_GROUP(gpio_140),
+	RTD1625_GROUP(gpio_141),
+	RTD1625_GROUP(gpio_142),
+	RTD1625_GROUP(gpio_143),
+	RTD1625_GROUP(gpio_144),
+	RTD1625_GROUP(gpio_164),
+	RTD1625_GROUP(gpio_165),
+	RTD1625_GROUP(ve4_uart_loc),
+};
+
+static const struct rtd_pin_group_desc rtd1625_main2_pin_groups[] = {
+	RTD1625_GROUP(gpio_14),
+	RTD1625_GROUP(gpio_15),
+	RTD1625_GROUP(gpio_20),
+	RTD1625_GROUP(gpio_21),
+	RTD1625_GROUP(gpio_22),
+	RTD1625_GROUP(hif_data),
+	RTD1625_GROUP(hif_en),
+	RTD1625_GROUP(hif_rdy),
+	RTD1625_GROUP(hif_clk),
+	RTD1625_GROUP(gpio_40),
+	RTD1625_GROUP(gpio_41),
+	RTD1625_GROUP(gpio_64),
+	RTD1625_GROUP(gpio_65),
+	RTD1625_GROUP(gpio_66),
+	RTD1625_GROUP(gpio_67),
+	RTD1625_GROUP(emmc_data_0),
+	RTD1625_GROUP(emmc_data_1),
+	RTD1625_GROUP(emmc_data_2),
+	RTD1625_GROUP(emmc_data_3),
+	RTD1625_GROUP(emmc_data_4),
+	RTD1625_GROUP(emmc_data_5),
+	RTD1625_GROUP(emmc_data_6),
+	RTD1625_GROUP(emmc_data_7),
+	RTD1625_GROUP(emmc_rst_n),
+	RTD1625_GROUP(emmc_cmd),
+	RTD1625_GROUP(emmc_clk),
+	RTD1625_GROUP(emmc_dd_sb),
+	RTD1625_GROUP(gpio_80),
+	RTD1625_GROUP(gpio_81),
+	RTD1625_GROUP(gpio_82),
+	RTD1625_GROUP(gpio_83),
+	RTD1625_GROUP(gpio_84),
+	RTD1625_GROUP(gpio_85),
+	RTD1625_GROUP(gpio_86),
+	RTD1625_GROUP(gpio_87),
+	RTD1625_GROUP(gpio_88),
+	RTD1625_GROUP(gpio_89),
+	RTD1625_GROUP(gpio_90),
+	RTD1625_GROUP(gpio_91),
+};
+
+static const char * const rtd1625_iso_gpio_groups[] = {
+	"gpio_10", "gpio_100", "gpio_101", "gpio_102", "gpio_103", "gpio_104",
+	"gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio_109", "gpio_11",
+	"gpio_110", "gpio_111", "gpio_112", "gpio_128", "gpio_129", "gpio_130",
+	"gpio_131", "gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149",
+	"gpio_150", "gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155",
+	"gpio_156", "gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161",
+	"gpio_162", "gpio_163", "gpio_45", "gpio_46", "gpio_47", "gpio_48",
+	"gpio_49", "gpio_50", "gpio_52", "gpio_8", "gpio_9", "gpio_94", "gpio_95",
+	"gpio_96", "gpio_97", "gpio_98", "gpio_99", "usb_cc1", "usb_cc2"
+};
+
+static const char * const rtd1625_iso_uart1_groups[] = {
+	"gpio_10", "gpio_11", "gpio_8", "gpio_9"
+};
+
+static const char * const rtd1625_iso_iso_tristate_groups[] = {
+	"gpio_10", "gpio_100", "gpio_101", "gpio_102", "gpio_103", "gpio_104",
+	"gpio_105", "gpio_106", "gpio_107", "gpio_108", "gpio_109", "gpio_11",
+	"gpio_110", "gpio_111", "gpio_112", "gpio_128", "gpio_129", "gpio_130",
+	"gpio_131", "gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149",
+	"gpio_150", "gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155",
+	"gpio_156", "gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161",
+	"gpio_162", "gpio_163", "gpio_45", "gpio_46", "gpio_47", "gpio_48",
+	"gpio_49", "gpio_50", "gpio_52", "gpio_8", "gpio_9", "gpio_94", "gpio_95",
+	"gpio_96", "gpio_97", "gpio_98", "gpio_99", "usb_cc1", "usb_cc2"
+};
+
+static const char * const rtd1625_iso_usb_cc1_groups[] = {
+	"usb_cc1"
+};
+
+static const char * const rtd1625_iso_usb_cc2_groups[] = {
+	"usb_cc2"
+};
+
+static const char * const rtd1625_iso_sdio_groups[] = {
+	"gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49", "gpio_50"
+};
+
+static const char * const rtd1625_iso_scpu_ejtag_loc2_groups[] = {
+	"ejtag_scpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
+};
+
+static const char * const rtd1625_iso_acpu_ejtag_loc2_groups[] = {
+	"ejtag_acpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
+};
+
+static const char * const rtd1625_iso_pcpu_ejtag_loc2_groups[] = {
+	"ejtag_pcpu_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
+};
+
+static const char * const rtd1625_iso_aucpu0_ejtag_loc2_groups[] = {
+	"ejtag_aucpu0_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
+};
+
+static const char * const rtd1625_iso_ve2_ejtag_loc2_groups[] = {
+	"ejtag_ve2_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
+};
+
+static const char * const rtd1625_iso_aucpu1_ejtag_loc2_groups[] = {
+	"ejtag_aucpu1_loc", "gpio_45", "gpio_46", "gpio_47", "gpio_48", "gpio_49"
+};
+
+static const char * const rtd1625_iso_pwm4_groups[] = {
+	"gpio_52"
+};
+
+static const char * const rtd1625_iso_uart7_groups[] = {
+	"gpio_94", "gpio_95"
+};
+
+static const char * const rtd1625_iso_pwm2_loc1_groups[] = {
+	"gpio_95"
+};
+
+static const char * const rtd1625_iso_uart8_groups[] = {
+	"gpio_96", "gpio_97"
+};
+
+static const char * const rtd1625_iso_pwm3_loc1_groups[] = {
+	"gpio_97"
+};
+
+static const char * const rtd1625_iso_ai_tdm0_groups[] = {
+	"gpio_100", "gpio_101", "gpio_102", "gpio_98"
+};
+
+static const char * const rtd1625_iso_vtc_i2s_groups[] = {
+	"gpio_100", "gpio_101", "gpio_102", "gpio_161", "gpio_98"
+};
+
+static const char * const rtd1625_iso_ai_i2s0_groups[] = {
+	"gpio_100", "gpio_101", "gpio_102", "gpio_156", "gpio_160", "gpio_161",
+	"gpio_98"
+};
+
+static const char * const rtd1625_iso_ao_tdm0_groups[] = {
+	"gpio_100", "gpio_101", "gpio_102", "gpio_99"
+};
+
+static const char * const rtd1625_iso_ao_i2s0_groups[] = {
+	"gpio_100", "gpio_101", "gpio_102", "gpio_112", "gpio_99"
+};
+
+static const char * const rtd1625_iso_ai_tdm1_groups[] = {
+	"gpio_103", "gpio_105", "gpio_106", "gpio_107"
+};
+
+static const char * const rtd1625_iso_ai_i2s1_loc0_groups[] = {
+	"ai_i2s1_loc", "gpio_103", "gpio_105", "gpio_106", "gpio_107"
+};
+
+static const char * const rtd1625_iso_ao_i2s0_loc1_groups[] = {
+	"gpio_103", "gpio_107"
+};
+
+static const char * const rtd1625_iso_ao_tdm1_loc0_groups[] = {
+	"gpio_104"
+};
+
+static const char * const rtd1625_iso_ao_i2s1_loc0_groups[] = {
+	"ao_i2s1_loc", "gpio_104", "gpio_105", "gpio_106", "gpio_107"
+};
+
+static const char * const rtd1625_iso_ao_tdm1_groups[] = {
+	"gpio_105", "gpio_106", "gpio_107"
+};
+
+static const char * const rtd1625_iso_ai_tdm2_groups[] = {
+	"gpio_108", "gpio_110", "gpio_111", "gpio_112"
+};
+
+static const char * const rtd1625_iso_pcm_groups[] = {
+	"gpio_108", "gpio_109", "gpio_110", "gpio_111"
+};
+
+static const char * const rtd1625_iso_ai_i2s2_groups[] = {
+	"gpio_108", "gpio_110", "gpio_111", "gpio_112"
+};
+
+static const char * const rtd1625_iso_ao_tdm2_groups[] = {
+	"gpio_109", "gpio_110", "gpio_111", "gpio_112"
+};
+
+static const char * const rtd1625_iso_ao_i2s2_groups[] = {
+	"gpio_109", "gpio_110", "gpio_111", "gpio_112"
+};
+
+static const char * const rtd1625_iso_vtc_ao_i2s_groups[] = {
+	"gpio_109", "gpio_110", "gpio_111", "gpio_112"
+};
+
+static const char * const rtd1625_iso_scpu_ejtag_loc0_groups[] = {
+	"ejtag_scpu_loc", "gpio_112"
+};
+
+static const char * const rtd1625_iso_acpu_ejtag_loc0_groups[] = {
+	"ejtag_acpu_loc", "gpio_112"
+};
+
+static const char * const rtd1625_iso_pcpu_ejtag_loc0_groups[] = {
+	"ejtag_pcpu_loc", "gpio_112"
+};
+
+static const char * const rtd1625_iso_aucpu0_ejtag_loc0_groups[] = {
+	"ejtag_aucpu0_loc", "gpio_112"
+};
+
+static const char * const rtd1625_iso_ve2_ejtag_loc0_groups[] = {
+	"ejtag_ve2_loc", "gpio_112"
+};
+
+static const char * const rtd1625_iso_gpu_ejtag_loc0_groups[] = {
+	"gpio_112"
+};
+
+static const char * const rtd1625_iso_ao_tdm1_loc1_groups[] = {
+	"gpio_112"
+};
+
+static const char * const rtd1625_iso_aucpu1_ejtag_loc0_groups[] = {
+	"ejtag_aucpu1_loc", "gpio_112"
+};
+
+static const char * const rtd1625_iso_edptx_hdp_groups[] = {
+	"gpio_128"
+};
+
+static const char * const rtd1625_iso_pwm5_groups[] = {
+	"gpio_130"
+};
+
+static const char * const rtd1625_iso_vi0_dtv_groups[] = {
+	"gpio_145", "gpio_146", "gpio_147", "gpio_148", "gpio_149", "gpio_150",
+	"gpio_151", "gpio_152", "gpio_153", "gpio_154", "gpio_155", "gpio_156",
+	"gpio_157", "gpio_158", "gpio_159", "gpio_160", "gpio_161"
+};
+
+static const char * const rtd1625_iso_vi1_dtv_groups[] = {
+	"gpio_154", "gpio_155", "gpio_156", "gpio_157", "gpio_158", "gpio_159",
+	"gpio_160", "gpio_161", "gpio_162"
+};
+
+static const char * const rtd1625_iso_ao_i2s0_loc0_groups[] = {
+	"gpio_154", "gpio_155"
+};
+
+static const char * const rtd1625_iso_dmic0_groups[] = {
+	"gpio_156", "gpio_157"
+};
+
+static const char * const rtd1625_iso_vtc_dmic_groups[] = {
+	"gpio_156", "gpio_157", "gpio_158", "gpio_159"
+};
+
+static const char * const rtd1625_iso_ai_i2s1_loc1_groups[] = {
+	"ai_i2s1_loc", "gpio_157", "gpio_158", "gpio_159", "gpio_160"
+};
+
+static const char * const rtd1625_iso_ao_i2s1_loc1_groups[] = {
+	"ao_i2s1_loc", "gpio_157", "gpio_158", "gpio_159", "gpio_161"
+};
+
+static const char * const rtd1625_iso_dmic1_groups[] = {
+	"gpio_158", "gpio_159"
+};
+
+static const char * const rtd1625_iso_dmic2_groups[] = {
+	"gpio_160", "gpio_161"
+};
+
+static const char * const rtd1625_iso_pwm0_loc2_groups[] = {
+	"gpio_162"
+};
+
+static const char * const rtd1625_iso_spdif_in_coaxial_groups[] = {
+	"gpio_163", "spdif_in_mode"
+};
+
+static const char * const rtd1625_iso_spdif_in_gpio_groups[] = {
+	"spdif_in_mode"
+};
+
+static const char * const rtd1625_iso_hi_width_disable_groups[] = {
+	"hi_width"
+};
+
+static const char * const rtd1625_iso_hi_width_1bit_groups[] = {
+	"hi_width"
+};
+
+static const char * const rtd1625_iso_sf_disable_groups[] = {
+	"sf_en"
+};
+
+static const char * const rtd1625_iso_sf_enable_groups[] = {
+	"sf_en"
+};
+
+static const char * const rtd1625_iso_arm_trace_debug_disable_groups[] = {
+	"arm_trace_dbg_en"
+};
+
+static const char * const rtd1625_iso_arm_trace_debug_enable_groups[] = {
+	"arm_trace_dbg_en"
+};
+
+static const char * const rtd1625_iso_aucpu0_ejtag_loc1_groups[] = {
+	"ejtag_aucpu0_loc"
+};
+
+static const char * const rtd1625_iso_aucpu1_ejtag_loc1_groups[] = {
+	"ejtag_aucpu1_loc"
+};
+
+static const char * const rtd1625_iso_ve2_ejtag_loc1_groups[] = {
+	"ejtag_ve2_loc"
+};
+
+static const char * const rtd1625_iso_scpu_ejtag_loc1_groups[] = {
+	"ejtag_scpu_loc"
+};
+
+static const char * const rtd1625_iso_pcpu_ejtag_loc1_groups[] = {
+	"ejtag_pcpu_loc"
+};
+
+static const char * const rtd1625_iso_acpu_ejtag_loc1_groups[] = {
+	"ejtag_acpu_loc"
+};
+
+static const char * const rtd1625_iso_i2c6_loc0_groups[] = {
+	"i2c6_loc"
+};
+
+static const char * const rtd1625_iso_i2c6_loc1_groups[] = {
+	"i2c6_loc"
+};
+
+static const char * const rtd1625_iso_uart0_loc0_groups[] = {
+	"uart0_loc"
+};
+
+static const char * const rtd1625_iso_uart0_loc1_groups[] = {
+	"uart0_loc"
+};
+
+static const char * const rtd1625_iso_etn_phy_loc0_groups[] = {
+	"etn_phy_loc"
+};
+
+static const char * const rtd1625_iso_etn_phy_loc1_groups[] = {
+	"etn_phy_loc"
+};
+
+static const char * const rtd1625_iso_spdif_loc0_groups[] = {
+	"spdif_loc"
+};
+
+static const char * const rtd1625_iso_spdif_loc1_groups[] = {
+	"spdif_loc"
+};
+
+static const char * const rtd1625_iso_rgmii_1v2_groups[] = {
+	"rgmii_vdsel"
+};
+
+static const char * const rtd1625_iso_rgmii_1v8_groups[] = {
+	"rgmii_vdsel"
+};
+
+static const char * const rtd1625_iso_rgmii_2v5_groups[] = {
+	"rgmii_vdsel"
+};
+
+static const char * const rtd1625_iso_rgmii_3v3_groups[] = {
+	"rgmii_vdsel"
+};
+
+static const char * const rtd1625_iso_csi_1v2_groups[] = {
+	"csi_vdsel"
+};
+
+static const char * const rtd1625_iso_csi_1v8_groups[] = {
+	"csi_vdsel"
+};
+
+static const char * const rtd1625_iso_csi_2v5_groups[] = {
+	"csi_vdsel"
+};
+
+static const char * const rtd1625_iso_csi_3v3_groups[] = {
+	"csi_vdsel"
+};
+
+static const char * const rtd1625_isom_gpio_groups[] = {
+	"gpio_0", "gpio_1", "gpio_28", "gpio_29"
+};
+
+static const char * const rtd1625_isom_pctrl_groups[] = {
+	"gpio_0", "gpio_1", "gpio_28", "gpio_29"
+};
+
+static const char * const rtd1625_isom_iso_tristate_groups[] = {
+	"gpio_0", "gpio_1", "gpio_28", "gpio_29"
+};
+
+static const char * const rtd1625_isom_ir_rx_loc1_groups[] = {
+	"gpio_1", "ir_rx_loc"
+};
+
+static const char * const rtd1625_isom_uart10_groups[] = {
+	"gpio_28", "gpio_29"
+};
+
+static const char * const rtd1625_isom_isom_dbg_out_groups[] = {
+	"gpio_28", "gpio_29"
+};
+
+static const char * const rtd1625_isom_ir_rx_loc0_groups[] = {
+	"gpio_29", "ir_rx_loc"
+};
+
+static const char * const rtd1625_ve4_gpio_groups[] = {
+	"gpio_12", "gpio_13", "gpio_132", "gpio_133", "gpio_134", "gpio_135",
+	"gpio_136", "gpio_137", "gpio_138", "gpio_139", "gpio_140", "gpio_141",
+	"gpio_142", "gpio_143", "gpio_144", "gpio_16", "gpio_164", "gpio_165",
+	"gpio_17", "gpio_18", "gpio_19", "gpio_2", "gpio_23", "gpio_24", "gpio_25",
+	"gpio_3", "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", "gpio_35",
+	"gpio_4", "gpio_42", "gpio_43", "gpio_44", "gpio_5", "gpio_51", "gpio_53",
+	"gpio_54", "gpio_55", "gpio_56", "gpio_57", "gpio_58", "gpio_59", "gpio_6",
+	"gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_7", "gpio_92", "gpio_93"
+};
+
+static const char * const rtd1625_ve4_uart0_loc0_groups[] = {
+	"gpio_2", "gpio_3"
+};
+
+static const char * const rtd1625_ve4_iso_tristate_groups[] = {
+	"gpio_12", "gpio_13", "gpio_132", "gpio_133", "gpio_134", "gpio_135",
+	"gpio_136", "gpio_137", "gpio_138", "gpio_139", "gpio_140", "gpio_141",
+	"gpio_142", "gpio_143", "gpio_144", "gpio_16", "gpio_164", "gpio_165",
+	"gpio_17", "gpio_18", "gpio_19", "gpio_2", "gpio_23", "gpio_24", "gpio_25",
+	"gpio_3", "gpio_30", "gpio_31", "gpio_32", "gpio_33", "gpio_34", "gpio_35",
+	"gpio_4", "gpio_42", "gpio_43", "gpio_44", "gpio_5", "gpio_51", "gpio_53",
+	"gpio_54", "gpio_55", "gpio_56", "gpio_57", "gpio_58", "gpio_59", "gpio_6",
+	"gpio_60", "gpio_61", "gpio_62", "gpio_63", "gpio_7", "gpio_92", "gpio_93"
+};
+
+static const char * const rtd1625_ve4_uart2_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_gspi0_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_scpu_ejtag_loc0_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_acpu_ejtag_loc0_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_pcpu_ejtag_loc0_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_aucpu0_ejtag_loc0_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_ve2_ejtag_loc0_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_gpu_ejtag_loc0_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_aucpu1_ejtag_loc0_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+
+static const char * const rtd1625_ve4_pwm0_loc1_groups[] = {
+	"gpio_6"
+};
+
+static const char * const rtd1625_ve4_pwm1_loc0_groups[] = {
+	"gpio_7"
+};
+
+static const char * const rtd1625_ve4_i2c0_groups[] = {
+	"gpio_12", "gpio_13"
+};
+
+static const char * const rtd1625_ve4_pwm0_loc3_groups[] = {
+	"gpio_12"
+};
+
+static const char * const rtd1625_ve4_dptx_hpd_groups[] = {
+	"gpio_16"
+};
+
+static const char * const rtd1625_ve4_pwm2_loc0_groups[] = {
+	"gpio_16"
+};
+
+static const char * const rtd1625_ve4_pcie0_groups[] = {
+	"gpio_18"
+};
+
+static const char * const rtd1625_ve4_pwm3_loc0_groups[] = {
+	"gpio_19"
+};
+
+static const char * const rtd1625_ve4_i2c3_groups[] = {
+	"gpio_24", "gpio_25"
+};
+
+static const char * const rtd1625_ve4_pcie1_groups[] = {
+	"gpio_30"
+};
+
+static const char * const rtd1625_ve4_uart9_groups[] = {
+	"gpio_32", "gpio_33"
+};
+
+static const char * const rtd1625_ve4_ve4_uart_loc2_groups[] = {
+	"gpio_32", "gpio_33", "ve4_uart_loc"
+};
+
+static const char * const rtd1625_ve4_sd_groups[] = {
+	"gpio_42", "gpio_43"
+};
+
+static const char * const rtd1625_ve4_i2c6_loc1_groups[] = {
+	"gpio_51", "gpio_61"
+};
+
+static const char * const rtd1625_ve4_uart3_groups[] = {
+	"gpio_53", "gpio_54", "gpio_55", "gpio_56"
+};
+
+static const char * const rtd1625_ve4_ts0_groups[] = {
+	"gpio_53", "gpio_54", "gpio_55", "gpio_56"
+};
+
+static const char * const rtd1625_ve4_gspi2_groups[] = {
+	"gpio_53", "gpio_54", "gpio_55", "gpio_56"
+};
+
+static const char * const rtd1625_ve4_ve4_uart_loc0_groups[] = {
+	"gpio_53", "gpio_54", "ve4_uart_loc"
+};
+
+static const char * const rtd1625_ve4_uart5_groups[] = {
+	"gpio_57", "gpio_58"
+};
+
+static const char * const rtd1625_ve4_uart0_loc1_groups[] = {
+	"gpio_57", "gpio_58"
+};
+
+static const char * const rtd1625_ve4_gspi1_groups[] = {
+	"gpio_57", "gpio_58", "gpio_59", "gpio_60"
+};
+
+static const char * const rtd1625_ve4_uart4_groups[] = {
+	"gpio_59", "gpio_60"
+};
+
+static const char * const rtd1625_ve4_i2c4_groups[] = {
+	"gpio_59", "gpio_60"
+};
+
+static const char * const rtd1625_ve4_spdif_out_groups[] = {
+	"gpio_61"
+};
+
+static const char * const rtd1625_ve4_spdif_in_optical_groups[] = {
+	"gpio_61"
+};
+
+static const char * const rtd1625_ve4_pll_test_loc0_groups[] = {
+	"gpio_62", "gpio_63"
+};
+
+static const char * const rtd1625_ve4_uart6_groups[] = {
+	"gpio_92", "gpio_93"
+};
+
+static const char * const rtd1625_ve4_i2c7_groups[] = {
+	"gpio_92", "gpio_93"
+};
+
+static const char * const rtd1625_ve4_ve4_uart_loc1_groups[] = {
+	"gpio_92", "gpio_93", "ve4_uart_loc"
+};
+
+static const char * const rtd1625_ve4_pwm1_loc1_groups[] = {
+	"gpio_93"
+};
+
+static const char * const rtd1625_ve4_pwm6_groups[] = {
+	"gpio_132"
+};
+
+static const char * const rtd1625_ve4_ts1_groups[] = {
+	"gpio_133", "gpio_134", "gpio_135", "gpio_136"
+};
+
+static const char * const rtd1625_ve4_pwm0_loc0_groups[] = {
+	"gpio_136"
+};
+
+static const char * const rtd1625_ve4_i2c6_loc0_groups[] = {
+	"gpio_137", "gpio_138"
+};
+
+static const char * const rtd1625_ve4_csi0_groups[] = {
+	"gpio_141"
+};
+
+static const char * const rtd1625_ve4_csi1_groups[] = {
+	"gpio_144"
+};
+
+static const char * const rtd1625_ve4_etn_led_loc1_groups[] = {
+	"gpio_164", "gpio_165"
+};
+
+static const char * const rtd1625_ve4_etn_phy_loc1_groups[] = {
+	"gpio_164", "gpio_165"
+};
+
+static const char * const rtd1625_ve4_i2c5_groups[] = {
+	"gpio_164", "gpio_165"
+};
+
+static const char * const rtd1625_main2_gpio_groups[] = {
+	"emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2",
+	"emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"emmc_dd_sb", "emmc_rst_n", "gpio_14", "gpio_15", "gpio_20", "gpio_21",
+	"gpio_22", "gpio_40", "gpio_41", "gpio_64", "gpio_65", "gpio_66", "gpio_67",
+	"gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_85", "gpio_86",
+	"gpio_87", "gpio_88", "gpio_89", "gpio_90", "gpio_91", "hif_clk",
+	"hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_emmc_groups[] = {
+	"emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2",
+	"emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"emmc_dd_sb", "emmc_rst_n"
+};
+
+static const char * const rtd1625_main2_iso_tristate_groups[] = {
+	"emmc_clk", "emmc_cmd", "emmc_data_0", "emmc_data_1", "emmc_data_2",
+	"emmc_data_3", "emmc_data_4", "emmc_data_5", "emmc_data_6", "emmc_data_7",
+	"emmc_dd_sb", "emmc_rst_n", "gpio_14", "gpio_15", "gpio_20", "gpio_21",
+	"gpio_40", "gpio_41", "gpio_64", "gpio_65", "gpio_66", "gpio_67", "gpio_80",
+	"gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_85", "gpio_86", "gpio_87",
+	"gpio_88", "gpio_89", "gpio_90", "gpio_91", "hif_clk", "hif_data", "hif_en",
+	"hif_rdy"
+};
+
+static const char * const rtd1625_main2_nf_groups[] = {
+	"emmc_data_0", "emmc_data_1", "emmc_data_2", "emmc_data_3", "emmc_data_4",
+	"emmc_data_5"
+};
+
+static const char * const rtd1625_main2_etn_led_loc0_groups[] = {
+	"gpio_14", "gpio_15"
+};
+
+static const char * const rtd1625_main2_etn_phy_loc0_groups[] = {
+	"gpio_14", "gpio_15"
+};
+
+static const char * const rtd1625_main2_rgmii_groups[] = {
+	"gpio_14", "gpio_15", "gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84",
+	"gpio_85", "gpio_86", "gpio_87", "gpio_88", "gpio_89", "gpio_90", "gpio_91"
+};
+
+static const char * const rtd1625_main2_i2c1_groups[] = {
+	"gpio_20", "gpio_21"
+};
+
+static const char * const rtd1625_main2_dbg_out1_groups[] = {
+	"gpio_22"
+};
+
+static const char * const rtd1625_main2_sd_groups[] = {
+	"gpio_40", "gpio_41", "hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_scpu_ejtag_loc1_groups[] = {
+	"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_acpu_ejtag_loc1_groups[] = {
+	"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_pcpu_ejtag_loc1_groups[] = {
+	"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_aupu0_ejtag_loc1_groups[] = {
+	"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_ve2_ejtag_loc1_groups[] = {
+	"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_hi_loc0_groups[] = {
+	"hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_hi_m_groups[] = {
+	"hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_aupu1_ejtag_loc1_groups[] = {
+	"gpio_40", "hif_clk", "hif_data", "hif_en", "hif_rdy"
+};
+
+static const char * const rtd1625_main2_spi_groups[] = {
+	"gpio_64", "gpio_65", "gpio_66", "gpio_67"
+};
+
+static const char * const rtd1625_main2_pll_test_loc1_groups[] = {
+	"gpio_65", "gpio_66"
+};
+
+static const char * const rtd1625_main2_rmii_groups[] = {
+	"gpio_80", "gpio_81", "gpio_82", "gpio_83", "gpio_84", "gpio_87", "gpio_88",
+	"gpio_89"
+};
+
+#define RTD1625_FUNC(_group, _name) \
+	{ \
+		.name = # _name, \
+		.groups = rtd1625_ ## _group ## _ ## _name ## _groups, \
+		.num_groups = ARRAY_SIZE(rtd1625_ ## _group ## _ ## _name ## _groups), \
+	}
+
+static const struct rtd_pin_func_desc rtd1625_iso_pin_functions[] = {
+	RTD1625_FUNC(iso, gpio),
+	RTD1625_FUNC(iso, uart1),
+	RTD1625_FUNC(iso, iso_tristate),
+	RTD1625_FUNC(iso, usb_cc1),
+	RTD1625_FUNC(iso, usb_cc2),
+	RTD1625_FUNC(iso, sdio),
+	RTD1625_FUNC(iso, scpu_ejtag_loc2),
+	RTD1625_FUNC(iso, acpu_ejtag_loc2),
+	RTD1625_FUNC(iso, pcpu_ejtag_loc2),
+	RTD1625_FUNC(iso, aucpu0_ejtag_loc2),
+	RTD1625_FUNC(iso, ve2_ejtag_loc2),
+	RTD1625_FUNC(iso, aucpu1_ejtag_loc2),
+	RTD1625_FUNC(iso, pwm4),
+	RTD1625_FUNC(iso, uart7),
+	RTD1625_FUNC(iso, pwm2_loc1),
+	RTD1625_FUNC(iso, uart8),
+	RTD1625_FUNC(iso, pwm3_loc1),
+	RTD1625_FUNC(iso, ai_tdm0),
+	RTD1625_FUNC(iso, vtc_i2s),
+	RTD1625_FUNC(iso, ai_i2s0),
+	RTD1625_FUNC(iso, ao_tdm0),
+	RTD1625_FUNC(iso, ao_i2s0),
+	RTD1625_FUNC(iso, ai_tdm1),
+	RTD1625_FUNC(iso, ai_i2s1_loc0),
+	RTD1625_FUNC(iso, ao_i2s0_loc1),
+	RTD1625_FUNC(iso, ao_tdm1_loc0),
+	RTD1625_FUNC(iso, ao_i2s1_loc0),
+	RTD1625_FUNC(iso, ao_tdm1),
+	RTD1625_FUNC(iso, ai_tdm2),
+	RTD1625_FUNC(iso, pcm),
+	RTD1625_FUNC(iso, ai_i2s2),
+	RTD1625_FUNC(iso, ao_tdm2),
+	RTD1625_FUNC(iso, ao_i2s2),
+	RTD1625_FUNC(iso, vtc_ao_i2s),
+	RTD1625_FUNC(iso, scpu_ejtag_loc0),
+	RTD1625_FUNC(iso, acpu_ejtag_loc0),
+	RTD1625_FUNC(iso, pcpu_ejtag_loc0),
+	RTD1625_FUNC(iso, aucpu0_ejtag_loc0),
+	RTD1625_FUNC(iso, ve2_ejtag_loc0),
+	RTD1625_FUNC(iso, gpu_ejtag_loc0),
+	RTD1625_FUNC(iso, ao_tdm1_loc1),
+	RTD1625_FUNC(iso, aucpu1_ejtag_loc0),
+	RTD1625_FUNC(iso, edptx_hdp),
+	RTD1625_FUNC(iso, pwm5),
+	RTD1625_FUNC(iso, vi0_dtv),
+	RTD1625_FUNC(iso, vi1_dtv),
+	RTD1625_FUNC(iso, ao_i2s0_loc0),
+	RTD1625_FUNC(iso, dmic0),
+	RTD1625_FUNC(iso, vtc_dmic),
+	RTD1625_FUNC(iso, ai_i2s1_loc1),
+	RTD1625_FUNC(iso, ao_i2s1_loc1),
+	RTD1625_FUNC(iso, dmic1),
+	RTD1625_FUNC(iso, dmic2),
+	RTD1625_FUNC(iso, pwm0_loc2),
+	RTD1625_FUNC(iso, spdif_in_coaxial),
+	RTD1625_FUNC(iso, spdif_in_gpio),
+	RTD1625_FUNC(iso, hi_width_disable),
+	RTD1625_FUNC(iso, hi_width_1bit),
+	RTD1625_FUNC(iso, sf_disable),
+	RTD1625_FUNC(iso, sf_enable),
+	RTD1625_FUNC(iso, arm_trace_debug_disable),
+	RTD1625_FUNC(iso, arm_trace_debug_enable),
+	RTD1625_FUNC(iso, aucpu0_ejtag_loc1),
+	RTD1625_FUNC(iso, aucpu1_ejtag_loc1),
+	RTD1625_FUNC(iso, ve2_ejtag_loc1),
+	RTD1625_FUNC(iso, scpu_ejtag_loc1),
+	RTD1625_FUNC(iso, pcpu_ejtag_loc1),
+	RTD1625_FUNC(iso, acpu_ejtag_loc1),
+	RTD1625_FUNC(iso, i2c6_loc0),
+	RTD1625_FUNC(iso, i2c6_loc1),
+	RTD1625_FUNC(iso, uart0_loc0),
+	RTD1625_FUNC(iso, uart0_loc1),
+	RTD1625_FUNC(iso, etn_phy_loc0),
+	RTD1625_FUNC(iso, etn_phy_loc1),
+	RTD1625_FUNC(iso, spdif_loc0),
+	RTD1625_FUNC(iso, spdif_loc1),
+	RTD1625_FUNC(iso, rgmii_1v2),
+	RTD1625_FUNC(iso, rgmii_1v8),
+	RTD1625_FUNC(iso, rgmii_2v5),
+	RTD1625_FUNC(iso, rgmii_3v3),
+	RTD1625_FUNC(iso, csi_1v2),
+	RTD1625_FUNC(iso, csi_1v8),
+	RTD1625_FUNC(iso, csi_2v5),
+	RTD1625_FUNC(iso, csi_3v3),
+};
+
+static const struct rtd_pin_func_desc rtd1625_isom_pin_functions[] = {
+	RTD1625_FUNC(isom, gpio),
+	RTD1625_FUNC(isom, pctrl),
+	RTD1625_FUNC(isom, iso_tristate),
+	RTD1625_FUNC(isom, ir_rx_loc1),
+	RTD1625_FUNC(isom, uart10),
+	RTD1625_FUNC(isom, isom_dbg_out),
+	RTD1625_FUNC(isom, ir_rx_loc0),
+};
+
+static const struct rtd_pin_func_desc rtd1625_ve4_pin_functions[] = {
+	RTD1625_FUNC(ve4, gpio),
+	RTD1625_FUNC(ve4, uart0_loc0),
+	RTD1625_FUNC(ve4, iso_tristate),
+	RTD1625_FUNC(ve4, uart2),
+	RTD1625_FUNC(ve4, gspi0),
+	RTD1625_FUNC(ve4, scpu_ejtag_loc0),
+	RTD1625_FUNC(ve4, acpu_ejtag_loc0),
+	RTD1625_FUNC(ve4, pcpu_ejtag_loc0),
+	RTD1625_FUNC(ve4, aucpu0_ejtag_loc0),
+	RTD1625_FUNC(ve4, ve2_ejtag_loc0),
+	RTD1625_FUNC(ve4, gpu_ejtag_loc0),
+	RTD1625_FUNC(ve4, aucpu1_ejtag_loc0),
+	RTD1625_FUNC(ve4, pwm0_loc1),
+	RTD1625_FUNC(ve4, pwm1_loc0),
+	RTD1625_FUNC(ve4, i2c0),
+	RTD1625_FUNC(ve4, pwm0_loc3),
+	RTD1625_FUNC(ve4, dptx_hpd),
+	RTD1625_FUNC(ve4, pwm2_loc0),
+	RTD1625_FUNC(ve4, pcie0),
+	RTD1625_FUNC(ve4, pwm3_loc0),
+	RTD1625_FUNC(ve4, i2c3),
+	RTD1625_FUNC(ve4, pcie1),
+	RTD1625_FUNC(ve4, uart9),
+	RTD1625_FUNC(ve4, ve4_uart_loc2),
+	RTD1625_FUNC(ve4, sd),
+	RTD1625_FUNC(ve4, i2c6_loc1),
+	RTD1625_FUNC(ve4, uart3),
+	RTD1625_FUNC(ve4, ts0),
+	RTD1625_FUNC(ve4, gspi2),
+	RTD1625_FUNC(ve4, ve4_uart_loc0),
+	RTD1625_FUNC(ve4, uart5),
+	RTD1625_FUNC(ve4, uart0_loc1),
+	RTD1625_FUNC(ve4, gspi1),
+	RTD1625_FUNC(ve4, uart4),
+	RTD1625_FUNC(ve4, i2c4),
+	RTD1625_FUNC(ve4, spdif_out),
+	RTD1625_FUNC(ve4, spdif_in_optical),
+	RTD1625_FUNC(ve4, pll_test_loc0),
+	RTD1625_FUNC(ve4, uart6),
+	RTD1625_FUNC(ve4, i2c7),
+	RTD1625_FUNC(ve4, ve4_uart_loc1),
+	RTD1625_FUNC(ve4, pwm1_loc1),
+	RTD1625_FUNC(ve4, pwm6),
+	RTD1625_FUNC(ve4, ts1),
+	RTD1625_FUNC(ve4, pwm0_loc0),
+	RTD1625_FUNC(ve4, i2c6_loc0),
+	RTD1625_FUNC(ve4, csi0),
+	RTD1625_FUNC(ve4, csi1),
+	RTD1625_FUNC(ve4, etn_led_loc1),
+	RTD1625_FUNC(ve4, etn_phy_loc1),
+	RTD1625_FUNC(ve4, i2c5),
+};
+
+static const struct rtd_pin_func_desc rtd1625_main2_pin_functions[] = {
+	RTD1625_FUNC(main2, gpio),
+	RTD1625_FUNC(main2, emmc),
+	RTD1625_FUNC(main2, iso_tristate),
+	RTD1625_FUNC(main2, nf),
+	RTD1625_FUNC(main2, etn_led_loc0),
+	RTD1625_FUNC(main2, etn_phy_loc0),
+	RTD1625_FUNC(main2, rgmii),
+	RTD1625_FUNC(main2, i2c1),
+	RTD1625_FUNC(main2, dbg_out1),
+	RTD1625_FUNC(main2, sd),
+	RTD1625_FUNC(main2, scpu_ejtag_loc1),
+	RTD1625_FUNC(main2, acpu_ejtag_loc1),
+	RTD1625_FUNC(main2, pcpu_ejtag_loc1),
+	RTD1625_FUNC(main2, aupu0_ejtag_loc1),
+	RTD1625_FUNC(main2, ve2_ejtag_loc1),
+	RTD1625_FUNC(main2, hi_loc0),
+	RTD1625_FUNC(main2, hi_m),
+	RTD1625_FUNC(main2, aupu1_ejtag_loc1),
+	RTD1625_FUNC(main2, spi),
+	RTD1625_FUNC(main2, pll_test_loc1),
+	RTD1625_FUNC(main2, rmii),
+};
+
+#undef RTD1625_FUNC
+
+static const struct rtd_pin_desc rtd1625_iso_muxes[] = {
+	[RTD1625_ISO_GPIO_8] = RTK_PIN_MUX(gpio_8, 0x0, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_9] = RTK_PIN_MUX(gpio_9, 0x0, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_10] = RTK_PIN_MUX(gpio_10, 0x0, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_11] = RTK_PIN_MUX(gpio_11, 0x0, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_ISO_USB_CC1] = RTK_PIN_MUX(usb_cc1, 0x0, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "usb_cc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_ISO_USB_CC2] = RTK_PIN_MUX(usb_cc2, 0x0, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "usb_cc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_45] = RTK_PIN_MUX(gpio_45, 0x0, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "pcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 24), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 24), "ve2_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "aucpu1_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_46] = RTK_PIN_MUX(gpio_46, 0x0, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 28), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 28), "pcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 28), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 28), "ve2_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 28), "aucpu1_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_ISO_GPIO_47] = RTK_PIN_MUX(gpio_47, 0x4, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "pcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "ve2_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "aucpu1_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_48] = RTK_PIN_MUX(gpio_48, 0x4, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "pcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "ve2_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "aucpu1_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_49] = RTK_PIN_MUX(gpio_49, 0x4, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aucpu0_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aucpu1_ejtag_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_50] = RTK_PIN_MUX(gpio_50, 0x4, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sdio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_52] = RTK_PIN_MUX(gpio_52, 0x4, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_94] = RTK_PIN_MUX(gpio_94, 0x4, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart7"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_95] = RTK_PIN_MUX(gpio_95, 0x4, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart7"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "pwm2_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_96] = RTK_PIN_MUX(gpio_96, 0x4, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart8"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_ISO_GPIO_97] = RTK_PIN_MUX(gpio_97, 0x8, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart8"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 0), "pwm3_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_98] = RTK_PIN_MUX(gpio_98, 0x8, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_tdm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "vtc_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_99] = RTK_PIN_MUX(gpio_99, 0x8, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ao_tdm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_100] = RTK_PIN_MUX(gpio_100, 0x8, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ai_tdm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ao_tdm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "vtc_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 12), "ai_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "ao_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_101] = RTK_PIN_MUX(gpio_101, 0x8, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "ai_tdm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ao_tdm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "vtc_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 16), "ai_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_102] = RTK_PIN_MUX(gpio_102, 0x8, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_tdm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao_tdm0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "vtc_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "ao_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_103] = RTK_PIN_MUX(gpio_103, 0x8, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_tdm1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "ai_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s0_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_104] = RTK_PIN_MUX(gpio_104, 0x8, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "ao_tdm1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "ao_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_ISO_GPIO_105] = RTK_PIN_MUX(gpio_105, 0xc, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_tdm1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao_tdm1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "ai_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_106] = RTK_PIN_MUX(gpio_106, 0xc, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_tdm1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ao_tdm1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "ai_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "ao_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_107] = RTK_PIN_MUX(gpio_107, 0xc, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "ai_tdm1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ao_tdm1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "ai_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xb, 8), "ao_i2s0_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_108] = RTK_PIN_MUX(gpio_108, 0xc, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "ai_tdm2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "pcm"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "ai_i2s2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_109] = RTK_PIN_MUX(gpio_109, 0xc, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ao_tdm2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "pcm"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "vtc_ao_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_110] = RTK_PIN_MUX(gpio_110, 0xc, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ai_tdm2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ao_tdm2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "pcm"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "ai_i2s2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 20), "ao_i2s2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "vtc_ao_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_111] = RTK_PIN_MUX(gpio_111, 0xc, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "ai_tdm2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "ao_tdm2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "pcm"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 24), "ai_i2s2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 24), "vtc_ao_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+
+	[RTD1625_ISO_GPIO_112] = RTK_PIN_MUX(gpio_112, 0x10, GENMASK(4, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ai_tdm2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ao_tdm2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 0), "pcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 0), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 0), "ve2_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 0), "ai_i2s2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 0), "gpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 0), "vtc_ao_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x10, 0), "ao_tdm1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x11, 0), "aucpu1_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x13, 0), "ao_i2s0")
+	),
+	[RTD1625_ISO_GPIO_128] = RTK_PIN_MUX(gpio_128, 0x10, GENMASK(8, 5),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 5), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 5), "edptx_hdp"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 5), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_129] = RTK_PIN_MUX(gpio_129, 0x10, GENMASK(12, 9),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 9), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 9), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_130] = RTK_PIN_MUX(gpio_130, 0x10, GENMASK(16, 13),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 13), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 13), "pwm5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 13), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_131] = RTK_PIN_MUX(gpio_131, 0x10, GENMASK(20, 17),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 17), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 17), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_145] = RTK_PIN_MUX(gpio_145, 0x10, GENMASK(24, 21),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 21), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_146] = RTK_PIN_MUX(gpio_146, 0x10, GENMASK(28, 25),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 25), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 25), "iso_tristate")
+	),
+
+	[RTD1625_ISO_GPIO_147] = RTK_PIN_MUX(gpio_147, 0x14, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_148] = RTK_PIN_MUX(gpio_148, 0x14, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_149] = RTK_PIN_MUX(gpio_149, 0x14, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_150] = RTK_PIN_MUX(gpio_150, 0x14, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_151] = RTK_PIN_MUX(gpio_151, 0x14, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_152] = RTK_PIN_MUX(gpio_152, 0x14, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_153] = RTK_PIN_MUX(gpio_153, 0x14, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_154] = RTK_PIN_MUX(gpio_154, 0x14, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 28), "ao_i2s0_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_ISO_GPIO_155] = RTK_PIN_MUX(gpio_155, 0x18, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 0), "ao_i2s0_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_156] = RTK_PIN_MUX(gpio_156, 0x18, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "dmic0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "vtc_dmic"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 4), "ai_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_157] = RTK_PIN_MUX(gpio_157, 0x18, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "dmic0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "vtc_dmic"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "ai_i2s1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "ao_i2s1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_158] = RTK_PIN_MUX(gpio_158, 0x18, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "dmic1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "vtc_dmic"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "ai_i2s1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "ao_i2s1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_159] = RTK_PIN_MUX(gpio_159, 0x18, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "dmic1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "vtc_dmic"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "ai_i2s1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "ao_i2s1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_160] = RTK_PIN_MUX(gpio_160, 0x18, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "dmic2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 20), "ai_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 20), "ai_i2s1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_161] = RTK_PIN_MUX(gpio_161, 0x18, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "vi0_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "dmic2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 24), "vtc_i2s"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x8, 24), "ai_i2s0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 24), "ao_i2s1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_ISO_GPIO_162] = RTK_PIN_MUX(gpio_162, 0x18, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "vi1_dtv"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "pwm0_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_ISO_GPIO_163] = RTK_PIN_MUX(gpio_163, 0x1c, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "spdif_in_coaxial"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+
+	[RTD1625_ISO_HI_WIDTH] = RTK_PIN_MUX(hi_width, 0x120, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "hi_width_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "hi_width_1bit")
+	),
+	[RTD1625_ISO_SF_EN] = RTK_PIN_MUX(sf_en, 0x120, GENMASK(11, 11),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 11), "sf_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 11), "sf_enable")
+	),
+	[RTD1625_ISO_ARM_TRACE_DBG_EN] = RTK_PIN_MUX(arm_trace_dbg_en, 0x120, GENMASK(13, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "arm_trace_debug_disable"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "arm_trace_debug_enable")
+	),
+	[RTD1625_ISO_EJTAG_AUCPU0_LOC] = RTK_PIN_MUX(ejtag_aucpu0_loc, 0x120, GENMASK(16, 14),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 14), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 14), "aucpu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 14), "aucpu0_ejtag_loc2")
+	),
+	[RTD1625_ISO_EJTAG_AUCPU1_LOC] = RTK_PIN_MUX(ejtag_aucpu1_loc, 0x120, GENMASK(19, 17),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 17), "aucpu1_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 17), "aucpu1_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 17), "aucpu1_ejtag_loc2")
+	),
+	[RTD1625_ISO_EJTAG_VE2_LOC] = RTK_PIN_MUX(ejtag_ve2_loc, 0x120, GENMASK(22, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "ve2_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ve2_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ve2_ejtag_loc2")
+	),
+	[RTD1625_ISO_EJTAG_SCPU_LOC] = RTK_PIN_MUX(ejtag_scpu_loc, 0x120, GENMASK(25, 23),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 23), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 23), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 23), "scpu_ejtag_loc2")
+	),
+	[RTD1625_ISO_EJTAG_PCPU_LOC] = RTK_PIN_MUX(ejtag_pcpu_loc, 0x120, GENMASK(28, 26),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 26), "pcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 26), "pcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 26), "pcpu_ejtag_loc2")
+	),
+	[RTD1625_ISO_EJTAG_ACPU_LOC] = RTK_PIN_MUX(ejtag_acpu_loc, 0x120, GENMASK(31, 29),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 29), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 29), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 29), "acpu_ejtag_loc2")
+	),
+	[RTD1625_ISO_I2C6_LOC] = RTK_PIN_MUX(i2c6_loc, 0x128, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "i2c6_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c6_loc1")
+	),
+	[RTD1625_ISO_UART0_LOC] = RTK_PIN_MUX(uart0_loc, 0x128, GENMASK(3, 2),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 2), "uart0_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 2), "uart0_loc1")
+	),
+	[RTD1625_ISO_AI_I2S1_LOC] = RTK_PIN_MUX(ai_i2s1_loc, 0x128, GENMASK(5, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "ai_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ai_i2s1_loc1")
+	),
+	[RTD1625_ISO_AO_I2S1_LOC] = RTK_PIN_MUX(ao_i2s1_loc, 0x128, GENMASK(7, 6),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 6), "ao_i2s1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 6), "ao_i2s1_loc1")
+	),
+	[RTD1625_ISO_ETN_PHY_LOC] = RTK_PIN_MUX(etn_phy_loc, 0x128, GENMASK(9, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "etn_phy_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "etn_phy_loc1")
+	),
+	[RTD1625_ISO_SPDIF_LOC] = RTK_PIN_MUX(spdif_loc, 0x128, GENMASK(14, 13),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 13), "spdif_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 13), "spdif_loc1")
+	),
+	[RTD1625_ISO_RGMII_VDSEL] = RTK_PIN_MUX(rgmii_vdsel, 0x188, GENMASK(17, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "rgmii_3v3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "rgmii_2v5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rgmii_1v8"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii_1v2")
+	),
+	[RTD1625_ISO_CSI_VDSEL] = RTK_PIN_MUX(csi_vdsel, 0x188, GENMASK(19, 18),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 18), "csi_3v3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 18), "csi_2v5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 18), "csi_1v8"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 18), "csi_1v2")
+	),
+
+	[RTD1625_ISO_SPDIF_IN_MODE] = RTK_PIN_MUX(spdif_in_mode, 0x188, GENMASK(20, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "spdif_in_gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "spdif_in_coaxial")
+	),
+};
+
+static const struct rtd_pin_desc rtd1625_isom_muxes[] = {
+	[RTD1625_ISOM_GPIO_0] = RTK_PIN_MUX(gpio_0, 0x0, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "pctrl"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_ISOM_GPIO_1] = RTK_PIN_MUX(gpio_1, 0x0, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "pctrl"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "ir_rx_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_ISOM_GPIO_28] = RTK_PIN_MUX(gpio_28, 0x0, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart10"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "pctrl"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "isom_dbg_out"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_ISOM_GPIO_29] = RTK_PIN_MUX(gpio_29, 0x0, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart10"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pctrl"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "ir_rx_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "isom_dbg_out"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_ISOM_IR_RX_LOC] = RTK_PIN_MUX(ir_rx_loc, 0x30, GENMASK(1, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ir_rx_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ir_rx_loc1")
+	),
+};
+
+static const struct rtd_pin_desc rtd1625_ve4_muxes[] = {
+	[RTD1625_VE4_GPIO_2] = RTK_PIN_MUX(gpio_2, 0x0, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "uart0_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_3] = RTK_PIN_MUX(gpio_3, 0x0, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "uart0_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_4] = RTK_PIN_MUX(gpio_4, 0x0, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "gspi0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 8), "gpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aucpu1_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_5] = RTK_PIN_MUX(gpio_5, 0x0, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "gspi0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "pcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "ve2_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 12), "gpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "aucpu1_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_6] = RTK_PIN_MUX(gpio_6, 0x0, GENMASK(20, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "gspi0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "pcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "ve2_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 16), "gpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm0_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "aucpu1_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_7] = RTK_PIN_MUX(gpio_7, 0x0, GENMASK(24, 21),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 21), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 21), "uart2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 21), "gspi0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 21), "scpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 21), "acpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 21), "pcpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 21), "aucpu0_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 21), "ve2_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xc, 21), "gpu_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 21), "pwm1_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 21), "aucpu1_ejtag_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 21), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_12] = RTK_PIN_MUX(gpio_12, 0x0, GENMASK(28, 25),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 25), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 25), "i2c0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 25), "pwm0_loc3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 25), "iso_tristate")
+	),
+
+	[RTD1625_VE4_GPIO_13] = RTK_PIN_MUX(gpio_13, 0x4, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_16] = RTK_PIN_MUX(gpio_16, 0x4, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "dptx_hpd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 4), "pwm2_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_17] = RTK_PIN_MUX(gpio_17, 0x4, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_18] = RTK_PIN_MUX(gpio_18, 0x4, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "pcie0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_19] = RTK_PIN_MUX(gpio_19, 0x4, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 16), "pwm3_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_23] = RTK_PIN_MUX(gpio_23, 0x4, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_24] = RTK_PIN_MUX(gpio_24, 0x4, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_25] = RTK_PIN_MUX(gpio_25, 0x4, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "i2c3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_VE4_GPIO_30] = RTK_PIN_MUX(gpio_30, 0x8, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pcie1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_31] = RTK_PIN_MUX(gpio_31, 0x8, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_32] = RTK_PIN_MUX(gpio_32, 0x8, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart9"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ve4_uart_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_33] = RTK_PIN_MUX(gpio_33, 0x8, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart9"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "ve4_uart_loc2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_34] = RTK_PIN_MUX(gpio_34, 0x8, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_35] = RTK_PIN_MUX(gpio_35, 0x8, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_42] = RTK_PIN_MUX(gpio_42, 0x8, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_43] = RTK_PIN_MUX(gpio_43, 0x8, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_VE4_GPIO_44] = RTK_PIN_MUX(gpio_44, 0xc, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_51] = RTK_PIN_MUX(gpio_51, 0xc, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "i2c6_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_53] = RTK_PIN_MUX(gpio_53, 0xc, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "uart3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ts0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "gspi2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "ve4_uart_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_54] = RTK_PIN_MUX(gpio_54, 0xc, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "uart3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ts0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "gspi2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "ve4_uart_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_55] = RTK_PIN_MUX(gpio_55, 0xc, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "uart3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "ts0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "gspi2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_56] = RTK_PIN_MUX(gpio_56, 0xc, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart3"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "ts0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "gspi2"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_57] = RTK_PIN_MUX(gpio_57, 0xc, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "uart0_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "gspi1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_58] = RTK_PIN_MUX(gpio_58, 0xc, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 28), "uart5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "uart0_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "gspi1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_VE4_GPIO_59] = RTK_PIN_MUX(gpio_59, 0x10, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "uart4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "i2c4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "gspi1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_60] = RTK_PIN_MUX(gpio_60, 0x10, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "uart4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "i2c4"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "gspi1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_61] = RTK_PIN_MUX(gpio_61, 0x10, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "i2c6_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "spdif_out"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "spdif_in_optical"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_62] = RTK_PIN_MUX(gpio_62, 0x10, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "pll_test_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_63] = RTK_PIN_MUX(gpio_63, 0x10, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "pll_test_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_92] = RTK_PIN_MUX(gpio_92, 0x10, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "uart6"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "i2c7"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "ve4_uart_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_93] = RTK_PIN_MUX(gpio_93, 0x10, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "uart6"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c7"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 24), "ve4_uart_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 24), "pwm1_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_132] = RTK_PIN_MUX(gpio_132, 0x10, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 28), "pwm6"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_VE4_GPIO_133] = RTK_PIN_MUX(gpio_133, 0x14, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ts1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_134] = RTK_PIN_MUX(gpio_134, 0x14, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "ts1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_135] = RTK_PIN_MUX(gpio_135, 0x14, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "ts1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_136] = RTK_PIN_MUX(gpio_136, 0x14, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "ts1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xd, 12), "pwm0_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_137] = RTK_PIN_MUX(gpio_137, 0x14, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "i2c6_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_138] = RTK_PIN_MUX(gpio_138, 0x14, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "i2c6_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_139] = RTK_PIN_MUX(gpio_139, 0x14, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_140] = RTK_PIN_MUX(gpio_140, 0x14, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_VE4_GPIO_141] = RTK_PIN_MUX(gpio_141, 0x18, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "csi0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_142] = RTK_PIN_MUX(gpio_142, 0x18, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_143] = RTK_PIN_MUX(gpio_143, 0x18, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_144] = RTK_PIN_MUX(gpio_144, 0x18, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "csi1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_164] = RTK_PIN_MUX(gpio_164, 0x18, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "etn_led_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "etn_phy_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "i2c5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_VE4_GPIO_165] = RTK_PIN_MUX(gpio_165, 0x18, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "etn_led_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "etn_phy_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "i2c5"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_VE4_UART_LOC] = RTK_PIN_MUX(ve4_uart_loc, 0x80, GENMASK(2, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "ve4_uart_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "ve4_uart_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 0), "ve4_uart_loc2")
+	),
+};
+
+static const struct rtd_pin_desc rtd1625_main2_muxes[] = {
+	[RTD1625_MAIN2_EMMC_RST_N] = RTK_PIN_MUX(emmc_rst_n, 0x0, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_DD_SB] = RTK_PIN_MUX(emmc_dd_sb, 0x0, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_CLK] = RTK_PIN_MUX(emmc_clk, 0x0, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_CMD] = RTK_PIN_MUX(emmc_cmd, 0x0, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_DATA_0] = RTK_PIN_MUX(emmc_data_0, 0x0, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_DATA_1] = RTK_PIN_MUX(emmc_data_1, 0x0, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_DATA_2] = RTK_PIN_MUX(emmc_data_2, 0x0, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_DATA_3] = RTK_PIN_MUX(emmc_data_3, 0x0, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_MAIN2_EMMC_DATA_4] = RTK_PIN_MUX(emmc_data_4, 0x4, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_DATA_5] = RTK_PIN_MUX(emmc_data_5, 0x4, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "nf"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_DATA_6] = RTK_PIN_MUX(emmc_data_6, 0x4, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_MAIN2_EMMC_DATA_7] = RTK_PIN_MUX(emmc_data_7, 0x4, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "emmc"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_14] = RTK_PIN_MUX(gpio_14, 0x4, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "etn_led_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "etn_phy_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_15] = RTK_PIN_MUX(gpio_15, 0x4, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "etn_led_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "etn_phy_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_20] = RTK_PIN_MUX(gpio_20, 0x4, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "i2c1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_21] = RTK_PIN_MUX(gpio_21, 0x4, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "i2c1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_MAIN2_GPIO_22] = RTK_PIN_MUX(gpio_22, 0x8, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "dbg_out1")
+	),
+	[RTD1625_MAIN2_HIF_DATA] = RTK_PIN_MUX(hif_data, 0x8, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 4), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 4), "pcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 4), "aupu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 4), "ve2_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 4), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 4), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 4), "aupu1_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_MAIN2_HIF_EN] = RTK_PIN_MUX(hif_en, 0x8, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 8), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 8), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 8), "pcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 8), "aupu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 8), "ve2_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 8), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 8), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 8), "aupu1_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_MAIN2_HIF_RDY] = RTK_PIN_MUX(hif_rdy, 0x8, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 12), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 12), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 12), "pcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 12), "aupu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 12), "ve2_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 12), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 12), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 12), "aupu1_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_MAIN2_HIF_CLK] = RTK_PIN_MUX(hif_clk, 0x8, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 16), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 16), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 16), "pcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 16), "aupu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 16), "ve2_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x9, 16), "hi_loc0"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xa, 16), "hi_m"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 16), "aupu1_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_40] = RTK_PIN_MUX(gpio_40, 0x8, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 20), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "scpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x4, 20), "acpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x5, 20), "pcpu_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x6, 20), "aupu0_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x7, 20), "ve2_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xe, 20), "aupu1_ejtag_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_41] = RTK_PIN_MUX(gpio_41, 0x8, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 24), "sd"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_64] = RTK_PIN_MUX(gpio_64, 0x8, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_MAIN2_GPIO_65] = RTK_PIN_MUX(gpio_65, 0xc, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 0), "pll_test_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 0), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_66] = RTK_PIN_MUX(gpio_66, 0xc, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x1, 4), "pll_test_loc1"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 4), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_67] = RTK_PIN_MUX(gpio_67, 0xc, GENMASK(13, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "spi"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_80] = RTK_PIN_MUX(gpio_80, 0xc, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "rmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_81] = RTK_PIN_MUX(gpio_81, 0xc, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_82] = RTK_PIN_MUX(gpio_82, 0xc, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 20), "rmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_83] = RTK_PIN_MUX(gpio_83, 0xc, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 24), "rmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_84] = RTK_PIN_MUX(gpio_84, 0xc, GENMASK(31, 28),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 28), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 28), "rmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 28), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 28), "iso_tristate")
+	),
+
+	[RTD1625_MAIN2_GPIO_85] = RTK_PIN_MUX(gpio_85, 0x10, GENMASK(3, 0),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 0), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 0), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 0), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_86] = RTK_PIN_MUX(gpio_86, 0x10, GENMASK(7, 4),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 4), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 4), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 4), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_87] = RTK_PIN_MUX(gpio_87, 0x10, GENMASK(11, 8),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 8), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 8), "rmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 8), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 8), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_88] = RTK_PIN_MUX(gpio_88, 0x10, GENMASK(15, 12),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 12), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 12), "rmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 12), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 12), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_89] = RTK_PIN_MUX(gpio_89, 0x10, GENMASK(19, 16),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 16), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x2, 16), "rmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 16), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 16), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_90] = RTK_PIN_MUX(gpio_90, 0x10, GENMASK(23, 20),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 20), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 20), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 20), "iso_tristate")
+	),
+	[RTD1625_MAIN2_GPIO_91] = RTK_PIN_MUX(gpio_91, 0x10, GENMASK(27, 24),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x0, 24), "gpio"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0x3, 24), "rgmii"),
+		RTK_PIN_FUNC(SHIFT_LEFT(0xf, 24), "iso_tristate")
+	),
+};
+
+static const struct rtd_pin_config_desc rtd1625_iso_configs[] = {
+	[RTD1625_ISO_GPIO_8] = RTK_PIN_CONFIG_V2(gpio_8, 0x20, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISO_GPIO_9] = RTK_PIN_CONFIG_V2(gpio_9, 0x20, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISO_GPIO_10] = RTK_PIN_CONFIG_V2(gpio_10, 0x20, 12, 1, 2, 0, 3, 4, 5,
+						  PADDRI_4_8),
+	[RTD1625_ISO_GPIO_11] = RTK_PIN_CONFIG_V2(gpio_11, 0x20, 18, 1, 2, 0, 3, 4, 5,
+						  PADDRI_4_8),
+	[RTD1625_ISO_GPIO_45] = RTK_PIN_CONFIG(gpio_45, 0x24, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_ISO_GPIO_46] = RTK_PIN_CONFIG(gpio_46, 0x24, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_ISO_GPIO_47] = RTK_PIN_CONFIG(gpio_47, 0x28, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_ISO_GPIO_48] = RTK_PIN_CONFIG(gpio_48, 0x28, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_ISO_GPIO_49] = RTK_PIN_CONFIG(gpio_49, 0x2c, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_ISO_GPIO_50] = RTK_PIN_CONFIG(gpio_50, 0x2c, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_ISO_GPIO_52] = RTK_PIN_CONFIG_V2(gpio_52, 0x2c, 26, 1, 2, 0, 3, 4, 5,
+						  PADDRI_4_8),
+	[RTD1625_ISO_GPIO_94] = RTK_PIN_CONFIG_V2(gpio_94, 0x30, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISO_GPIO_95] = RTK_PIN_CONFIG_V2(gpio_95, 0x30, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISO_GPIO_96] = RTK_PIN_CONFIG_V2(gpio_96, 0x30, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISO_GPIO_97] = RTK_PIN_CONFIG_V2(gpio_97, 0x30, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISO_GPIO_98] = RTK_PIN_CONFIG_V2(gpio_98, 0x30, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISO_GPIO_99] = RTK_PIN_CONFIG_V2(gpio_99, 0x34, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISO_GPIO_100] = RTK_PIN_CONFIG_V2(gpio_100, 0x34, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_101] = RTK_PIN_CONFIG_V2(gpio_101, 0x34, 12, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_102] = RTK_PIN_CONFIG_V2(gpio_102, 0x34, 18, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_103] = RTK_PIN_CONFIG_V2(gpio_103, 0x34, 24, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_104] = RTK_PIN_CONFIG_V2(gpio_104, 0x38, 0, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_105] = RTK_PIN_CONFIG_V2(gpio_105, 0x38, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_106] = RTK_PIN_CONFIG_V2(gpio_106, 0x38, 12, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_107] = RTK_PIN_CONFIG_V2(gpio_107, 0x38, 18, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_108] = RTK_PIN_CONFIG_V2(gpio_108, 0x38, 24, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_109] = RTK_PIN_CONFIG_V2(gpio_109, 0x3c, 0, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_110] = RTK_PIN_CONFIG_V2(gpio_110, 0x3c, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_111] = RTK_PIN_CONFIG_V2(gpio_111, 0x3c, 12, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_112] = RTK_PIN_CONFIG_V2(gpio_112, 0x3c, 18, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_128] = RTK_PIN_CONFIG_V2(gpio_128, 0x3c, 24, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_129] = RTK_PIN_CONFIG_V2(gpio_129, 0x40, 0, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_130] = RTK_PIN_CONFIG_V2(gpio_130, 0x40, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_131] = RTK_PIN_CONFIG_V2(gpio_131, 0x40, 12, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_145] = RTK_PIN_CONFIG_V2(gpio_145, 0x40, 18, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_146] = RTK_PIN_CONFIG_V2(gpio_146, 0x40, 24, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_147] = RTK_PIN_CONFIG_V2(gpio_147, 0x44, 0, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_148] = RTK_PIN_CONFIG_V2(gpio_148, 0x44, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_149] = RTK_PIN_CONFIG_V2(gpio_149, 0x44, 12, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_150] = RTK_PIN_CONFIG_V2(gpio_150, 0x44, 18, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_151] = RTK_PIN_CONFIG_V2(gpio_151, 0x44, 24, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_152] = RTK_PIN_CONFIG_V2(gpio_152, 0x48, 0, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_153] = RTK_PIN_CONFIG_V2(gpio_153, 0x48, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_154] = RTK_PIN_CONFIG_V2(gpio_154, 0x48, 12, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_155] = RTK_PIN_CONFIG_V2(gpio_155, 0x48, 18, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_156] = RTK_PIN_CONFIG_V2(gpio_156, 0x48, 24, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_157] = RTK_PIN_CONFIG_V2(gpio_157, 0x4c, 0, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_158] = RTK_PIN_CONFIG_V2(gpio_158, 0x4c, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_159] = RTK_PIN_CONFIG_V2(gpio_159, 0x4c, 12, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_160] = RTK_PIN_CONFIG_V2(gpio_160, 0x4c, 18, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_161] = RTK_PIN_CONFIG_V2(gpio_161, 0x4c, 24, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_162] = RTK_PIN_CONFIG_V2(gpio_162, 0x50, 0, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_GPIO_163] = RTK_PIN_CONFIG_V2(gpio_163, 0x50, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_ISO_USB_CC1] = RTK_PIN_CONFIG_V2(usb_cc1, 0x50, 12, NA, NA, 0, 1, 2, 3,
+						  PADDRI_4_8),
+	[RTD1625_ISO_USB_CC2] = RTK_PIN_CONFIG_V2(usb_cc2, 0x50, 16, NA, NA, 0, 1, 2, 3,
+						  PADDRI_4_8),
+};
+
+static const struct rtd_pin_config_desc rtd1625_isom_configs[] = {
+	[RTD1625_ISOM_GPIO_0] = RTK_PIN_CONFIG_V2(gpio_0, 0x4, 5, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISOM_GPIO_1] = RTK_PIN_CONFIG_V2(gpio_1, 0x4, 11, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISOM_GPIO_28] = RTK_PIN_CONFIG_V2(gpio_28, 0x4, 17, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_ISOM_GPIO_29] = RTK_PIN_CONFIG_V2(gpio_29, 0x4, 23, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+};
+
+static const struct rtd_pin_config_desc rtd1625_ve4_configs[] = {
+	[RTD1625_VE4_GPIO_2] = RTK_PIN_CONFIG_V2(gpio_2, 0x1c, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_3] = RTK_PIN_CONFIG_V2(gpio_3, 0x1c, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_4] = RTK_PIN_CONFIG_V2(gpio_4, 0x1c, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_5] = RTK_PIN_CONFIG_V2(gpio_5, 0x1c, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_6] = RTK_PIN_CONFIG_V2(gpio_6, 0x1c, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_7] = RTK_PIN_CONFIG_V2(gpio_7, 0x20, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_12] = RTK_PIN_CONFIG_V2(gpio_12, 0x20, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_13] = RTK_PIN_CONFIG_V2(gpio_13, 0x20, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_16] = RTK_PIN_CONFIG_V2(gpio_16, 0x20, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_17] = RTK_PIN_CONFIG_V2(gpio_17, 0x20, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_18] = RTK_PIN_CONFIG_V2(gpio_18, 0x24, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_19] = RTK_PIN_CONFIG_V2(gpio_19, 0x24, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_23] = RTK_PIN_CONFIG_V2(gpio_23, 0x24, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_24] = RTK_PIN_CONFIG_V2(gpio_24, 0x24, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_25] = RTK_PIN_CONFIG_V2(gpio_25, 0x24, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_30] = RTK_PIN_CONFIG_V2(gpio_30, 0x28, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_31] = RTK_PIN_CONFIG_V2(gpio_31, 0x28, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_32] = RTK_PIN_CONFIG_V2(gpio_32, 0x28, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_33] = RTK_PIN_CONFIG_V2(gpio_33, 0x28, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_34] = RTK_PIN_CONFIG_V2(gpio_34, 0x28, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_35] = RTK_PIN_CONFIG_V2(gpio_35, 0x2c, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_42] = RTK_PIN_CONFIG_V2(gpio_42, 0x2c, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_43] = RTK_PIN_CONFIG_V2(gpio_43, 0x2c, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_44] = RTK_PIN_CONFIG_V2(gpio_44, 0x2c, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_51] = RTK_PIN_CONFIG_V2(gpio_51, 0x2c, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_53] = RTK_PIN_CONFIG_V2(gpio_53, 0x30, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_54] = RTK_PIN_CONFIG_V2(gpio_54, 0x30, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_55] = RTK_PIN_CONFIG_V2(gpio_55, 0x30, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_56] = RTK_PIN_CONFIG_V2(gpio_56, 0x30, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_57] = RTK_PIN_CONFIG_V2(gpio_57, 0x30, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_58] = RTK_PIN_CONFIG_V2(gpio_58, 0x34, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_59] = RTK_PIN_CONFIG_V2(gpio_59, 0x34, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_60] = RTK_PIN_CONFIG_V2(gpio_60, 0x34, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_61] = RTK_PIN_CONFIG_V2(gpio_61, 0x34, 18, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_62] = RTK_PIN_CONFIG_V2(gpio_62, 0x34, 24, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_63] = RTK_PIN_CONFIG_V2(gpio_63, 0x38, 0, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_92] = RTK_PIN_CONFIG_V2(gpio_92, 0x38, 6, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_93] = RTK_PIN_CONFIG_V2(gpio_93, 0x38, 12, 1, 2, 0, 3, 4, 5, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_132] = RTK_PIN_CONFIG_V2(gpio_132, 0x38, 18, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_VE4_GPIO_133] = RTK_PIN_CONFIG_V2(gpio_133, 0x38, 24, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_VE4_GPIO_134] = RTK_PIN_CONFIG_V2(gpio_134, 0x3c, 0, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_VE4_GPIO_135] = RTK_PIN_CONFIG_V2(gpio_135, 0x3c, 6, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_VE4_GPIO_136] = RTK_PIN_CONFIG_V2(gpio_136, 0x3c, 12, 1, 2, 0, 3, 4, 5,
+						   PADDRI_4_8),
+	[RTD1625_VE4_GPIO_137] = RTK_PIN_CONFIG(gpio_137, 0x3c, 18, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_138] = RTK_PIN_CONFIG(gpio_138, 0x3c, 21, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_139] = RTK_PIN_CONFIG(gpio_139, 0x3c, 24, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_140] = RTK_PIN_CONFIG(gpio_140, 0x3c, 27, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_141] = RTK_PIN_CONFIG(gpio_141, 0x40, 0, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_142] = RTK_PIN_CONFIG(gpio_142, 0x40, 3, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_143] = RTK_PIN_CONFIG(gpio_143, 0x40, 6, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_144] = RTK_PIN_CONFIG(gpio_144, 0x40, 9, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_164] = RTK_PIN_CONFIG(gpio_164, 0x40, 12, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_VE4_GPIO_165] = RTK_PIN_CONFIG(gpio_165, 0x40, 15, 1, 2, 0, NA, NA, PADDRI_4_8),
+};
+
+static const struct rtd_pin_config_desc rtd1625_main2_configs[] = {
+	[RTD1625_MAIN2_EMMC_CLK] = RTK_PIN_CONFIG(emmc_clk, 0x14, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_CMD] = RTK_PIN_CONFIG(emmc_cmd, 0x14, 13, 0, 1, NA, 2, 13, NA),
+	[RTD1625_MAIN2_EMMC_DATA_0] = RTK_PIN_CONFIG(emmc_data_0, 0x18, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_DATA_1] = RTK_PIN_CONFIG(emmc_data_1, 0x18, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_DATA_2] = RTK_PIN_CONFIG(emmc_data_2, 0x1c, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_DATA_3] = RTK_PIN_CONFIG(emmc_data_3, 0x1c, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_DATA_4] = RTK_PIN_CONFIG(emmc_data_4, 0x20, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_DATA_5] = RTK_PIN_CONFIG(emmc_data_5, 0x20, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_DATA_6] = RTK_PIN_CONFIG(emmc_data_6, 0x24, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_DATA_7] = RTK_PIN_CONFIG(emmc_data_7, 0x24, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_DD_SB] = RTK_PIN_CONFIG(emmc_dd_sb, 0x28, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_EMMC_RST_N] = RTK_PIN_CONFIG(emmc_rst_n, 0x28, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_GPIO_14] = RTK_PIN_CONFIG(gpio_14, 0x28, 26, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_15] = RTK_PIN_CONFIG(gpio_15, 0x28, 29, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_20] = RTK_PIN_CONFIG_I2C(gpio_20, 0x2c, 0, 1, 2, 0, 3, 4, 5, 7, 8,
+						     PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_21] = RTK_PIN_CONFIG_I2C(gpio_21, 0x2c, 9, 1, 2, 0, 3, 4, 5, 7, 8,
+						     PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_22] = RTK_PIN_CONFIG_V2(gpio_22, 0x2c, 18, 1, 2, 0, 3, 7, 8,
+						     PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_40] = RTK_PIN_CONFIG(gpio_40, 0x30, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_GPIO_41] = RTK_PIN_CONFIG(gpio_41, 0x30, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_GPIO_64] = RTK_PIN_CONFIG(gpio_64, 0x34, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_GPIO_65] = RTK_PIN_CONFIG(gpio_65, 0x34, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_GPIO_66] = RTK_PIN_CONFIG(gpio_66, 0x38, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_GPIO_67] = RTK_PIN_CONFIG(gpio_67, 0x38, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_GPIO_80] = RTK_PIN_CONFIG(gpio_80, 0x38, 26, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_81] = RTK_PIN_CONFIG(gpio_81, 0x38, 29, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_82] = RTK_PIN_CONFIG(gpio_82, 0x3c, 0, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_83] = RTK_PIN_CONFIG(gpio_83, 0x3c, 3, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_84] = RTK_PIN_CONFIG(gpio_84, 0x3c, 6, 1, 2, 0, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_85] = RTK_PIN_CONFIG(gpio_85, 0x3c, 9, 1, 2, NA, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_86] = RTK_PIN_CONFIG(gpio_86, 0x3c, 12, 1, 2, NA, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_87] = RTK_PIN_CONFIG(gpio_87, 0x3c, 22, 1, 2, NA, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_88] = RTK_PIN_CONFIG(gpio_88, 0x40, 0, 1, 2, NA, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_89] = RTK_PIN_CONFIG(gpio_89, 0x40, 10, 1, 2, NA, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_90] = RTK_PIN_CONFIG(gpio_90, 0x40, 20, 1, 2, NA, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_GPIO_91] = RTK_PIN_CONFIG(gpio_91, 0x44, 0, 1, 2, NA, NA, NA, PADDRI_4_8),
+	[RTD1625_MAIN2_HIF_CLK] = RTK_PIN_CONFIG(hif_clk, 0x44, 10, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_HIF_DATA] = RTK_PIN_CONFIG(hif_data, 0x48, 0, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_HIF_EN] = RTK_PIN_CONFIG(hif_en, 0x48, 13, 0, 1, NA, 2, 12, NA),
+	[RTD1625_MAIN2_HIF_RDY] = RTK_PIN_CONFIG(hif_rdy, 0x4c, 0, 0, 1, NA, 2, 12, NA),
+};
+
+static const struct rtd_pin_sconfig_desc rtd1625_iso_sconfigs[] = {
+	RTK_PIN_SCONFIG(gpio_45, 0x24, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_46, 0x24, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_47, 0x28, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_48, 0x28, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_49, 0x2c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_50, 0x2c, 16, 3, 19, 3, 22, 3),
+};
+
+static const struct rtd_pin_sconfig_desc rtd1625_main2_sconfigs[] = {
+	RTK_PIN_SCONFIG(emmc_clk, 0x14, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_cmd, 0x14, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_0, 0x18, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_1, 0x18, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_2, 0x1c, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_3, 0x1c, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_4, 0x20, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_5, 0x20, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_data_6, 0x24, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_data_7, 0x24, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(emmc_dd_sb, 0x28, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(emmc_rst_n, 0x28, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_40, 0x30, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_41, 0x30, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_64, 0x34, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_65, 0x34, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_66, 0x38, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(gpio_67, 0x38, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(gpio_86, 0x3c, 0, 0, 14, 4, 18, 4),
+	RTK_PIN_SCONFIG(gpio_87, 0x3c, 0, 0, 24, 4, 28, 4),
+	RTK_PIN_SCONFIG(gpio_88, 0x40, 0, 0, 2, 4, 6, 4),
+	RTK_PIN_SCONFIG(gpio_89, 0x40, 0, 0, 12, 4, 16, 4),
+	RTK_PIN_SCONFIG(gpio_90, 0x40, 0, 0, 22, 4, 26, 4),
+	RTK_PIN_SCONFIG(gpio_91, 0x44, 0, 0, 2, 4, 6, 4),
+	RTK_PIN_SCONFIG(hif_clk, 0x44, 13, 3, 16, 3, 19, 3),
+	RTK_PIN_SCONFIG(hif_data, 0x48, 3, 3, 6, 3, 9, 3),
+	RTK_PIN_SCONFIG(hif_en, 0x48, 16, 3, 19, 3, 22, 3),
+	RTK_PIN_SCONFIG(hif_rdy, 0x4c, 3, 3, 6, 3, 9, 3),
+};
+
+static const struct rtd_reg_range rtd1625_iso_reg_ranges[] = {
+	{ .offset = 0x0,  .len = 0x58 },
+	{ .offset = 0x120, .len = 0x10 },
+	{ .offset = 0x180, .len = 0xc },
+	{ .offset = 0x1A0, .len = 0xc },
+};
+
+static const struct rtd_pin_range rtd1625_iso_pin_ranges = {
+	.ranges = rtd1625_iso_reg_ranges,
+	.num_ranges = ARRAY_SIZE(rtd1625_iso_reg_ranges),
+};
+
+static const struct rtd_reg_range rtd1625_isom_reg_ranges[] = {
+	{ .offset = 0x0,  .len = 0xc },
+	{ .offset = 0x30, .len = 0x4 },
+};
+
+static const struct rtd_pin_range rtd1625_isom_pin_ranges = {
+	.ranges = rtd1625_isom_reg_ranges,
+	.num_ranges = ARRAY_SIZE(rtd1625_isom_reg_ranges),
+};
+
+static const struct rtd_reg_range rtd1625_ve4_reg_ranges[] = {
+	{ .offset = 0x0,  .len = 0x48 },
+	{ .offset = 0x80, .len = 0x4 },
+};
+
+static const struct rtd_pin_range rtd1625_ve4_pin_ranges = {
+	.ranges = rtd1625_ve4_reg_ranges,
+	.num_ranges = ARRAY_SIZE(rtd1625_ve4_reg_ranges),
+};
+
+static const struct rtd_reg_range rtd1625_main2_reg_ranges[] = {
+	{ .offset = 0x0,  .len = 0x50 },
+};
+
+static const struct rtd_pin_range rtd1625_main2_pin_ranges = {
+	.ranges = rtd1625_main2_reg_ranges,
+	.num_ranges = ARRAY_SIZE(rtd1625_main2_reg_ranges),
+};
+
+static const struct rtd_pinctrl_desc rtd1625_iso_pinctrl_desc = {
+	.pins = rtd1625_iso_pins,
+	.num_pins = ARRAY_SIZE(rtd1625_iso_pins),
+	.groups = rtd1625_iso_pin_groups,
+	.num_groups = ARRAY_SIZE(rtd1625_iso_pin_groups),
+	.functions = rtd1625_iso_pin_functions,
+	.num_functions = ARRAY_SIZE(rtd1625_iso_pin_functions),
+	.muxes = rtd1625_iso_muxes,
+	.num_muxes = ARRAY_SIZE(rtd1625_iso_muxes),
+	.configs = rtd1625_iso_configs,
+	.num_configs = ARRAY_SIZE(rtd1625_iso_configs),
+	.sconfigs = rtd1625_iso_sconfigs,
+	.num_sconfigs = ARRAY_SIZE(rtd1625_iso_sconfigs),
+	.pin_range = &rtd1625_iso_pin_ranges,
+};
+
+static const struct rtd_pinctrl_desc rtd1625_isom_pinctrl_desc = {
+	.pins = rtd1625_isom_pins,
+	.num_pins = ARRAY_SIZE(rtd1625_isom_pins),
+	.groups = rtd1625_isom_pin_groups,
+	.num_groups = ARRAY_SIZE(rtd1625_isom_pin_groups),
+	.functions = rtd1625_isom_pin_functions,
+	.num_functions = ARRAY_SIZE(rtd1625_isom_pin_functions),
+	.muxes = rtd1625_isom_muxes,
+	.num_muxes = ARRAY_SIZE(rtd1625_isom_muxes),
+	.configs = rtd1625_isom_configs,
+	.num_configs = ARRAY_SIZE(rtd1625_isom_configs),
+	.pin_range = &rtd1625_isom_pin_ranges,
+};
+
+static const struct rtd_pinctrl_desc rtd1625_ve4_pinctrl_desc = {
+	.pins = rtd1625_ve4_pins,
+	.num_pins = ARRAY_SIZE(rtd1625_ve4_pins),
+	.groups = rtd1625_ve4_pin_groups,
+	.num_groups = ARRAY_SIZE(rtd1625_ve4_pin_groups),
+	.functions = rtd1625_ve4_pin_functions,
+	.num_functions = ARRAY_SIZE(rtd1625_ve4_pin_functions),
+	.muxes = rtd1625_ve4_muxes,
+	.num_muxes = ARRAY_SIZE(rtd1625_ve4_muxes),
+	.configs = rtd1625_ve4_configs,
+	.num_configs = ARRAY_SIZE(rtd1625_ve4_configs),
+	.pin_range = &rtd1625_ve4_pin_ranges,
+};
+
+static const struct rtd_pinctrl_desc rtd1625_main2_pinctrl_desc = {
+	.pins = rtd1625_main2_pins,
+	.num_pins = ARRAY_SIZE(rtd1625_main2_pins),
+	.groups = rtd1625_main2_pin_groups,
+	.num_groups = ARRAY_SIZE(rtd1625_main2_pin_groups),
+	.functions = rtd1625_main2_pin_functions,
+	.num_functions = ARRAY_SIZE(rtd1625_main2_pin_functions),
+	.muxes = rtd1625_main2_muxes,
+	.num_muxes = ARRAY_SIZE(rtd1625_main2_muxes),
+	.configs = rtd1625_main2_configs,
+	.num_configs = ARRAY_SIZE(rtd1625_main2_configs),
+	.sconfigs = rtd1625_main2_sconfigs,
+	.num_sconfigs = ARRAY_SIZE(rtd1625_main2_sconfigs),
+	.pin_range = &rtd1625_main2_pin_ranges,
+};
+
+static int rtd1625_pinctrl_probe(struct platform_device *pdev)
+{
+	const struct rtd_pinctrl_desc *desc = device_get_match_data(&pdev->dev);
+
+	return rtd_pinctrl_probe(pdev, desc);
+}
+
+static const struct of_device_id rtd1625_pinctrl_of_match[] = {
+	{.compatible = "realtek,rtd1625-iso-pinctrl", .data = &rtd1625_iso_pinctrl_desc},
+	{.compatible = "realtek,rtd1625-isom-pinctrl", .data = &rtd1625_isom_pinctrl_desc},
+	{.compatible = "realtek,rtd1625-ve4-pinctrl", .data = &rtd1625_ve4_pinctrl_desc},
+	{.compatible = "realtek,rtd1625-main2-pinctrl", .data = &rtd1625_main2_pinctrl_desc},
+	{},
+};
+MODULE_DEVICE_TABLE(of, rtd1625_pinctrl_of_match);
+
+static struct platform_driver rtd1625_pinctrl_driver = {
+	.driver = {
+		.name = "rtd1625-pinctrl",
+		.of_match_table = rtd1625_pinctrl_of_match,
+		.pm = &realtek_pinctrl_pm_ops,
+	},
+	.probe = rtd1625_pinctrl_probe,
+};
+
+module_platform_driver(rtd1625_pinctrl_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Realtek Semiconductor Corporation");
+MODULE_DESCRIPTION("Realtek DHC SoC RTD1625 pinctrl driver");