KVM: SEV: Do cache maintenance on the source VM during intra-host migrationgrafted

Manually perform cache maintenance on the source VM during intra-host
migration to ensure no stale data is left in CPU caches after the VM is
destroyed.  Because the source VM is "converted" to a non-SEV VM, KVM's
memory reclaim flows won't trigger cache maintenance, e.g. when all guest
memory is reclaimed in response to detaching from the mmu_notifier.

Note, relying on the destination VM to do cache maintenance isn't an option
as KVM doesn't require identical guest memory configurations, i.e. the
source VM may have access to memory that the destination VM does not.
Enforcing equivalent memory configurations is infeasible, as it would
require a *deep* comparison of memslots, e.g. to verify that not only are
the memslot identical, but what the memslots point at is also identical.

Fixes: b56639318bb2 ("KVM: SEV: Add support for SEV intra host migration")
Cc: stable@vger.kernel.org
Reported-by: Stefan Teodorescu <fane@google.com>
Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-ID: <20260923163721.1584779-3-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

1 files changed, 92 insertions, 0 deletions

diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
new file mode 100644
index 000000000..1af4fc320
--- /dev/null
+++ b/drivers/pinctrl/meson/Kconfig
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-only
+menuconfig PINCTRL_MESON
+	tristate "Amlogic SoC pinctrl drivers"
+	depends on ARCH_MESON || COMPILE_TEST
+	depends on OF
+	default ARCH_MESON
+	select PINMUX
+	select PINCONF
+	select GENERIC_PINCONF
+	select GPIOLIB
+	select REGMAP_MMIO
+
+if PINCTRL_MESON
+
+config PINCTRL_MESON8
+	bool "Meson 8 SoC pinctrl driver"
+	depends on ARM || COMPILE_TEST
+	select PINCTRL_MESON8_PMX
+	default ARCH_MESON
+
+config PINCTRL_MESON8B
+	bool "Meson 8b SoC pinctrl driver"
+	depends on ARM || COMPILE_TEST
+	select PINCTRL_MESON8_PMX
+	default ARCH_MESON
+
+config PINCTRL_MESON_GXBB
+	tristate "Meson gxbb SoC pinctrl driver"
+	depends on ARM64 || COMPILE_TEST
+	select PINCTRL_MESON8_PMX
+	default ARCH_MESON
+
+config PINCTRL_MESON_GXL
+	tristate "Meson gxl SoC pinctrl driver"
+	depends on ARM64 || COMPILE_TEST
+	select PINCTRL_MESON8_PMX
+	default ARCH_MESON
+
+config PINCTRL_MESON8_PMX
+	tristate
+
+config PINCTRL_MESON_AXG
+	tristate "Meson axg Soc pinctrl driver"
+	depends on ARM64 || COMPILE_TEST
+	select PINCTRL_MESON_AXG_PMX
+	default ARCH_MESON
+
+config PINCTRL_MESON_AXG_PMX
+	tristate
+
+config PINCTRL_MESON_G12A
+	tristate "Meson g12a Soc pinctrl driver"
+	depends on ARM64 || COMPILE_TEST
+	select PINCTRL_MESON_AXG_PMX
+	default ARCH_MESON
+
+config PINCTRL_MESON_A1
+	tristate "Meson a1 Soc pinctrl driver"
+	depends on ARM64 || COMPILE_TEST
+	select PINCTRL_MESON_AXG_PMX
+	default ARCH_MESON
+
+config PINCTRL_MESON_S4
+	tristate "Meson s4 Soc pinctrl driver"
+	depends on ARM64 || COMPILE_TEST
+	select PINCTRL_MESON_AXG_PMX
+	default ARCH_MESON
+
+config PINCTRL_AMLOGIC_A4
+	bool "AMLOGIC pincontrol"
+	depends on ARM64 || COMPILE_TEST
+	default ARCH_MESON
+	help
+	  This is the driver for the pin controller found on Amlogic SoCs.
+
+	  This driver is simplify subsequent support for new amlogic SoCs,
+	  to support new Amlogic SoCs, only need to add the corresponding dts file,
+	  no additional binding header files or C file are added.
+
+config PINCTRL_AMLOGIC_C3
+	tristate "Amlogic C3 SoC pinctrl driver"
+	depends on ARM64 || COMPILE_TEST
+	select PINCTRL_MESON_AXG_PMX
+	default ARCH_MESON
+
+config PINCTRL_AMLOGIC_T7
+	tristate "Amlogic T7 SoC pinctrl driver"
+	depends on ARM64 || COMPILE_TEST
+	select PINCTRL_MESON_AXG_PMX
+	default ARCH_MESON
+
+endif