diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2026-09-20 10:43:12 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2026-09-20 10:43:12 -0700 |
| commit | 60ee24f055f87c74d3fccdedcb761df9253fd5c0 (patch) | |
| tree | 77b6835c8c1b44aece706f0bafa207dffc6f05db /drivers/phy/mediatek | |
| parent | 0a885f68d0e90dcef77e575b09104df7263e2aca (diff) | |
| parent | 486a70ef848264dcf9a57f0bb0452848db9537de (diff) | |
| download | linux-stable-60ee24f055f87c74d3fccdedcb761df9253fd5c0.tar.gz linux-stable-60ee24f055f87c74d3fccdedcb761df9253fd5c0.zip | |
Merge tag 'phy-fixes-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy fixes from Vinod Koul:
- avoid atomic context delay in renesas driver
- TMDS and PLL rate calculation fixes for mediatek driver
* tag 'phy-fixes-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
phy: mediatek: phy-mtk-hdmi-mt8195: Fix TMDS clk bit ratio setting
phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow
phy: renesas: rcar-gen3-usb2: Avoid long delay in atomic context
Diffstat (limited to 'drivers/phy/mediatek')
| -rw-r--r-- | drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 4 | ||||
| -rw-r--r-- | drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c index 1426a2db9..a4bc12689 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -36,7 +36,7 @@ mtk_phy_tmds_clk_ratio(struct mtk_hdmi_phy *hdmi_phy, bool enable) * clock bit ratio 1:40, under 3.4Gbps, clock bit ratio 1:10 */ if (enable) - mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, 3); + mtk_phy_update_field(regs + HDMI20_CLK_CFG, REG_TXC_DIV, VAL_TXC_DIV4); else mtk_phy_clear_bits(regs + HDMI20_CLK_CFG, REG_TXC_DIV); } @@ -290,7 +290,7 @@ static int mtk_hdmi_pll_calc(struct mtk_hdmi_phy *hdmi_phy, struct clk_hw *hw, posdiv2 = 1; /* Digital clk divider, max /32 */ - digital_div = div_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); + digital_div = div64_u64(ns_hdmipll_ck, posdiv1 * posdiv2 * pixel_clk); if (!(digital_div <= 32 && digital_div >= 1)) return -EINVAL; diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h index e26caaf4d..58800d765 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.h @@ -17,6 +17,9 @@ #define HDMI20_CLK_CFG 0x70 #define REG_TXC_DIV GENMASK(31, 30) +#define VAL_TXC_DIV2 1 +#define VAL_TXC_DIV4 2 +#define VAL_TXC_DIV8 3 #define HDMI_1_CFG_0 0x00 #define RG_HDMITX21_DRV_IBIAS_CLK GENMASK(10, 5) |
