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| author | Cheng Lingfei <chenglingfei@foxmail.com> | 2026-08-24 20:45:46 +0800 |
|---|---|---|
| committer | Tejun Heo <tj@kernel.org> | 2026-08-24 06:55:59 -1000 |
| commit | 909a3f0e9d8b0d8001cf6e99808f88eca8e44328 (patch) | |
| tree | be05d18bd5619b55ff3b30f28a292907021768ee /drivers/cache/Kconfig | |
| download | linux-stable-909a3f0e9d8b0d8001cf6e99808f88eca8e44328.tar.gz linux-stable-909a3f0e9d8b0d8001cf6e99808f88eca8e44328.zip | |
docs: cgroup-v2: fix misc.events key format descriptiongrafted
In misc cgroup, misc.events does not output a simple "max" key. Instead,
each registered misc resource outputs a separate key suffixed with ".max"
(i.e., "<res>.max").
Update the documentation to clarify that the entry key is "<res>.max".
Suggested-by: Michal Koutný <mkoutny@suse.com>
Signed-off-by: Cheng Lingfei <chenglingfei@foxmail.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/cache/Kconfig')
| -rw-r--r-- | drivers/cache/Kconfig | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig new file mode 100644 index 000000000..1518449d4 --- /dev/null +++ b/drivers/cache/Kconfig @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0 + +menuconfig CACHEMAINT_FOR_DMA + bool "Cache management for noncoherent DMA" + depends on RISCV + default y + help + These drivers implement support for noncoherent DMA master devices + on platforms that lack the standard CPU interfaces for this. + +if CACHEMAINT_FOR_DMA + +config AX45MP_L2_CACHE + bool "Andes Technology AX45MP L2 Cache controller" + select RISCV_NONSTANDARD_CACHE_OPS + help + Support for the L2 cache controller on Andes Technology AX45MP platforms. + +config SIFIVE_CCACHE + bool "Sifive Composable Cache controller" + depends on ARCH_SIFIVE || ARCH_STARFIVE + help + Support for the composable cache controller on SiFive platforms. + +config STARFIVE_STARLINK_CACHE + bool "StarFive StarLink Cache controller" + depends on ARCH_STARFIVE + depends on 64BIT + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS + help + Support for the StarLink cache controller IP from StarFive. + +endif #CACHEMAINT_FOR_DMA + +menuconfig CACHEMAINT_FOR_HOTPLUG + bool "Cache management for memory hot plug like operations" + depends on GENERIC_CPU_CACHE_MAINTENANCE + help + These drivers implement cache management for flows where it is necessary + to flush data from all host caches. + +if CACHEMAINT_FOR_HOTPLUG + +config HISI_SOC_HHA + tristate "HiSilicon Hydra Home Agent (HHA) device driver" + depends on (ARM64 && ACPI) || COMPILE_TEST + help + The Hydra Home Agent (HHA) is responsible for cache coherency + on the SoC. This drivers enables the cache maintenance functions of + the HHA. + + This driver can be built as a module. If so, the module will be + called hisi_soc_hha. + +endif #CACHEMAINT_FOR_HOTPLUG |